JPS6154546A - Memory access system - Google Patents

Abstract

PURPOSE:To speed up the memory accessing by sending an address from a CPU only in the first read of the memory contents and increasing addresses one by one at and after the second read of the memory contents. CONSTITUTION:A central processor 10 sends a memory address, the 1st read order and a name code of a peripheral device to a memory part 70 of a peripheral device 30 via a common bus 20. The 1st read order is discriminated by a control order discriminating part 103, and a memory address is set to an address register 100. This address is supplied to a register 300 via a gate 304, and the memory contents are suppied to a data register 101. At the same time, the contents of the register 300 are increased by 1. Then an end report signal is sent to the processor 10, and the memory contents are read out when the 2nd read order is received.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory access method for a peripheral processing unit connected to a central processing unit operating in a program mode in an information processing system.

(Prior Art) Conventionally, i! I! Read memory contents like hR! When performing a masterpiece, the central processing unit sends a read address and a read order as an instruction to the peripheral processing unit for each access.

(Problems to be solved by the invention) For peripheral processing devices! If the memory address is sent every time it is accessed, the overall read operation will take a long time, slowing down the operation speed, and the processing capacity of the central processing unit will decrease due to real-time processing. It was crowded.

An object of the present invention is to provide a first memory content read operation when a central processing unit successively executes a memory content read operation for a plurality of peripheral processing units connected to the central processing unit. This method eliminates the above drawback by executing all 7 operations of reading the memory contents without sending the memory address from the central processing unit to the peripheral processing unit only when the central processing unit sends the memory address to the peripheral processing unit after the second time. Another object of the present invention is to provide a memory access method that speeds up the read operation of memory contents.

Means for Solving Problem C) The memory access method according to the present invention is used in an information processing system consisting of a central processing unit and a plurality of peripheral processing units 1↑ connected to the central processing unit. be.

In the above, a plurality of peripheral processing units [in other words, an interface control unit, a processor, a control unit, a memory unit, and a memory address generation unit include an address register, a data register, and ,
11'', which includes a name code identification section, a control order identification section, and a memory address generation section.

The address register is for holding all addresses of the peripheral processing unit itself sent from the central processing unit.

The data register is for holding data stored in the memory section.

The name code detection section is for detecting a name code for identifying the peripheral processing bag itself.

The control order identification unit is for identifying an order for controlling a read operation in the peripheral processing device itself.

The memory address generation unit is for generating all memory addresses based on the addresses held in the address register.

In the memory access method according to the present invention, in the above-mentioned 4'1, when the control order identification unit identifies that the control order from the central processing unit is the first board order, the memory address sent from the central processing unit is This is to read from the memory section and perform nine rows, and conversely, when it is identified that it is the second order, the read is executed at an updated address incremented by 1 from the memory address.

(Example) Next, the present invention will be described in detail with reference to drawing f8.

Figure 1 shows a system book that applies the memory access method according to the present invention! - It is a block diagram showing one example of a configuration. Referring to Figure 1, 10 is the central processing unit, 30-32
are peripheral processing units, respectively, and 2o is a common bus, and the central processing unit 10 and peripheral processing units 30 to 32 are connected via a common bus. Further, 40 is an interface 1ilJ supra, 50 is a processor, 60 is a memory control unit, and 70 is a memory unit. In Figure 1, the interface controller 40 holds memory addresses and data sent from the central processing unit 10 via the common bus 20, and also identifies control orders and all peripheral processing units 30. identification of the name code. After receiving memory write/read requests from the interface control unit 40 and the internal processor 60 of the peripheral processing device 30, the memory control unit 50 controls write and read operations for the memory unit 70.

FIG. 2 is a block diagram showing the detailed configuration of the memory address generation section inside the interface control section 40. As shown in FIG.

In Figure 2, 100 is an address register, lo
t is a data register, 102 is a control order identification unit, 10
3 is a name code identification section, and 104 is a memory address generation section. FIG. 3 is a block diagram showing details of the memory address generation unit 1 (14) shown in the second I'''JK.

31i, 21st? 1. (00 is the address register, 301 is the 11ρ portion, 302 to 306 are the part) 1.;
7J is the gate.

In FIGS. 2 and 3, address register game 1 (
10 holds the exit address in the memory address generation unit 1()4. The double angle 5+j2os is for transmitting the output signal of the address register 100. 1
The peripheral processing unit G3
The order for controlling the atomizing operation to
Choose one item. The name code identification unit 103 identifies the peripheral processing device f? 3off Detect the name code for identification. The memory address generation unit xo4 holds an address to be sent to the memory unit 70. Memory address generator ■4
The register 300 inside the
When selected, the contents of the address register 100 are set, but when selected by the gate 302, the previous shift of the register 300, which has been increased by LJ by 1, is updated and set. The gate 306 performs an OR operation between the first number order and the memory access completion report (,').
? This is an OR gate for calculation.

Next, the memory access method according to the present invention will be explained with reference to FIGS. 1 to 3.

From the central processing unit 10 to the memory section 70 of the peripheral processing unit 30
When instructing to read the memory contents, the memory address, the first read order, and the name code of the peripheral processing device 30 are respectively sent via the common bus 20f. When the name code identification unit 103 determines that it is the own peripheral processing device 30, a match determination signal is sent out as an output on the signal line 200, and the control order identification unit 10
2 will be notified of this fact. When the first read order on the common bus 20 is identified by the control order identifying unit 102 that received the notification, the memory address on the signal 13201 is set in the address register 100. Then the first
The contents of the address register 100 are selected via the signal line 205 by the control signal on the signal line 203 which becomes NO when a read order is made.
It is input to register 800 via gate 304. When the control signal on the signal line 202, which becomes 1" at the time of the first grid order, is input to the gate 306, the address information on the signal line 30B is set in the register 300 by the control signal output to the signal line 307. Therefore, in order to issue a read operation instruction 4 to the memory control unit 60, the value of the read instruction signal on the signal line 208 becomes 1# and is sent. It is sent out on line 206.

Read data from the memory section 70 is input to the data register 101 via the signal line 207f, and when the memory read operation is completed, a control instruction is sent onto the signal line 204, thereby setting the data in the data register 101. Ru. At the same time, the contents of the register 300 inside the memory address generator 104 are incremented by one according to the control instruction on the signal line 204. For incremental operations, a signal is sent from gate 306 to signal line 307 via signal line 204 at the end of the read operation of the memory contents.
This is done by setting the incremented memory address selected by the gate 302 in the register 300 by the control (0'1 signal) on the 8 line 307. When the memory read 1h operation is completed, a completion report signal is sent to the central processing unit io. is sent to the common bus 20 via the signal line 209f.

When the first read order is read from the memory unit 70,
The central processing unit 1filo subsequently sends out a second grade order on the common bus 20 in order to carry out a mapping operation. The control order identification unit 102 identifies the second lead order'
Separating from fa, the read instruction signal on the signal-tdJ 208 is set to 1'' and sent to the memory control unit 60.

Therefore, the contents of the memory address generation unit 104 held at the end of execution of the first read order are sent out as a memory address via the signal line 206f. Below, the first
Similar to the glue order, the read data read from the memory section 70 and a report of the completion of memory reading while it is not active are sent to the central processing unit IO.

As explained above, according to the present invention, the central ear device i!
Are you being hit by ILC? (If the central processing unit continuously performs memory read operations for one device, the central processing unit only performs the first memory read operation.) There is no need to send the memory address (r-) for consecutive read operations after the 2152nd read operation, such as outputting memory addresses 7 and -3 of the device.

(Effects of the Invention) As explained above, according to the present invention, when the central processing unit continuously executes all memory read operations for a plurality of peripheral processing units connected to the central processing unit, the first By configuring the central processing unit to send the memory address to the peripheral m device only for the first memory read operation, and not to send the memory address for the second and subsequent consecutive read operations, it is possible to easily This has the effect of enabling high-speed memory access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an actual system configuration to which all the memory access methods according to the present invention are applied. FIG. 2 is a block diagram showing details of the peripheral part (interface in 5 devices: tl11 phloem) of FIG. 1. FIG. It is a block diagram showing iJ in detail. 10...Central processing unit (direct) 20...Common bus 30
~32...Peripheral processing bag is 40...Interface control unit 50...Processor 60...Memory control unit 70.
...Memory section 100...Address register 101
...Data register 102...Control order identification section 103...Name code identification section 104...Memory completion generation section 300...Register 301...Increment section 302
~306...Gate

Claims (1)

[Claims] A memory access method used in an information processing system comprising a central processing unit and a plurality of peripheral processing units connected to the central processing unit, wherein each of the plurality of peripheral processing units includes an interface control unit, a processor and , comprising a memory control unit and a memory unit, and the interface control unit includes an address register for holding an address of the peripheral processing unit itself sent from the central processing unit, and an address register for holding the address of the peripheral processing unit itself sent from the central processing unit, and a memory unit for reading data from the memory unit. a data register for holding data; a name code identification unit for detecting a name code for identifying the peripheral processing device itself; and a name code identification unit for identifying an order for controlling a read operation in the peripheral processing device itself. The control order identification unit includes a control order identification unit and a memory address generation unit for generating a memory address based on the address held in the address register, and the control order identification unit controls the control from the central processing unit. When the order is identified as the first read order, reading is executed from the memory section using the memory address sent from the central processing unit, and conversely, when the order is identified as the second read order, reading from the memory section is performed using the memory address sent from the central processing unit. A memory access method characterized in that it is realized by configuring to execute reading at an address updated by incrementing by 1 from the address.