JPS6153743A - Metal wiring of semiconductor device - Google Patents
Metal wiring of semiconductor deviceInfo
- Publication number
- JPS6153743A JPS6153743A JP17401184A JP17401184A JPS6153743A JP S6153743 A JPS6153743 A JP S6153743A JP 17401184 A JP17401184 A JP 17401184A JP 17401184 A JP17401184 A JP 17401184A JP S6153743 A JPS6153743 A JP S6153743A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- less
- stress
- width
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置、より詳しくは、半導体装置の金
属配線に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly to metal wiring for a semiconductor device.
IC,LSIなどの集積回路である半導体装置において
は、多数の能動素子(トランジスタ、ダイオード)およ
び受動素子(抵抗、キャノ4シタ)が半導体基板(例え
ば、シリコン基板)に形成され、これら素子が金属配線
によって所定回路を構成するように接続されている。In semiconductor devices, which are integrated circuits such as ICs and LSIs, a large number of active elements (transistors, diodes) and passive elements (resistors, capacitors) are formed on a semiconductor substrate (e.g., a silicon substrate), and these elements are made of metal. They are connected by wiring to form a predetermined circuit.
従来の技術および発明が解決しようとする問題点このよ
うな金属配線(特に、アルミニウム記報)は、高集積化
に伴ない配線幅も細くされ、その幅が3μm以下のもの
も形成されるようになってきた。Problems to be Solved by the Prior Art and the Invention The width of such metal wiring (particularly aluminum memory) is becoming narrower as the integration becomes higher, and wires with a width of 3 μm or less are being formed. It has become.
このように細い配線がM線で500 ltm以上の直線
部を有して所定接続のために走らせられることがある。Such thin wiring may have a straight section of 500 ltm or more as an M line and be run for a predetermined connection.
このような場合に、アルミニウム配線形成時にも配線自
身にストレス(特に、引張り応力)が生じ、さらに後工
程での熱処理(例えば、パッシペーシミン膜形成時の加
熱、”ッケーシングの封止時の加熱)などによって、ス
トレスが大きくなり、時としてアルミニウム結晶の界面
あるいはすべり面に沿った切断に至ることがある。In such cases, stress (particularly tensile stress) is generated on the wiring itself even when aluminum wiring is formed, and heat treatment in post-processes (e.g., heating when forming a passi-pecimin film, heating when sealing a casing), etc. As a result, the stress becomes large, sometimes leading to cutting along the interface or slip plane of the aluminum crystal.
問題点を解決するための手段
本発明は、上述の問題点を解消した半導体装置の配線を
捉供するものであって、半導体装置の金属配線において
配線幅が3μm以下でかつ直線部長さが500μm以上
となるようなところにはその途中にストレス緩和部を設
けることを特徴とする半導体装置の金属配線によって問
題点が予防される。Means for Solving the Problems The present invention provides a wiring for a semiconductor device that solves the above-mentioned problems, and the metal wiring of the semiconductor device has a wiring width of 3 μm or less and a straight line length of 500 μm or more. This problem can be prevented by metal wiring of a semiconductor device, which is characterized by providing a stress-reducing portion in the middle of the metal wiring where this occurs.
作用
金属配線でのストレス緩和部とは、(1) 185μm
以上でかつ長さ51rrn以上の拡張部分、(2) z
形状部分又は(3)多層配線構造での接続部分であって
、1ず直線部の長さを500/nn以下とすることによ
って、そしてこれらの部分の存在によって配線自身のス
トレスを弱めることができる。The stress relief part in the working metal wiring is (1) 185μm
(2) z
Shaped portions or (3) connecting portions in a multilayer wiring structure, first, by making the length of the straight portion 500/nn or less, and by the presence of these portions, the stress of the wiring itself can be weakened. .
実施し11
以下、添付図面を参照して本発明の好ましい実施態様例
によって本発明をより詳しく説明する。Embodiment 11 The present invention will now be described in more detail by way of preferred embodiments of the present invention with reference to the accompanying drawings.
第1図、第2図および第3図は、本発明に係る金属配線
を有する半導体装置の概略平面図である。1, 2, and 3 are schematic plan views of a semiconductor device having metal wiring according to the present invention.
第1図においては、アルミニウム配I?:’J I A
およびIBはその幅が31rrrL以下であジ、半導体
(シリコン)基板の所定領域と接触している’FJ’、
IiE部(例えげ、エミッタ雷極)2A、2Bと母線
(例えば、エミクタ供給電源ライン)3とを接続してい
る。In Figure 1, the aluminum arrangement I? :'JIA
and IB has a width of 31 rrrL or less and is in contact with a predetermined region of the semiconductor (silicon) substrate; 'FJ';
The IiE sections (for example, emitter lightning poles) 2A and 2B are connected to a bus bar (for example, an emitter supply power line) 3.
従来ならば、電極部2A 、2Bと母線3とを@繍的に
結ぶ配線を設けるところであるが、その距離が50〇−
以上である場合には、本発明にしたがって拡張部分4A
、4B、4Cおよび4Dが500μ以内のところに設け
られている。これら拡張部分はそれぞれ幅が51rnL
以上でありかつ長さが5μm以上であり、アルミニウム
配置191A、II3の一部分であって配線形成時のエ
ツチング用マスクツ4ターンを適切に変更するだけで通
常の工程にし之がって形成される。なお、第1図におい
ては配線の +1途中2ケ所に拡張部分が設け
られているが、配線の必要距離に応じて1ケ所あるいは
3ケ所以上に設けられる。また、不明1t(II寄書中
のアルミニウム配線はアツベニウム又はその合金(At
−8L 、At−Cu)で作られるものをいう。Conventionally, wiring would be provided to connect the electrode portions 2A, 2B and the bus bar 3 in a similar manner, but the distance would be 500 -
In this case, according to the present invention, the extended portion 4A
, 4B, 4C and 4D are provided within 500μ. Each of these extensions is 51rnL wide.
It has a length of 5 .mu.m or more, is a part of the aluminum arrangement 191A, II3, and is formed according to a normal process only by appropriately changing the four turns of the etching mask during wiring formation. In FIG. 1, extensions are provided at two locations along the +1 line of the wiring, but they may be provided at one or three or more locations depending on the required distance of the wiring. In addition, the aluminum wiring in the unknown 1t (II contribution) is atsubenium or its alloy (At
-8L, At-Cu).
本発明の別の実施態様である第2図に示したアルミニウ
ム配線21A、21Bはその途中に2形状部分24A
、24B 、24Cおよび24Dを有する。これら配線
21A、21Bは幅が3μm以下であり、電極部22A
、22Bから母線3までが500μ以上であって、配線
の直線部分が500μmよυも長くならないように同じ
配線幅の2形状部(曲がり部)24A〜24Dが設けら
れている。The aluminum wiring 21A, 21B shown in FIG. 2, which is another embodiment of the present invention, has a two-shaped portion 24A in the middle thereof.
, 24B, 24C and 24D. These wirings 21A and 21B have a width of 3 μm or less, and the electrode portion 22A
, 22B to the bus bar 3 is 500 μm or more, and two shaped portions (bent portions) 24A to 24D having the same wiring width are provided so that the straight line portion of the wire is not longer than 500 μm.
第1図での拡張部分4Aおよび4Dは2形状部とするこ
とをも苫んでいる。It is also difficult to make the expanded portions 4A and 4D in FIG. 1 into two-shaped portions.
さらに別の実施態様である第3図に示したアルミニウム
配線31A、31Bは多層配線構造を利用しており、上
側アルミニウム配線部分35A。In yet another embodiment, the aluminum interconnects 31A and 31B shown in FIG. 3 utilize a multilayer interconnect structure, with an upper aluminum interconnect portion 35A.
35B 、37A 、37Bと下側アルミニウム配線部
分36A、30B、38A、38Bとからなる。35B, 37A, 37B and lower aluminum wiring portions 36A, 30B, 38A, 38B.
そして、上′Qll+および下側のアルミニウム配線部
分の接続部分39A、39B、39C,39D。And connection parts 39A, 39B, 39C, 39D of the upper 'Qll+ and lower aluminum wiring parts.
39F、および39Fが層間絶縁膜(図示せず)に形成
されたコンタクトホールに作られる。この場合にも、ア
ルミニウム配線部分35A、35B〜38A、38Bそ
れぞれの幅は31t7n以下であジ、かつ長さは500
μm以下である。39F and 39F are formed in contact holes formed in an interlayer insulating film (not shown). Also in this case, the width of each of the aluminum wiring portions 35A, 35B to 38A, 38B is 31t7n or less, and the length is 500mm.
It is less than μm.
発明の効果
上述したように本発明に係る半導体装置の金属(アルミ
ニウム)配線においては、幅が3μm以下であるときに
は直線部分の長さを500μm以内にしかつストレス緩
和部を設けているので、配線自身に発生するストレスが
弱められてストレスによる切断が防止できる。このこと
は半導体装置の平均寿命を延ばすことになる。Effects of the Invention As mentioned above, in the metal (aluminum) wiring of the semiconductor device according to the present invention, when the width is 3 μm or less, the length of the straight portion is set to within 500 μm and the stress relief portion is provided, so that the wire itself The stress generated in the process is weakened and stress-induced cuts can be prevented. This will extend the average lifespan of the semiconductor device.
第1図、第2図および第3図は、本発明に係る金属配線
を有する半導体装置の部分概略断面図である。
IA、IB、21A、21B・・・配おメ、4A。
4B 、4C,4D・・・拡張部分、24A、24B。
24C,24D−Z形状部分、35A、37A(35B
、37B)・・・上(ti!lアルミニウム配線部分、
36A、38A(36B、38B)・・・下側アルミニ
ウム自己113部分。1, 2, and 3 are partial schematic sectional views of a semiconductor device having metal wiring according to the present invention. IA, IB, 21A, 21B... 4A. 4B, 4C, 4D...Extended portion, 24A, 24B. 24C, 24D-Z shape part, 35A, 37A (35B
, 37B)...Top (ti!l aluminum wiring part,
36A, 38A (36B, 38B)...lower aluminum self 113 part.
Claims (1)
下でかつ直線部長さが500μm以上となるようなとこ
ろにはその途中にストレス緩和部を設けることを特徴と
する半導体装置の金属配線。 2、前記金属配線がアルミニウム又はその合金であるこ
とを特徴とする特許請求の範囲第1項記載の配線。 3、前記ストレス緩和部が幅5μm以上で長さ5μm以
上の拡張部分であることを特徴とする特許請求の範囲第
1項又は第2項に記載の配線。 4、前記ストレス緩和部がZ形状部分であることを特徴
とする特許請求の範囲第1項又は第2項に記載の配線。 5、前記ストレス緩和部が多層配線構造での接続部分で
あることを特徴とする特許請求の範囲第1項又は第2項
に記載の配線。[Scope of Claims] 1. A semiconductor device characterized in that, in the metal wiring of the semiconductor device, a stress relief part is provided in the middle of the metal wiring where the wiring width is 3 μm or less and the straight line length is 500 μm or more. metal wiring. 2. The wiring according to claim 1, wherein the metal wiring is made of aluminum or an alloy thereof. 3. The wiring according to claim 1 or 2, wherein the stress relief portion is an extended portion having a width of 5 μm or more and a length of 5 μm or more. 4. The wiring according to claim 1 or 2, wherein the stress relief portion is a Z-shaped portion. 5. The wiring according to claim 1 or 2, wherein the stress relief part is a connection part in a multilayer wiring structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59174011A JP2599349B2 (en) | 1984-08-23 | 1984-08-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59174011A JP2599349B2 (en) | 1984-08-23 | 1984-08-23 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6153743A true JPS6153743A (en) | 1986-03-17 |
JP2599349B2 JP2599349B2 (en) | 1997-04-09 |
Family
ID=15971079
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59174011A Expired - Fee Related JP2599349B2 (en) | 1984-08-23 | 1984-08-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2599349B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6633346B1 (en) | 1999-02-04 | 2003-10-14 | Mitsubishi Denki Kabushiki Kaisha | Projection television |
US9490207B2 (en) | 2007-10-22 | 2016-11-08 | Rohm Co., Ltd. | Semiconductor device having a copper wire within an interlayer dielectric film |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4851258U (en) * | 1971-10-18 | 1973-07-04 | ||
JPS5283063A (en) * | 1975-12-29 | 1977-07-11 | Fujitsu Ltd | Production of semiconductor device |
JPS5827343A (en) * | 1981-08-10 | 1983-02-18 | Matsushita Electronics Corp | Semiconductor integrated circuit |
JPS58111347A (en) * | 1981-12-24 | 1983-07-02 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JPS58122749A (en) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-08-23 JP JP59174011A patent/JP2599349B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4851258U (en) * | 1971-10-18 | 1973-07-04 | ||
JPS5283063A (en) * | 1975-12-29 | 1977-07-11 | Fujitsu Ltd | Production of semiconductor device |
JPS5827343A (en) * | 1981-08-10 | 1983-02-18 | Matsushita Electronics Corp | Semiconductor integrated circuit |
JPS58111347A (en) * | 1981-12-24 | 1983-07-02 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JPS58122749A (en) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | Semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6633346B1 (en) | 1999-02-04 | 2003-10-14 | Mitsubishi Denki Kabushiki Kaisha | Projection television |
US9490207B2 (en) | 2007-10-22 | 2016-11-08 | Rohm Co., Ltd. | Semiconductor device having a copper wire within an interlayer dielectric film |
Also Published As
Publication number | Publication date |
---|---|
JP2599349B2 (en) | 1997-04-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |