JPS6152986B2 - - Google Patents

Description

[Detailed description of the invention] The present invention is a highly integrated ( LSI )
The present invention relates to semiconductor devices that are becoming increasingly integrated (integration), and particularly relates to a method of manufacturing a semiconductor device using a polycrystalline silicon (poly-Si) layer as an electrode or wiring. There have been remarkable advances in LSI technology in recent years, especially in MOS (Metal-Oxide-
In field effect transistor (FET) LSIs, the so-called Si gate technology, which uses poly-Si as the gate electrode and forms the source and drain in self-alignment, is making a big contribution. However, in order to achieve even higher levels of integration, there are several problems with conventional Si gate technology that must be resolved. Therefore, the conventional LSI n-channel
Taking the MOSFET manufacturing method as an example, Figure 1 a to h
The above problems will be explained with reference to. First, p-type Si basic 1 is prepared, and the p-type Si basic surface is selectively oxidized to form oxidized Si (SiO ₂ ) of about 1 μm.
A film 2 is formed (FIG. 1a). This oxidation process is a process for isolating elements, and this oxide film 2 is usually called a field oxide film. The field oxide film 2 is usually formed by selectively forming a silicon nitride (Si ₃ N ₄ ) film and thermally oxidizing the substrate using this as a mask. Next, the so-called exposed substrate surface on which the field oxide film 2 is not formed is oxidized to form a thin SiO 2 film 3 of about 700 Å, which will later become a gate oxide film, and the entire surface of this _{SiO 2 film} 3 is Then, a poly-Si layer 4 of about 3000 Å is formed by, for example, vapor phase growth (FIG. 1b). Thereafter, phosphorus (P) is diffused into the poly-Si layer 4 at about 1000° C. for about 10 minutes using, for example, trichlorophosphoric acid (POCl ₃ ) as a diffusion source (FIG. 1c). In this way, polySi
When phosphorus is diffused into the layer 4, the resistance of the poly-Si layer 4' becomes about 20 Ω/hole, as shown by the solid line in FIG. Thereafter, a photoresist film 5 is selectively formed on the phosphorus-doped poly-Si layer 4', and the poly-Si layer 4' is patterned by plasma etching using, for example, creon plasma, and later the gate electrode and A poly-Si layer 4' is left as a wiring (Fig. 1d). Next, the resist film 5 is removed and, for example, using the etched poly-Si layer 4' as a mask, As ions are implanted at 1×10 ¹⁵ /cm ² at 150 Kev in an N ₂ atmosphere at 1000° C., for example. Annealing is performed for about 1 hour to form source region 6 and drain region 7 (FIG. 1e). After the source region 6 and the drain region 7 are formed in this way, it contains about 1×10 ²¹ /cm ³ of phosphorus.
A SiO ₂ film, so-called PSG film 8, is formed on the entire surface with a thickness of about 1 μm.
This PSG film 8 is heat treated at a temperature of about 1050°C for 20 minutes to melt the PSG film surface, so-called reflow.
(Figure 1 f). Through this reflow, the PSG film 8
The surface becomes smooth, and the Al that will be formed later
There will be fewer breaks in the layers. After this, contact holes are opened to take out the electrodes of the source region 6 and drain region 7,
The Al layer 9 is formed on the entire surface by vapor deposition, and the Al layer 9 is formed into an arbitrary pattern 9 by ordinary photolithography.
a, 9b. _After this _, in order to obtain ohmic contact, for example, about 10
Sinter for a minute (Figure 1g). Next, a PSG film 10 with a thickness of, for example, about 1 μm is formed on the entire surface, and an electrode extraction portion is formed in the opening 1 in this PSG film 10.
0a and complete (Fig. 1 h). When manufacturing a MOSFET in this way, the resistance value of the poly-Si layer 4', which serves as the electrode and wiring, is approximately 20Ω/gate as described above, and this resistance value changes depending on the diffusion time of phosphorus. The result will be as shown by the solid line in Figure 2. As is clear from Fig. 2, the resistance decreases as the diffusion time increases, but it does not fall below about 20Ω/mouth. This is because the concentration of phosphorus in the poly-Si layer does not increase beyond its solid solubility. In addition, poly-Si layers are used as wiring and electrodes for transmitting signals in LSIs, and their resistance must be reduced as much as possible to reduce the operating speed of the device. For example, the thickness of the poly-Si layer is approximately 6000Å, which is twice the thickness of 3000Å.
When the thickness is increased, the resistance is approximately halved, but as the thickness increases, it becomes difficult to perform accurate patterning, and in particular, it cannot be used in the process of forming fine patterns. The present invention has been made in view of the above points, and provides a method for manufacturing a semiconductor device that can lower the resistance without increasing the thickness of the poly-Si layer and improve the operating speed of the element. be. That is, the present invention forms a metal layer on a semiconductor substrate and a poly-Si layer doped with impurities that will serve as an electrode or wiring, and then heat-treats the poly-Si layer, and then irradiates the poly-Si layer with laser light to reduce the resistance of the poly-Si layer. This is the manufacturing method. The present invention will be described below based on embodiments and with reference to the drawings. Figures 3a to 3i are process cross-sectional views showing one embodiment of the present invention, and are LSI-based n-channel
This is an example when applied to a MOSFET manufacturing method. First, as in the conventional method, a p-type Si substrate 11 is prepared, and this p-type Si substrate 11 is selectively oxidized to form a field oxide film 12 of about 1 μm (FIG. 3a). Thereafter, the poly-Si layer 14 is heated for about 10 minutes at about 1000°C using, for example, trichlorophosphoric acid (POCl ₃ ) as a diffusion source.
Diffuse phosphorus (P) for minutes (Figure 3c). When phosphorus is diffused into the poly-Si layer 14 in this way, the resistance of the poly-Si layer 14' increases to 20Ω/2, as shown in FIG.
Become a custodian. Thereafter, a photoresist film 15 is selectively formed on the phosphorus-doped poly-Si layer 14', and the poly-Si layer 14' is patterned by plasma etching using, for example, creon plasma, and later the gate electrode and A poly-Si layer 14' is left as a wiring (FIG. 3d). Next, the resist film 15 is removed and, for example, using the etched poly-Si layer 14' as a mask, As ions are implanted at 1×10 ¹⁶ /cm ² at 150 Kev in an N ₂ atmosphere at 1000° C., for example. Annealing is performed for about 1 hour to form a source region 16 and a drain region 17 (FIG. 3e). After the source region 16 and drain region 17 are formed in this manner, a SiO ₂ film containing phosphorus at a concentration of about 1×10 ²¹ /cm ^{3 ,} the so-called PSG film 18, is formed over the entire surface to a thickness of about 1 μm. Heat treatment is performed at a temperature of about 1050°C for 20 minutes to reflow the PSG film surface (Figure 3 f). By this reflow, the PSG film 18
The surface becomes smooth, and the Al that will be formed later
There will be fewer breaks in the layers. After this, the source region 16 and the drain region 17
Contact holes are opened for taking out the electrodes, and an Al layer 19 is formed by vapor deposition over the entire surface.The Al layer 19 is formed into arbitrary patterns 19a and 19b by ordinary photolithography. After this, in order to obtain ohmic contact, heat treatment (sintering) is performed for about 10 minutes in a forming gas (H ₂ :N ₂ =10% by volume: 90% by volume) atmosphere at, for example, 450°C (FIG. 3g). After patterning and heat-treating the Al layer 19 in this manner, a laser beam 30 is irradiated from the surfaces of the Al layers 19a and 19b and the surface of the PSG film 18 (FIG. 3h). Then, the laser beam 30 is irradiated onto the poly-Si layer 14' through the PSG film 18 other than the patterned Al layers 19a and 19b. The laser beam 30 used here was a pulsed laser beam, and an Nd-YAG laser device as shown in FIG. 4 with a maximum output of 10 W was used. And the laser light source 41 of this Nd-YAG laser device
The output light from the so-called laser beam 30 is bent by 90 degrees by a reflecting mirror 43 via a first lens 42, and then bent by a second lens 44 by about 40 μm to 80 μm.
Wafer 4 placed on stage 45
6 is irradiated. Furthermore, by scanning the stage 45 in the X direction and the Y direction, the polySi
The entire surface of the wafer 46 on which the layer has been formed can be irradiated. Also, the pulse width of the pulsed laser beam used here was 20
The time was μsec to 200 μsec, and the frequency was 5KHz to 30KHz. Al patterned in this way
After sintering the layers 19a and 19b, the poly-Si layer 14' is irradiated with a laser beam 30 through the PSG film 18, so that the resistance of the poly-Si layer 14' becomes the second level.
As shown by the dotted line in the figure, the resistance becomes about 1/2 of that before the laser beam 30 is irradiated, that is, about 10 Ω/hole, making it suitable for use as a gate electrode or wiring for this poly-Si layer 14'. Furthermore, as described later, the laser beam 3
In order to perform the irradiation of 0 after the sintering of the Al layers 19a and 19b, the poly-Si layer 1 is
4' resistance rarely increases. Next, a PSG film 10 having a thickness of, for example, about 1 μm is formed on the entire surface, and an electrode extraction portion is opened 10a in this PSG film 10 to complete the process (FIG. 3i). When a MOSFET is manufactured in this way, the resistance of the poly-Si layer 14' is as shown by the dotted line in FIG.
It can be seen that the value has decreased to about half of the value before irradiation with laser light 30 times. Although the detailed mechanism of this phenomenon has not yet been elucidated, the irradiation of the laser beam 30 activates the electrically inactive phosphorus, and at the same time changes the grain structure of the poly-Si layer, resulting in a change in the carrier. It is thought that mobility has also increased. Furthermore, when a poly-Si layer (approximately 3000 Å) is doped with As, the lowest resistance of approximately 30 Ω/hole can be obtained, but this can be further reduced to approximately half by irradiation with laser light. However, if a high temperature thermal process such as sintering of the Al layer is performed after irradiation with the laser beam 30, the resistance of the poly layer 30, which has decreased to about 1/2, increases by more than 10%. This results in a reduction in the operating speed of the device by about 10% or more. According to the present invention, since the laser beam irradiation is performed after the sintering of the Al layer is completed, the resistance of the poly-Si layer remains reduced to about 1/2 of its initial value, which is transmitted through the poly-Si layer. The signal propagation speed is approximately twice that of the conventional example. In addition, since there is no need to increase the thickness of the poly-Si layer in order to lower the resistance, there is no problem in microfabrication of the poly-Si layer, which is an excellent feature. Also, as shown in Figure 5, the resistance of the poly-Si layer is
It can be continuously changed by changing the output power of the laser beam. Therefore, after evaluating the characteristics of the completed LSI, in order to adjust the resistance of the poly-Si layer to an appropriate value, adjust the output of the laser light according to the results shown in Figure 5 to obtain the desired characteristics. is also possible. This application is
In particular, it can be applied to adjust the characteristics of poly-Si, which is used as a resistor in linear circuits using bipolar elements, by selectively irradiating it. In the above example, the laser light irradiation process was performed on Al
Although this step is carried out after sintering the layers, it may also be carried out, for example, after the last step, the so-called PSG film 20, is formed.
Further, the insulating layer formed on the poly-Si layer 30 is not limited to the PSG film, but may be a SiO ₂ film or a BSG film (boron-doped SiO ₂ film). Furthermore, in the above embodiment, when doping impurities into the poly-Si layer, the diffusion of phosphorus using _POcl3 as a diffusion source was described, but As or boron may also be used as the impurity, and solid phase diffusion or ion implantation can be used as the impurity introduction means. May be used. Furthermore, in the above embodiment, impurity doping into the poly-Si layer was performed separately from the formation of the source and drain regions, but impurities were doped into the poly-Si layer at the same time as forming the source and drain regions. You may do so. Further, in the above embodiment, a p-type Si substrate is used, but it may be an n-type Si substrate, and in this case, boron or the like is used as the impurity to be diffused. Furthermore, in the above embodiment, the n-channel
Although we have explained MOSFET, it can also be applied to CMOS and bipolar transistors.

[Brief explanation of the drawing]

Figure 1 a to h are process cross-sectional views showing the manufacturing process of an n-channel MOSFET, which is one of the conventional semiconductor devices. Figure 2 is a curve showing the resistance change of the poly-Si layer with respect to the diffusion time of phosphorus from _POcl3 . In the figure, the solid line is the conventional case, the dotted line is the case of the embodiment of the present invention, and Fig. 3 a to i are process cross-sectional views when applied to the manufacturing process of an n-channel MOSFET as an embodiment of the present invention. , FIG. 4 is a perspective view schematically showing the laser device for irradiating the laser beam in FIG. 3, and FIG. 5 is a curve diagram showing the resistance change of the poly-Si layer depending on the output of the laser beam. 11: p-type Si substrate, 12: field oxide film,
13: SiO ₂ film as gate oxide film, 14: PolySi
Layer 14': Phosphorus-doped poly-Si layer 1
5: Photoresist film, 16: Source region, 1
7: Drain region, 18: Reflowed PSG
Membranes 19a and 19b: patterned
Al layer, 20: PSG film, 20a: electrode extraction opening, 30: laser light.

Claims (1)

[Claims] 1. When manufacturing a semiconductor device using a polycrystalline silicon layer doped with impurities as an electrode or wiring, a metal layer connected to the polycrystalline silicon layer used as the electrode or wiring and the semiconductor substrate is formed. 1. A method of manufacturing a semiconductor device, comprising: irradiating at least a portion of the polycrystalline silicon layer with a laser beam after performing heat treatment. 2. The manufacturing method according to claim 1, wherein aluminum is used as the metal layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein aluminum containing silicon is used as the metal layer. 4. A method for manufacturing a semiconductor device according to the above claims, characterized in that the output of the laser beam is controlled and the resistance of the poly-Si layer is controlled.