JPS6151471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a framing synchronization signal generation circuit used for television teletext, etc., which generates a framing gate signal from a framing signal and stably extracts a framing synchronization signal regardless of the timing of generation of a horizontal synchronization signal. The purpose is to provide a circuit that can obtain

When performing teletext broadcasting, the transmitting side uses the vertical blanking period to transmit the burst signal ○B after the horizontal synchronization signal ○ _A1 and the next horizontal synchronization signal ○ _A2 , as shown in Figure 1, for example. A bit synchronization signal (C) for creating a sampling clock on the receiving side, which will be described later, and a framing signal with an error-correctable, for example, 8-bit code to distinguish character data signals from other signals. A and character data signal ○d are inserted in digital form and transmitted. On the receiving side, a sampling clock signal having a frequency twice that of the bit synchronization signal ○c is continuously obtained, and the character data signal from the transmitting side is read with high precision using the sampling clock signal. There is. In this case, the receiving side generates a framing synchronization signal before the arrival of the character data signal ○2, detects the arrival of the character data signal after this, and reads the character data signal ○2 more accurately.

FIG. 2 shows a conventional circuit diagram for obtaining the above-mentioned framing synchronization signal. In the same figure, the bit synchronization signal ○c, which comes in from input terminal 1 as a combination of "1" and "0", and the framing signal a (third
The character data signal ○d is supplied to the shift register 2, and is sequentially shifted by the clock signal b from the input terminal 3 (see Fig. 3B), and the character data signal c (see Fig. 3C) is supplied to the shift register 2. The signal is supplied to the framing code detector 4 at the timing of . The framing code detector 4 reads each of the codes A to H of the framing signal a, and when all the codes of the signal a are read, a detection signal d as shown in FIG. 2D is taken out in synchronization with the clock signal b. On the other hand, the horizontal synchronizing signal ○ _I1 inputted from the input terminal 5 is supplied to the framing gate signal generation circuit 6, and is delayed by a preset time by the monostable multivibrator provided here, and then is delayed by a predetermined width. The resulting framing code signal e (E in the figure) is supplied to the AND circuit 7 together with the output signal d of the framing code detector 4. Framing code detector 4 with AND circuit 7
The code detection signal d from the frame is ANDed with the framing gate signal e from the framing gate signal generation circuit 6, and a framing synchronization signal f (F in the figure) synchronized with the framing code detection signal is taken out from the output terminal 8. .

Here, generally, the horizontal synchronization signals ○ _i1 , ○ _i2 ,...
Since the timing of occurrence of ``() may be shifted due to noise components, it is necessary to set a wide pulse width of the framing gate signal e in order to reliably gate the code detection signal d of the framing code detector 4. However, if the pulse width of the framing gate signal e is made too wide, the framing signal a
If the generation timing of is shifted due to noise components, etc., the code detection signal generated by the final code of framing signal a becomes a false detection signal, and the framing synchronization signal is extracted by this false detection signal. This has the disadvantage that it is not possible to reliably synchronize the framing.

The present invention eliminates the above drawbacks, and the third
An example will be described below with reference to the drawings.

FIG. 3 shows a block system diagram of one embodiment of the framing synchronization signal generation circuit according to the present invention, in which the same components as in FIG. 2 are given the same numbers.
In the figure, 9 is a prediction circuit that constantly checks the output of the shift register 2, and when the code of the framing signal a is composed of N bits, all the codes of the framing signal a are output to the output of the shift register 2. The state 1 bit before the current state (i.e.,
(N-1) bit shifted state), then the next N
This circuit predicts that the framing code detection signal d will be detected when the second shift is executed, and takes out the output in advance, so that the signal from shift register 2 is output for (N-1) bits. The structure is such that a signal g as shown in FIG. 3G is taken out when the signal is detected. That is, the bits of the framing signal a are A, B, C, D, E, F, G, H.
(A is the last input bit), and the output data of shift register 2 is X ₁ , X ₂ , X ₃ ,
When X ₄ , X ₅ , X ₆ , X ₇ , X ₈ ( _{X 1 is} the last data output), when all of Output signal g is taken out when there is only disagreement.

On the other hand, the flip-flop 10 is brought into a reset state by the horizontal synchronizing signal ○ ₁ from the input terminal 5, and a signal j as shown in FIG. 3J is taken out from the Q terminal. As a result, the output g of the prediction circuit 9 and the output j of the flip-flop 10 are ANDed in the AND circuit 11 and the output is taken out.
A framing gate signal h as shown in FIG. In the AND circuit 7, the output d of the framing code detector 4 and the output h of the D-flip-flop 13 are ANDed, and a signal i as shown in FIG. 3I is taken out from the output terminal 8 as a framing synchronization signal. Signal i is applied to flip-flop 10 to set it. By setting the flip-flop 10, the output of the AND circuit 11 disappears, and the framing gate signal h disappears. Therefore, in FIG. Even if there are similar combinations, the framing synchronization signal will not be taken out from the output terminal 8 by mistake.

Note that since the prediction circuit 9 is actually constructed of a circuit that can be used in common with the framing code detection circuit 4, it can be constructed with less space and at low cost.

As described above, the framing synchronization signal generation circuit according to the present invention detects the framing code when the code of the framing signal is shifted by 1 bit from the output of the shift register at a time point 1 bit before the entire code of the framing signal is output from the shift register. Since the framing gate signal is obtained by predicting that the signal may be detected, the horizontal synchronization signal cannot be detected unlike the conventional circuit that uses a monostable multivibrator to obtain the framing gate signal from the horizontal synchronization signal. There is no need to widen the pulse width of the framing gate signal in consideration of the deviation, and therefore, even if the timing of the generation of the framing signal is shifted due to noise components, etc., the false framing code is not generated before the framing gate signal as in the conventional method. The detection signal is not extracted, so there is no malfunction, and there is no need for a monostable multivibrator to obtain the framing gate signal, so the circuit can be easily configured and no adjustment is required. It has the following features.

[Brief explanation of the drawing]

Fig. 1 is a transmission signal waveform diagram used in television teletext broadcasting, Fig. 2 is a block system diagram of an example of a conventional framing synchronization signal generation circuit, and Figs. 3 A to J.
4 is a signal waveform diagram for explaining the operation of the conventional circuit and the circuit of the present invention, and FIG. 4 is a block system diagram of an embodiment of the framing synchronization signal generating circuit according to the present invention. 1...Input terminal, 2...Shift register, 3...
...Clock signal input terminal, 4...Framing code detector, 5...Horizontal synchronization signal input terminal, 8...
...Framing synchronization signal output terminal, 9...Prediction circuit, 10...Flip-flop, 13...D-flip-flop.

Claims (1)

[Claims] 1. A shift register that sequentially shifts and extracts a plurality of binarized data having a predetermined combination;
a detector that is supplied with the output of the shift register and detects the final code of the framing signal data having a plurality of codes in the data to extract a framing code detection signal, and for gating the framing code detection signal. A framing synchronization signal generation circuit that takes out a framing synchronization signal at a time point when the framing gate signal matches is supplied with the output of the shift register, and a predetermined number of codes of the framing signal are all output from the shift register. a prediction circuit that extracts a framing gate signal of a predetermined time width by predicting that the above-mentioned framing code detection signal is likely to be detected when the signal is shifted by one bit next at a point in time one bit before; 1. A framing synchronization signal generating circuit comprising: a circuit for logically multiplying the output and the output of the framing code detector to extract the framing synchronization signal.