JPS6150347A - Forming process of contact hole - Google Patents
Forming process of contact holeInfo
- Publication number
- JPS6150347A JPS6150347A JP17290584A JP17290584A JPS6150347A JP S6150347 A JPS6150347 A JP S6150347A JP 17290584 A JP17290584 A JP 17290584A JP 17290584 A JP17290584 A JP 17290584A JP S6150347 A JPS6150347 A JP S6150347A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- contact hole
- film
- hole
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title abstract description 16
- 238000001020 plasma etching Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012528 membrane Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置に形成されるコンタクトホールの形
成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for forming contact holes in semiconductor devices.
（ロ）従来の技術
半導体装置において、絶縁膜にコンタクトホールを形成
するには、まず光蝕刻法によって絶縁膜の上にレジスト
のマスクを形成し、次ニコノマスクの上から反応性イオ
ンエツチング（以下、ＲＩＥと略称する。）を行ってい
た。ところが、このようなコンタクトホールの形成方法
では、形成されたコンタクトホールは急峻な形状を示し
ていた。(b) Conventional technology In order to form a contact hole in an insulating film in a semiconductor device, a resist mask is first formed on the insulating film by photolithography, and then reactive ion etching (hereinafter referred to as (abbreviated as RIE). However, in this method of forming a contact hole, the formed contact hole has a steep shape.
このため、コンタクトホールに形成される金属配線に断
線、剥離が生じやすく、半導体装置の信頼性を低下させ
ていた。Therefore, the metal wiring formed in the contact hole is likely to be disconnected or peeled off, reducing the reliability of the semiconductor device.
そこで、このような欠点を無くすためにコンタクトホー
ルをテーパー加工する方法が、ラウンドエツチング法と
いう名称で電子通信学会技術研究報告５５０８２−４８
に提案されている。Therefore, in order to eliminate such defects, a method of tapering the contact hole is called the round etching method and is published in Technical Research Report 55082-48 of the Institute of Electronics and Communication Engineers.
has been proposed.
このラウンドエツチング法は、まず絶縁膜上のレジスト
膜をマスクとして、たとえばＣＦ４とＨ２との混合ガス
を用いて、通常のＲＩＫにより急峻なコンタクトホール
を形成する。そして、次にレジスト膜を取り除いた後に
、Ｃ３ＦａとＨ２との混合ガスを使用したｉｌＫによっ
て、前記コンタクトホールをテーパー加工するものであ
る。しかるに、このとき使用する０３１＠とＨ２との混
合ガスはコンタクトホールの角を取るものであって、最
初のＲＩＨにおいてはこのＣ３ＦＢとＮ２との混合ガス
を使用することができない。In this round etching method, a steep contact hole is first formed by ordinary RIK using a resist film on an insulating film as a mask and using a mixed gas of, for example, CF4 and H2. Then, after removing the resist film, the contact hole is tapered using ilK using a mixed gas of C3Fa and H2. However, the mixed gas of 031@ and H2 used at this time takes the corners of the contact hole, and this mixed gas of C3FB and N2 cannot be used in the first RIH.
ｅ→ 発明が解決しようとする問題点
前述のラウンドエツチング法によると、ＲＩＥをレジス
ト膜の除去前と除去後とで合せて２回行わねばならなか
った。しかも、１回目のＲＩＥで使用するガスと、２回
目のＲＩＥで使用するガスとは夫々異なるものであるの
で、工程が複雑であり、煩わしかった。e→ Problems to be Solved by the Invention According to the round etching method described above, RIE had to be performed twice: before and after the removal of the resist film. Moreover, since the gas used in the first RIE and the gas used in the second RIE are different, the process is complicated and troublesome.
ｉ、？−）問題点を解決するための手段本発明は絶縁膜
の上にレジスト膜を形成する工程と、このレジスト膜に
コンタクトホール形成用の孔を形成する工程と、レジス
ト膜を昇温し前記孔をテーパー加工する工程と、レジス
ト膜の上から反応性イオンエツチングを行ってレジスト
膜と前記絶縁膜とを同時にエツチングする工程とを備１
′″・′“（７）ＭＥ’；ｆ４．ｊｃ”ｊ６ｔ
６！＄９１ｃ、−ｔ＜ ＠状を有するコンタクトホール
を形成することを特徴とするｐンタクトホールの形成方
法である。i,? -) Means for Solving Problems The present invention includes a step of forming a resist film on an insulating film, a step of forming a hole for forming a contact hole in this resist film, and a step of heating the resist film to form a contact hole. and a step of etching the resist film and the insulating film simultaneously by performing reactive ion etching from above the resist film.
′″・′”(7) ME'; f4. jc"j6t
6! This is a method for forming a p-tact hole characterized by forming a contact hole having a shape of $91c, -t<@.
−）作用
本発明は、レジスト膜を昇温することニヨッテ、レジス
ト膜に形成された急峻な孔をテーパー形状にし、次にレ
ジスト膜と絶縁膜とを同時にＲＩＥにてエツチングする
ことによって、前記孔のテーパー形状を絶縁膜に伝える
ものである。したがって、絶縁膜番こはテーパー形状の
コンタクトホールが形成される。-) Effect The present invention is capable of etching the holes by heating the resist film, making the steep holes formed in the resist film into a tapered shape, and then etching the resist film and the insulating film at the same time by RIE. The tapered shape is transmitted to the insulating film. Therefore, a tapered contact hole is formed in the insulating film.
（へ）実施例
、第１図は本発明が実施されている半導体装置の部分断
面図である。この図に奢いて、（１）はシリコン基板、
（２）はこのシリコン基板（１）の上に形成されたＮ１
の３４０２膜、（３）はこの第１の８４０２膜（２）の
上に選択的に形成された下層配線であって、この下層配
線（３）は導電性のポリシリコンで形成される。(f) Embodiment FIG. 1 is a partial sectional view of a semiconductor device in which the present invention is implemented. In this figure, (1) is a silicon substrate,
(2) is the N1 formed on this silicon substrate (1).
The 3402 film (3) is a lower wiring selectively formed on the first 8402 film (2), and the lower wiring (3) is made of conductive polysilicon.
（４）は下層配線（３）を覆うように形成された絶縁膜
としての第２の８１０２膜である。なお、第２の３４０
２膜（４）の上にはＡＩ！等による上層配線（図示せず
）がなされる。（５）は上層配線と下層配線（３）との
コンタクトをとるためのテーパー形状のフンタクトホー
ルである。(4) is a second 8102 film as an insulating film formed to cover the lower layer wiring (3). In addition, the second 340
AI on the 2nd membrane (4)! Upper layer wiring (not shown) is made by etc. (5) is a tapered contact hole for making contact between the upper layer wiring and the lower layer wiring (3).
次に、上述の半導体装置に形成されているコンタクトホ
ール（５）の形成方法について、第２図ないし第５図に
もとづいて説明する。Next, a method for forming the contact hole (5) formed in the above-mentioned semiconductor device will be explained based on FIGS. 2 to 5.
まず第２図において、第２の５ｉ０２膜（４）の上にホ
トレジストＡＺ１３５０Ｊ（商品名）を塗布し、これを
プリベークすることによってレジスト膜（６）を形成す
る。次に、このレジスト膜（６）を通常の光蝕刻法によ
って露光、現像し、第３図に示すようにコンタクトホー
ル形成用の孔（７）を形成する。な詔、このときレジス
ト膜（６）にあけられた孔（７）は急峻な形状を呈する
。First, in FIG. 2, a photoresist AZ1350J (trade name) is applied on the second 5i02 film (4) and prebaked to form a resist film (6). Next, this resist film (6) is exposed and developed by a conventional photoetching method to form a hole (7) for forming a contact hole, as shown in FIG. In this case, the hole (7) made in the resist film (6) has a steep shape.
次に、レジスト膜（６）を１５０℃でポストベークする
ことによって、前記孔（７）の角にまるみを持たせ、孔
７を第４図に示すよ引こテーパー加ヱする。Next, by post-baking the resist film (6) at 150° C., the corners of the holes (7) are rounded and the holes 7 are tapered as shown in FIG.
このようにＡＺ１３５０Ｊによるレジスト膜（６）は適
度に昇温されることによってやわらかくなり、角ばった
部分はまるみを持つように変形する。As described above, the resist film (6) made of AZ1350J becomes soft when the temperature is appropriately raised, and the angular portions are deformed into rounded shapes.
次に、テーパー形状の孔（７）が形成されているレジス
ト膜（６）の上から ＣＦ４と０２との混合比が９６：
４の混合ガスを使ってＲＩＥ−を行う。このとき上記混
合ガスは、レジスト膜（６）と第２の５ｉ０２膜（４）
との露出部を等しいエヅチングレートで同時にエツチン
グする。すると、第５図に示すようにレジスト膜（６）
の孔（７）のテーパー形状がＷＳ２の５１０２膜（４）
に伝えられ、第２のＳｉｏ２膜（４）にテーパー形状の
コンタクトホール（５）が形成される。なお、第２のＳ
ｉＯ２膜（４）およびレジスト膜（６）の膜厚は、適宜
に決定することができるう
（ト）発明の効果
本発明はレジスト膜を昇温しでレジスト膜の孔をテーパ
ー加工し、このレジスト膜の上からレジスト膜と絶縁膜
との露出部をＲＩ Ｆ、によって同時にエツチングする
だけで、テーパー形状のコンタクトホールを前記絶縁膜
に容易に形成することができる。Next, from above the resist film (6) in which the tapered holes (7) are formed, the mixing ratio of CF4 and 02 is 96:
Perform RIE- using the mixed gas of step 4. At this time, the mixed gas is applied to the resist film (6) and the second 5i02 film (4).
At the same time, the exposed parts are etched at the same etching rate. Then, as shown in FIG. 5, the resist film (6)
The tapered shape of the hole (7) is WS2 5102 membrane (4)
A tapered contact hole (5) is formed in the second Sio2 film (4). Note that the second S
The film thicknesses of the iO2 film (4) and the resist film (6) can be appropriately determined. A tapered contact hole can be easily formed in the insulating film by simply etching the exposed portions of the resist film and the insulating film from above the resist film at the same time using RIF.
第１図は本発明が実施されている半導体装置の部分断面
図、第２図ないし１５図は本発明の一実施例の工程説明
である。
（４）・・・Ｓｉｏ２膜（絶縁膜）、（５）・・・コン
タクトホール。（６）・・・レジスト膜、（７）・・・
孔。FIG. 1 is a partial sectional view of a semiconductor device in which the present invention is implemented, and FIGS. 2 to 15 are process explanations of one embodiment of the present invention. (4)...Sio2 film (insulating film), (5)...contact hole. (6)...Resist film, (7)...
Hole.
Claims (1)
レジスト膜にコンタクトホール形成用の孔を形成する工
程と、レジスト膜を昇温し前記孔をテーパー加工する工
程と、レジスト膜の上から反応性イオンエッチングを行
つてレジスト膜と前記絶縁膜とを同時にエッチングする
工程とを備え、絶縁膜の前期孔に対応する部分にテーパ
ー形状を有するコンタクトホールを形成することを特徴
とするコンタクトホールの形成方法。(1) A step of forming a resist film on the insulating film, a step of forming a hole for forming a contact hole in this resist film, a step of increasing the temperature of the resist film and tapering the hole, and a step of forming a resist film on the resist film. A contact comprising the step of simultaneously etching the resist film and the insulating film by performing reactive ion etching from above, and forming a contact hole having a tapered shape in a portion of the insulating film corresponding to the first hole. How to form a hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17290584A JPS6150347A (en) | 1984-08-20 | 1984-08-20 | Forming process of contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17290584A JPS6150347A (en) | 1984-08-20 | 1984-08-20 | Forming process of contact hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6150347A true JPS6150347A (en) | 1986-03-12 |
Family
ID=15950514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17290584A Pending JPS6150347A (en) | 1984-08-20 | 1984-08-20 | Forming process of contact hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6150347A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008066059A1 (en) * | 2006-11-30 | 2008-06-05 | Kabushiki Kaisha Toshiba | Semiconductor device and semiconductor device manufacturing method |
-
1984
- 1984-08-20 JP JP17290584A patent/JPS6150347A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008066059A1 (en) * | 2006-11-30 | 2008-06-05 | Kabushiki Kaisha Toshiba | Semiconductor device and semiconductor device manufacturing method |
| US7749901B2 (en) | 2006-11-30 | 2010-07-06 | Kabushiki Kaisha Toshiba | Method for forming a tapered via of a semiconductor device |
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