JPS59194472A - Forming method of gate oxidized film - Google Patents
Forming method of gate oxidized filmInfo
- Publication number
- JPS59194472A JPS59194472A JP6950283A JP6950283A JPS59194472A JP S59194472 A JPS59194472 A JP S59194472A JP 6950283 A JP6950283 A JP 6950283A JP 6950283 A JP6950283 A JP 6950283A JP S59194472 A JPS59194472 A JP S59194472A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- substrate
- oxidized
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はゲート酸化膜の形成方法、特に異なる厚みを有
するゲート酸化膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for forming a gate oxide film, and particularly to a method for forming gate oxide films having different thicknesses.
（ロ）従来技術
最近のＭＯ８ＩＣでは動作速度の高速化、大規模集積化
、低消費電力化の要求があり、ＩＣを構成するＭＯＳト
ランジスタの徽細化が急務となっている。この一方法と
して選択酸化技術が挙げられる。(b) Prior Art Recent MO8ICs are required to have higher operating speeds, larger scale integration, and lower power consumption, and there is an urgent need to make the MOS transistors that make up the ICs finer. One such method is selective oxidation technology.
第１図Ａ〜第１図Ｅを参照して選択酸化技術を説明する
。第１図Ａでは、Ｐ型シリコン基板（１）の表面に薄（
パッド酸化膜（２）を形成した後素子形成領域（３）上
を選択的にシリコン窒化膜（４）を減圧ｃＶＤ法により
付着する。The selective oxidation technique will be explained with reference to FIGS. 1A to 1E. In Figure 1A, a thin (
After forming the pad oxide film (2), a silicon nitride film (4) is selectively deposited on the element formation region (3) by low pressure CVD method.
第１図Ｂでは、シリコン窒化膜（４）をマスクとして１
１００．’Ｃの水蒸気雰囲気中で熱酸化処理を施して厚
さ約１趨の埋め込みフィールド酸化膜（５）を形成する
。なお本工程ではフィールド酸化膜（５）の形成中にパ
ッド酸化膜（２）のピンホールやその周端の基板（１）
表面にホワイトリボンあるいはホワイトスポットと呼ば
れるシリコン窒化物の析出物（６）が形成され、ゲート
酸化時の障害となるので除去する必要がある。In FIG. 1B, the silicon nitride film (4) is used as a mask.
100. A buried field oxide film (5) having a thickness of about 1 line is formed by thermal oxidation treatment in a water vapor atmosphere of 'C. Note that in this step, during the formation of the field oxide film (5), pinholes in the pad oxide film (2) and the substrate (1) around the pinholes are removed.
A silicon nitride precipitate (6) called a white ribbon or white spot is formed on the surface and must be removed because it becomes an obstacle during gate oxidation.
第１図Ｃでは、シリコン窒化膜（４）およびパッド酸化
膜（２）をエツチング除去する。この際に析出物（６）
は除去できない。In FIG. 1C, the silicon nitride film (4) and pad oxide film (2) are removed by etching. At this time, precipitate (6)
cannot be removed.
第１図りでは、基板（１）表面を犠牲酸化し、析出物（
６）も酸化する。犠牲酸化は１０００℃のドライ０２で
行い、５００〜２００ＯＡ厚の犠牲酸化膜（力を形成す
る。In the first drawing, the surface of the substrate (1) is sacrificially oxidized, and the precipitates (
6) is also oxidized. Sacrificial oxidation is performed in dry 02 at 1000° C. to form a sacrificial oxide film with a thickness of 500 to 200 OA.
第１図Ｅでは、この犠牲酸化膜（７）をエツチング除去
し、同時に析出物（６）も除去す唇にの結果ゲート酸化
時に問題となる析出物（６）は完全に除去でき、続いて
所望の厚みのゲート酸化膜を形成している。In Figure 1E, as a result of etching away this sacrificial oxide film (7) and removing the precipitates (6) at the same time, the precipitates (6), which pose a problem during gate oxidation, can be completely removed. A gate oxide film of desired thickness is formed.
指上した犠牲酸化により極めて薄いゲート酸化膜が安定
に形成されそれを用いたＭＯＳ）ランジスタのゲート耐
圧も均一化できる。Through the sacrificial oxidation, an extremely thin gate oxide film is stably formed, and the gate breakdown voltage of a MOS transistor using it can be made uniform.
しかしながら最近のＭＯ８ＩＣでは同一チップ内にゲー
ト耐圧の異なるＭＯＳ）ランジスタを集積化する要望が
ある。すなわち入出力用のＭＯＳトランジスタは外部回
路との結合を行うので高耐圧を要求されるのである。However, in recent MO8ICs, there is a demand for integrating MOS transistors with different gate breakdown voltages in the same chip. That is, input/output MOS transistors are required to have a high breakdown voltage since they are coupled to external circuits.
（ハ）発明の目的
本発明は指点に鑑みてなされ、犠牲酸化膜を利用するこ
とにより同一工程で異なる膜厚のゲート酸化膜を同時に
形成することを目的とする。(c) Purpose of the Invention The present invention has been made in view of the point of view, and an object of the present invention is to simultaneously form gate oxide films of different thicknesses in the same process by using a sacrificial oxide film.
に）発明の構成
本発明は第２図Ａ−Ｅの如く、以下の工程より構成され
ている。B) Structure of the Invention The present invention is comprised of the following steps as shown in FIGS. 2A to 2E.
（１）半導体基板Ｑｌｊ上にパッド酸化膜αりを介して
選択的に選択酸化マスク層ａ優を付着する工程。(1) Step of selectively depositing a selective oxidation mask layer a on the semiconductor substrate Qlj via the pad oxide film α.
（２）基板住１）にその一部を埋め込んだ厚いフィール
ド酸化膜Ｑ５）を形成する工程。(2) Step of forming a thick field oxide film Q5) partially buried in the substrate layer 1).
（３）基板（１１１表面を犠牲酸化する工程。(3) Step of sacrificial oxidation of the substrate (111 surface).
（４）基似Ｑ］）表面の犠牲酸化膜（１′７）を選択的
に除去する工程。(4) Base Q]) Step of selectively removing the sacrificial oxide film (1'7) on the surface.
（５）基板（１１）表面をゲート酸化して異なる膜厚の
ゲート酸化膜（１９を形成する工程。(5) A step of gate oxidizing the surface of the substrate (11) to form gate oxide films (19) of different thicknesses.
（ホ）実施例
本発明の一実施例を第２図Ａ乃至第２図Ｅを参照して詳
述する。(E) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2E.
本発明の第１の工程は半導体基板（１１）上にパッド酸
化膜ａりを介して選択的に選択酸化マスク層Ｉを付着す
ることにある（第２図Ａ）。すなわち比抵抗２Ω、ｃＩ
ＩＬのＰ型シリコン基板Ｑｌ）表面全面に熱酸化により
約７０ＯＡの薄いパッド酸化膜ａ２を形成し、その上に
約７０ＯＡ厚のシリコン窒化物Ｑ４）を減圧ＣＶＤ法に
より付着する。シリコン窒化膜ａ４は周知のホトエツチ
ングにより素子形成領域Ｑ３上忙選択的に残し、選択酸
化マスク層α荀とする。The first step of the present invention consists in selectively depositing a selective oxidation mask layer I on a semiconductor substrate (11) via a pad oxide film (FIG. 2A). That is, specific resistance 2Ω, cI
A thin pad oxide film a2 of about 70 OA is formed on the entire surface of the IL P-type silicon substrate Ql) by thermal oxidation, and silicon nitride Q4) of about 70 OA thick is deposited thereon by low pressure CVD. The silicon nitride film a4 is selectively left on the element forming region Q3 by well-known photoetching, and is used as a selective oxidation mask layer α.
本発明の第２の工程は半導体基板（１１）＆Ｃその一部
を埋め込んだ厚いフィールド酸化膜ミツを形成すること
にある（第２図Ｂ）。選択酸化は酸化雰囲気中で行なわ
れ、選択酸化マスク層α荀のない基板（１１）表面に約
１μｍの厚いフィールド酸化膜を形成する。この構造は
周知のＬＯＣＯ８構造を構成する。The second step of the present invention consists in forming a thick field oxide layer that embeds a portion of the semiconductor substrate (11) (FIG. 2B). Selective oxidation is performed in an oxidizing atmosphere to form a thick field oxide film of about 1 μm on the surface of the substrate (11) without the selective oxidation mask layer α. This structure constitutes the well-known LOCO8 structure.
なお本工程では選択酸化処理中にパッド酸化膜αりのビ
ーンホールやその周端の基板（１１１表面にホワイトリ
ボンあるいはホワイトスポットと呼ばれるシリコン窒化
物の析出物αｅが形成され、ゲート酸化一時の障害とな
り除去する必要がある。更に本工程では選択酸化マスク
層Ｉおよびパッド酸化膜ａ２をエツチング除去し、基板
（１１）の素子形成領域側を露出する。このときホワイ
トリボンあるいはホワイトスポット等の析出物ｔｔｅは
除去できない。In addition, during the selective oxidation process in this process, silicon nitride precipitates αe, called white ribbons or white spots, are formed on the bean hole in the pad oxide film α and on the substrate (111) surface at the peripheral edge thereof, which may cause a temporary hindrance during gate oxidation. Further, in this step, the selective oxidation mask layer I and the pad oxide film a2 are removed by etching to expose the element forming area side of the substrate (11).At this time, precipitates such as white ribbons or white spots are removed by etching. tte cannot be removed.
本発明の第３の工程は半導体基板Ｑｌ）表面を犠牲酸化
すること。（ある（第２図Ｃ）。犠牲酸化は約１０００
℃でドライ０．雰囲気で行い、５ｏｏ〜２０００Ａの犠
牲酸化膜ａηを基板α１）の素子形成領域０３表兜に形
成する。この結果前述した析出物（Ｉ６）も犠牲酸化膜
より基板αＩ）表面より分離される。The third step of the present invention is sacrificial oxidation of the surface of the semiconductor substrate Ql). (There is (Figure 2C).Sacrificial oxidation is about 1000
Dry at 0°C. A sacrificial oxide film aη of 500 to 2000 Å is formed on the surface of the element formation region 03 of the substrate α1). As a result, the aforementioned precipitate (I6) is also separated from the surface of the substrate αI) by the sacrificial oxide film.
本発明の第４の工程は半導体基板０．１）表面の犠牲酸
化腹鰭を選択的に除去されることにある（第２図Ｄ）。The fourth step of the present invention consists in selectively removing the sacrificial oxidized pelvic fins on the surface of the semiconductor substrate 0.1) (FIG. 2D).
本工程は本発明の最も特徴とする工程である。即ち、犠
牲酸化膜ａηを残す部分は図示の如くホトレジスト層鱈
で被覆し、て酸化膜のエツチング処理を行うと、露出さ
れている犠牲酸化膜αηはエツチング除去されて素子形
成領域０を露出する。This step is the most characteristic step of the present invention. That is, the portion where the sacrificial oxide film aη is left is covered with a photoresist layer as shown in the figure, and when the oxide film is etched, the exposed sacrificial oxide film αη is etched away, exposing the element forming region 0. .
このエツチング時に析出物ａ６Ｊも同時虻エツチング除
去され、露出した素子形成領域Ｑ３表面にはゲート酸化
に障害となるホワイトリボンあるいはホワイトスポット
等の析出物α０は完全に除去される。During this etching, the precipitates a6J are also removed by etching, and the precipitates α0, such as white ribbons or white spots, which are obstacles to gate oxidation, are completely removed from the surface of the exposed element forming region Q3.
一方犠牲酸化膜αηを残した部分ではこの析出物αｅの
影響により犠牲酸化膜（ｌηの膜厚が薄（なっている。On the other hand, in the portion where the sacrificial oxide film αη remains, the thickness of the sacrificial oxide film (lη) becomes thin due to the influence of the precipitates αe.
本発明の第５の工程は半導体基板（１１）表面をゲート
酸化して異なる厚みのゲート酸化膜ａ匂を形成すること
にある（第２図Ｅ）。すなわち熱酸化により基板α１）
の素子形成領域（１国表面にゲート酸化膜を生成すると
、露出された素子形成領域（１３）にはゲート酸化のみ
による薄いゲート酸化膜部が形成され、犠牲酸化膜＜１
７）を残存させた素子形成領域（１３１には犠牲酸化お
よびゲート酸化による厚いゲート酸化膜部が同時に形成
される。犠牲酸化膜ａ特の厚みをＴｏＸＩ、ゲート酸化
のみのゲート酸化膜Ｑ９の厚みをＴ０工、とすると、厚
いゲート酸化膜部の厚みＴ０工は、ＴＯＸ ” ＴＯＸ
Ｉ ＋ ＴＯＸ２
の関係が成立する。具体的には
（１） Ｔｏｘｔ ” ５００ Ａ、 Ｔｏｘｔ ＝
５０ＯＡ のとき、Ｔｏ！＝７０ＯＡ
（２） Ｔｏｘ＋＝ ５０ＯＡ、 Ｔｏｘｔ＝ ３０
ＯＡ のとき、Ｔ、Ｘ：： ６００Ａ
（３） ｌ］：１０工１＝１００ＯＡ、 Ｔ、工、＝
５０ＯＡ のとき、Ｔｏｘ：１１００ Ａ
となる。この結果薄いゲート酸化膜（ＬＩは犠牲酸化に
より析出物Ｑ６）の影響を完全に除去して極めて薄く形
成でき、厚いゲート酸化膜（ＬＳＩは犠牲酸化膜だけ厚
く形成されるので欠陥密度の減少により析出物α６）に
よる耐圧不良を補うことができるのである。The fifth step of the present invention consists in gate oxidizing the surface of the semiconductor substrate (11) to form gate oxide films of different thicknesses (FIG. 2E). In other words, by thermal oxidation, the substrate α1)
When a gate oxide film is formed on the surface of the element formation region (13), a thin gate oxide film portion is formed only by gate oxidation in the exposed element formation region (13), and the sacrificial oxide film <1
In the element formation region (131) where 7) remains, a thick gate oxide film part is simultaneously formed by sacrificial oxidation and gate oxidation.The thickness of the sacrificial oxide film a is ToXI, and the thickness of the gate oxide film Q9 with only gate oxidation Assuming that T0 is the thickness of the thick gate oxide film, the thickness of the thick gate oxide film is TOX ” TOX
The relationship I + TOX2 holds true. Specifically, (1) Toxt ” 500 A, Toxt =
When 50OA, To! =70OA (2) Tox+=50OA, Toxt=30
When OA, T,
At 50OA, Tox: 1100A. As a result, it is possible to form an extremely thin gate oxide film (LI is formed thickly by the sacrificial oxide film) by completely removing the influence of the thin gate oxide film (LI is a precipitate Q6 due to sacrificial oxidation), and a thick gate oxide film (LSI is formed thick only by the sacrificial oxide film, so the defect density is reduced) This makes it possible to compensate for the poor pressure resistance caused by the precipitates α6).
（へ）効果
本発明に依れば、第１に同一工程で同時に厚さの異なる
ゲート酸化膜ａ９１を実現できるので、極めて製造容易
である。第２に素子の微細化に伴い薄いゲート酸化膜を
要求され・るが、この薄いゲート酸化膜αωを犠牲酸化
により安定して製造できる。(f) Effects According to the present invention, firstly, gate oxide films a91 having different thicknesses can be realized at the same time in the same process, so manufacturing is extremely easy. Second, thin gate oxide films are required as devices become smaller, and this thin gate oxide film αω can be stably manufactured by sacrificial oxidation.
第３に犠牲酸化を利用することによりフィールド酸化膜
ａつのエツチング量を最小限に抑えることができる。第
４に異なる厚みのゲート酸化膜部により同一チップに異
なるゲート耐圧のＭＯＳ ）ランジスタを集積化でき、
特に微細化した低耐圧の素子と高耐圧の素子とを同一チ
ップに形成できる。Third, by using sacrificial oxidation, the amount of etching of the field oxide film can be minimized. Fourth, gate oxide film parts with different thicknesses allow MOS transistors with different gate breakdown voltages to be integrated on the same chip.
In particular, miniaturized low-voltage elements and high-voltage elements can be formed on the same chip.
第１図Ａ乃至第１図Ｅは従来のゲート酸化膜の形成方法
を説明する断面図、第２図Ａ乃至第２図Ｅは本発明のゲ
ート酸化膜の形成方法を曲、明する断面図である。
主な図番の説明
（１１）は半導体基板、０３は素子形成領域、Ｉは選択
酸化マスク層、ａ！１９はツーイールド酸化膜、側は析
出物、αηは擬牲酸化膜、α９はゲート酸化膜である。1A to 1E are cross-sectional views illustrating a conventional method for forming a gate oxide film, and FIGS. 2A to 2E are sectional views illustrating a method for forming a gate oxide film according to the present invention. It is. Explanation of main figure numbers (11) is a semiconductor substrate, 03 is an element formation region, I is a selective oxidation mask layer, a! 19 is a two-yield oxide film, the side is a precipitate, αη is a pseudo oxide film, and α9 is a gate oxide film.
Claims (1)
択酸化マスク層を付着する工程、前記基板を選択酸化し
て基板にその一部を埋め込んだ厚いフィールド酸化膜を
形成する工程、前記選択酸化マスク層及びパッド酸化膜
を除去し露出した基板表面を犠牲酸化する工程、犠牲酸
化膜を選択的に除去する工程、前記犠牲酸化膜を除去し
た基板表面および前記犠牲酸化膜を残した基板表面にゲ
ート酸化膜を形成する工程を具備することを特徴とする
ゲート酸化膜の形成方法。(1) a step of selectively depositing a selective oxidation mask layer on a semiconductor substrate via a pad oxide film; a step of selectively oxidizing the substrate to form a thick field oxide film partially buried in the substrate; A step of removing the selective oxidation mask layer and the pad oxide film and sacrificially oxidizing the exposed substrate surface, a step of selectively removing the sacrificial oxide film, a substrate surface from which the sacrificial oxide film has been removed, and a substrate with the sacrificial oxide film remaining. A method for forming a gate oxide film, comprising the step of forming a gate oxide film on a surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6950283A JPS59194472A (en) | 1983-04-19 | 1983-04-19 | Forming method of gate oxidized film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6950283A JPS59194472A (en) | 1983-04-19 | 1983-04-19 | Forming method of gate oxidized film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59194472A true JPS59194472A (en) | 1984-11-05 |
Family
ID=13404564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6950283A Pending JPS59194472A (en) | 1983-04-19 | 1983-04-19 | Forming method of gate oxidized film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59194472A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63271963A (en) * | 1987-04-28 | 1988-11-09 | Nec Corp | Manufacture of semiconductor device |
| KR20010045448A (en) * | 1999-11-05 | 2001-06-05 | 박종섭 | Method of forming gate oxide layer |
| KR100342641B1 (en) * | 1998-07-21 | 2002-07-04 | 가네꼬 히사시 | Method of manufacturing a semiconductor device |
| US7084035B2 (en) | 2004-04-13 | 2006-08-01 | Ricoh Company, Ltd. | Semiconductor device placing high, medium, and low voltage transistors on the same substrate |
-
1983
- 1983-04-19 JP JP6950283A patent/JPS59194472A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63271963A (en) * | 1987-04-28 | 1988-11-09 | Nec Corp | Manufacture of semiconductor device |
| KR100342641B1 (en) * | 1998-07-21 | 2002-07-04 | 가네꼬 히사시 | Method of manufacturing a semiconductor device |
| KR20010045448A (en) * | 1999-11-05 | 2001-06-05 | 박종섭 | Method of forming gate oxide layer |
| US7084035B2 (en) | 2004-04-13 | 2006-08-01 | Ricoh Company, Ltd. | Semiconductor device placing high, medium, and low voltage transistors on the same substrate |
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