KR20010045448A - Method of forming gate oxide layer - Google Patents

Method of forming gate oxide layer Download PDF

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Publication number
KR20010045448A
KR20010045448A KR1019990048742A KR19990048742A KR20010045448A KR 20010045448 A KR20010045448 A KR 20010045448A KR 1019990048742 A KR1019990048742 A KR 1019990048742A KR 19990048742 A KR19990048742 A KR 19990048742A KR 20010045448 A KR20010045448 A KR 20010045448A
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South Korea
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oxide film
gate oxide
oxide layer
forming
semiconductor substrate
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KR1019990048742A
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Korean (ko)
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권재순
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990048742A priority Critical patent/KR20010045448A/en
Publication of KR20010045448A publication Critical patent/KR20010045448A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for manufacturing a gate oxide layer is provided to simplify a manufacturing process by forming gate oxide layers of different thickness by an one-shot oxide layer deposition process. CONSTITUTION: A thick gate oxide layer formation region(III') and a thin gate oxide layer formation region(IV') are defined in a semiconductor substrate(200). A trench and an isolating layer(202) filling the trench are sequentially formed in an isolating region of the semiconductor substrate. An oxide layer(208) is formed on the semiconductor substrate to cover the isolating layer. A photoresist layer pattern is formed on the oxide layer to cover the thick gate oxide layer formation region. A part of the oxide layer in the thin gate oxide formation region is eliminated by using the photoresist layer pattern as a mask to form a gate oxide layer of a different thickness. The photoresist layer pattern is removed. The surface of the gate oxide layer of the different thickness is cleaned.

Description

게이트산화막 형성방법{Method of forming gate oxide layer}Method of forming gate oxide layer

본 발명은 하나의 칩 내에서 두께가 서로 다른 게이트산화막을 형성하는 방법에 관한 것으로, 특히, 공정이 단순화되고, 두께조절이 용이한 게이트산화막 형성방법에 관한 것이다.The present invention relates to a method for forming a gate oxide film having a different thickness in one chip, and more particularly, to a method for forming a gate oxide film with a simplified process and easy thickness control.

도 1a 내지 도 1e는 종래기술에 따른 게이트산화막 제조를 위한 공정단면도이다.1A to 1E are cross-sectional views of a process for manufacturing a gate oxide film according to the prior art.

도 1a와 같이, 반도체기판(100) 상에 질화막 또는 감광막 등을 이용하여 소자비활성영역(Ⅱ)을 식각하여 트렌치(trench)(t1)를 형성한다. 여기에서, 도면부호 Ⅰ은 소자활성영역에 해당된다.As shown in FIG. 1A, a trench t1 is formed by etching the device inactive region II on the semiconductor substrate 100 using a nitride film or a photosensitive film. Here, reference I corresponds to the element active region.

그리고 반도체기판(100) 상에 트렌치(trench)(t1)를 덮도록 절연막을 증착하여 형성한 후, 기판 표면이 노출되도록 CMP(Chemical Mechanical Polishing)처리함으로써 소자활성영역과 비활성영역을 구분시키는 격리막(102)을 형성한다.An insulating layer is formed by depositing an insulating film to cover the trench t1 on the semiconductor substrate 100 and then separating the device active region from the inactive region by performing CMP (Chemical Mechanical Polishing) treatment to expose the substrate surface. 102).

도 1b와 같이, 반도체기판(100) 상에 격리막(102)을 덮도록 산화실리콘 등을 증착하여 제 1산화막(106)을 형성한다.As shown in FIG. 1B, the first oxide film 106 is formed by depositing silicon oxide or the like on the semiconductor substrate 100 to cover the separator 102.

도면부호 Ⅲ은 두꺼운 게이트산화막 형성영역이고, 도면부호 Ⅳ는 얇은 게이트산화막 형성영역을 도시한 것이다.Reference numeral III denotes a thick gate oxide film formation region, and reference numeral IV illustrates a thin gate oxide film formation region.

제 1산화막(106) 상에 감광막을 도포한 후, 노광 및 현상함으로써 두꺼운 게이트산화막 형성영역(Ⅲ)을 덮으며 얇은 게이트산화막 형성영역(Ⅳ)을 노출시키는 감광막패턴(110)을 형성한다.After the photosensitive film is coated on the first oxide film 106, the photosensitive film pattern 110 is formed to cover the thick gate oxide film forming region III and expose the thin gate oxide film forming region IV by exposing and developing the photoresist film.

이 후, 감광막패턴(110)을 마스크로 하여 제 1산화막(106)을 습식식각(12)방법으로 제거 함으로써 반도체기판(100)의 얇은 게이트산화막 형성영역(Ⅳ)을 노출시킨다.Thereafter, the first oxide film 106 is removed by the wet etching method 12 using the photoresist pattern 110 as a mask to expose the thin gate oxide film forming region IV of the semiconductor substrate 100.

도 1c와 같이, 감광막패턴을 제거한다.As shown in FIG. 1C, the photoresist pattern is removed.

제 1산화막은 도면에서와 같이, 두꺼운 게이트산화막 형성영역(Ⅲ)에서는 식각이 진행되지 않아 최초에 형성된 두께(106a)로 그대로 있는 반면, 얇은 게이트산화막 형성영역(Ⅳ)에서는 완전히 제거된 상태에 있다.As shown in the drawing, the first oxide film remains intact in the thick gate oxide film forming region III and remains at the thickness 106a initially formed because the etching is not performed, whereas the first oxide film is completely removed in the thin gate oxide film forming region IV. .

감광막패턴이 제거된 이 후에도 제 1산화막에 감광막이 잔류되어 있으므로, 이를 제거하기 위한 에슁(ashing)공정 및 불산(HF)을 이용한 세정공정을 순차적으로 진행시킨다.Since the photoresist film remains in the first oxide film even after the photoresist pattern is removed, an ashing process and a cleaning process using hydrofluoric acid (HF) are sequentially performed to remove the photoresist film.

도 1d와 같이, 두꺼운 게이트산화막 형성영역(Ⅲ)에 잔류된 제 1산화막 및 반도체기판(100)의 얇은 게이트산화막 형성영역(Ⅳ)을 덮도록 산화실리콘 등을 증착하여 제 2산화막(108)을 형성한다.As shown in FIG. 1D, silicon oxide or the like is deposited to cover the first oxide film remaining in the thick gate oxide film forming region III and the thin gate oxide film forming region IV of the semiconductor substrate 100 to deposit the second oxide film 108. Form.

도 1e와 같이, 제 2산화막 상에 다결정실리콘을 증착한 후, 패턴식각함으로써 두꺼운 게이트산화막 형성영역(Ⅲ)과 얇은 게이트산화막 형성영역(Ⅳ)에 각각의 제 1, 제 2게이트(120a)(120b)를 형성한다.As shown in FIG. 1E, after the polycrystalline silicon is deposited on the second oxide film, the first and second gates 120a (thickness) are formed in the thick gate oxide film formation region (III) and the thin gate oxide film formation region (IV) by pattern etching. 120b).

따라서, 종래의 기술에서는 제 1게이트(120a) 하부에는 두꺼운 게이트산화막(108a)이 형성되고, 제 2게이트(120b) 하부에는 얇은 게이트산화막(108b)이 패터닝된다.Therefore, in the related art, a thick gate oxide film 108a is formed below the first gate 120a and a thin gate oxide film 108b is patterned below the second gate 120b.

그러나, 종래의 기술에서는 두꺼운/얇은 게이트산화막을 형성하기 위해 2회에 걸친 산화막 증착공정이 진행되므로 공정 횟수가 증가되고, 또한, 소자의 채널에 이온주입된 보론이온이 게이트산화막과 기판 사이에 편석되어 됨에 따라 PMOS인 경우 소자의 문턱전압(VT)을 변하게 함으로써 소자형성을 어렵게 하였다.However, in the related art, since the oxide deposition process is performed twice in order to form a thick / thin gate oxide film, the number of processes is increased, and boron ions implanted into the channel of the device are segregated between the gate oxide film and the substrate. As a result, in the case of the PMOS, the device formation is difficult by changing the threshold voltage (V T ) of the device.

그리고 제 1산화막 패턴 식각 후에 진행되는 세정 공정 시, HF를 이용하여 세정함에 따라 제 1산화막 표면이 불균일하게 식각된다. 따라서, 이 후 제 1산화막을 덮는 제 2산화막 형성 시, 제 2산화막의 두께를 콘트롤하기 어려운 문제점이 있었다.In the cleaning process performed after the first oxide film pattern etching, the surface of the first oxide film is unevenly etched by using HF. Therefore, thereafter, when forming the second oxide film covering the first oxide film, it is difficult to control the thickness of the second oxide film.

상기의 문제점을 해결하고자, 본 발명의 목적은 각기 두께가 두꺼운/얇은 게이트산화막 형성 시, 공정이 단순하고도 얇은 부분과 두꺼운 부분의 두께의 콘트롤이 용이한 게이트산화막의 형성방법을 제공하려는 것이다.In order to solve the above problems, it is an object of the present invention to provide a method for forming a gate oxide film having a simple process and control of the thickness of a thin portion and a thick portion, respectively, when forming a thick / thin gate oxide film.

상기 목적을 달성하고자, 두꺼운 게이트산화막 형성영역과 얇은 게이트산화막 형성영역이 정의된 반도체기판 상에 서로 다른 두께의 게이트산화막을 형성하는 방법에 있어서, 본 발명은 게이트산화막 형성방법은 반도체기판 상의 소자격리영역에 트렌치 및 트렌치를 채우는 격리막을 순차적으로 형성하는 공정과, 반도체기판 상에 격리막을 덮도록 산화막을 형성하는 공정과, 산화막 상에 두꺼운 게이트산화막 형성영역을 덮도록 감광막패턴을 형성하는 공정과, 감광막패턴을 마스크로 얇은 게이트산화막 형성영역의 산화막을 일부 제거하여 서로 다른 두께를 갖는 게이트산화막을 형성하는 공정과, 감광막패턴을 제거하는 공정과, 서로 다른 두께를 갖는 게이트산화막 표면을 세정하는 공정을 구비한 것이 특징이다.In order to achieve the above object, in the method for forming a gate oxide film having a different thickness on a semiconductor substrate in which a thick gate oxide film forming region and a thin gate oxide film forming region are defined, the present invention provides a method for forming a gate oxide film in isolation of a device on a semiconductor substrate. Sequentially forming trenches and isolation layers filling trenches in the region, forming an oxide film on the semiconductor substrate so as to cover the isolation film, forming a photoresist pattern on the oxide film so as to cover the thick gate oxide film formation region; Removing a portion of the oxide film in the thin gate oxide film forming region using the photosensitive film pattern as a mask to form a gate oxide film having different thicknesses, removing the photosensitive film pattern, and cleaning the surface of the gate oxide film having different thicknesses. It is featured.

도 1a 내지 도 1e는 종래기술에 따른 게이트산화막 제조를 위한 공정단면도이고,1A to 1E are cross-sectional views of a process for manufacturing a gate oxide film according to the prior art,

도 2a 내지 도 2d는 본 발명에 따른 게이트산화막 제조를 위한 공정단면도이다.2A to 2D are cross-sectional views of a process for manufacturing a gate oxide film according to the present invention.

*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200. 반도체기판 102, 202. 격리막100, 200. Semiconductor substrate 102, 202. Separator

110, 210. 감광막패턴 120, 220. 건식 식각110, 210. Photoresist pattern 120, 220. Dry etching

t1, t2. 트렌치t1, t2. Trench

Ⅰ, Ⅰ`. 소자의 활성영역 Ⅱ, Ⅱ`. 비활성영역I, I`. Active region II, II` of the device. Inactive area

Ⅲ, Ⅲ`. 두꺼운 게이트산화막 형성영역III, III`. Thick Gate Oxide Formation Area

Ⅳ, Ⅳ`. 얇은 게이트산화막 형성영역Ⅳ, Ⅳ`. Thin Gate Oxide Formation Area

106, 106a, 108, 208. 산화막106, 106a, 108, 208. Oxide film

108a, 108b, 208a, 208b. 게이트산화막108a, 108b, 208a, 208b. Gate oxide

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2d는 본 발명에 따른 게이트산화막 제조를 위한 공정단면도이다.2A to 2D are cross-sectional views of a process for manufacturing a gate oxide film according to the present invention.

도 2a와 같이, 반도체기판(200)의 소자의 비활성영역(Ⅱ`)을 식각함으로써 트렌치(t2)를 형성한다.As shown in FIG. 2A, the trench t2 is formed by etching the inactive region II ′ of the device of the semiconductor substrate 200.

여기에서, 도면부호 Ⅰ`는 소자의 활성영역을 도시한 것이다.Here, reference I 'shows the active region of the device.

그리고 반도체기판(200) 상에 트렌치(t2)를 덮도록 산화실리콘 등의 절연막을 증착한 후, 기판 표면이 노출되도록 CMP 하여 격리막(202)을 형성한다. 이 격리막(202)은 소자의 활성영역(Ⅰ`)과 비활성영역(Ⅱ`) 사이를 구분시킨다.Then, an insulating film of silicon oxide or the like is deposited on the semiconductor substrate 200 to cover the trench t2, and then the CMP is formed to expose the substrate surface to form the isolation film 202. The separator 202 distinguishes between the active region I 'and the inactive region II' of the device.

이 후, 반도체기판(200)을 전세정처리함으로써 표면에 형성된 자연산화막 등을 제거한다.Thereafter, the semiconductor substrate 200 is pre-cleaned to remove the natural oxide film or the like formed on the surface.

도 2b와 같이, 반도체기판(200) 상에 격리막(202)을 덮도록 산화실리콘 등을 증착하여 제 1산화막(206)을 형성한다. 반도체기판(200)에는 두꺼운 게이트산화막 형성영역( Ⅲ`)과 얇은 게이트산화막 형성영역(Ⅳ`)이 정의되어 있다.As illustrated in FIG. 2B, the first oxide film 206 is formed by depositing silicon oxide or the like on the semiconductor substrate 200 to cover the separator 202. In the semiconductor substrate 200, a thick gate oxide film forming region III ′ and a thin gate oxide film forming region IV ′ are defined.

이어서, 산화막(206) 상에 감광막을 도포한 후, 노광 및 현상하여 두꺼운 게이트산화막 형성영역(Ⅲ`)을 덮으며 얇은 게이트산화막 형성영역(Ⅳ`)을 노출시키도록 감광막패턴(210)을 해터닝한다.Subsequently, after the photoresist film is applied on the oxide film 206, the photoresist film pattern 210 is exposed and developed to cover the thick gate oxide film formation region III ′ and to expose the thin gate oxide film formation region IV ′. Turn.

이 후, 감광막패턴(210)을 마스크로 산화막(206)의 일부를 습식식각(220) 방법을 이용하여 제거한다. 습식식각 시에 사용되는 식각액은 희석된 불산(HF)용액이 이용된다.Thereafter, a portion of the oxide film 206 is removed using the wet etching method 220 using the photoresist pattern 210 as a mask. As an etchant used for wet etching, diluted hydrofluoric acid (HF) solution is used.

도 2c와 같이, 감광막패턴을 제거한다.As shown in FIG. 2C, the photoresist pattern is removed.

산화막(208)은 도면에서와 같이, 두꺼운 게이트산화막 형성영역(Ⅲ`)에서는 식각이 진행되지 않아 최초에 형성된 두께를 유지한 반면, 얇은 게이트산화막 형성영역(Ⅳ`)에서는 일부가 제거된 상태에 있다.As shown in the drawing, the oxide film 208 maintains its original thickness because no etching proceeds in the thick gate oxide film forming region III ′, while a portion of the oxide film 208 is removed in the thin gate oxide film forming region IV ′. have.

감광막패턴이 제거된 후, 산화막(208) 표면에 감광막이 잔류되어 있다.After the photoresist pattern is removed, the photoresist remains on the surface of the oxide film 208.

따라서, 본 발명에서는 산화막 표면에 잔류된 감광막을 제거하기 위해, O3또는 H2SO4+ H2O2를 이용하여 에슁 공정을 진행시킨다.Therefore, in the present invention, in order to remove the photoresist remaining on the surface of the oxide film, an etching process is performed using O 3 or H 2 SO 4 + H 2 O 2 .

이 후, 에슁공정이 완료되면, 잔류된 불순물 등을 제거하기 위해, 산화막 표면을 세정처리한다.After that, when the etching process is completed, the surface of the oxide film is washed to remove residual impurities and the like.

본 발명에서는 산화막 표면 세정 처리 시, NH4OH +H2O2+ H2O 를 혼합한 혼합액이 이용된다.In the present invention, this mixture a mixture of the oxide film during the cleaning surface treatment, NH 4 OH + H 2 O 2 + H 2 O is used.

도 2d와 같이, 산화막 상에 다결정실리콘을 증착한 후, 패턴식각함으로써 두꺼운 게이트산화막 형성영역(Ⅲ`)과 얇은 게이트산화막 형성영역(Ⅳ`)에 각각의 제 1, 제 2게이트(220a)(220b)를 형성한다.As shown in FIG. 2D, after the polysilicon is deposited on the oxide film, the first and second gates 220a are formed in the thick gate oxide film formation region III ′ and the thin gate oxide film formation region IV ′ by pattern etching. 220b).

따라서, 본 발명에서는 제 1게이트(220a) 하부에는 두꺼운 게이트산화막(208a)이 형성되고, 제 2게이트(220b) 하부에는 얇은 게이트산화막(208b)이 패터닝된다.Therefore, in the present invention, a thick gate oxide film 208a is formed under the first gate 220a, and a thin gate oxide film 208b is patterned under the second gate 220b.

상술한 바와 같이, 본 발명에서는 1회에 걸친 산화막 증착공정으로 서로 다른 두께를 갖는 게이트산화막을 형성가능하므로, 공정 횟수가 줄어 공정이 단순화될뿐더러, 소자의 채널에 이온주입된 보론이온이 게이트산화막과 기판 사이에 편석되는 양이 줄어 VT조절이 용이하다.As described above, in the present invention, since the gate oxide film having a different thickness can be formed by a single oxide film deposition process, the number of steps is reduced, the process is simplified, and boron ions implanted into the channel of the device are gate oxide films. The amount of segregation between the substrate and the substrate is reduced, which facilitates V T adjustment.

또한, 본 발명에서는 산화막 표면 세정 처리 시, NH4OH +H2O2+ H2O 를 혼합한 혼합액을 이용함에 따라, 최종적으로 얻는 게이트산화막의 두께 콘트롤이 용이한 잇점이 있다.Further, in the present invention, when the oxide film surface cleaning treatment is used, the thickness control of the gate oxide film finally obtained is easy by using a mixed solution of NH 4 OH + H 2 O 2 + H 2 O.

Claims (4)

두꺼운 게이트산화막 형성영역과 얇은 게이트산화막 형성영역이 정의된 반도체기판 상에 서로 다른 두께의 게이트산화막을 형성하는 방법에 있어서,A method of forming a gate oxide film having a different thickness on a semiconductor substrate having a thick gate oxide film formation region and a thin gate oxide film formation region defined therein, 반도체기판 상의 소자격리영역에 트렌치 및 상기 트렌치를 채우는 격리막을 순차적으로 형성하는 공정과,Sequentially forming a trench in the device isolation region on the semiconductor substrate and an isolation film filling the trench; 상기 반도체기판 상에 상기 격리막을 덮도록 산화막을 형성하는 공정과,Forming an oxide film on the semiconductor substrate to cover the separator; 상기 산화막 상에 상기 두꺼운 게이트산화막 형성영역을 덮도록 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the oxide film so as to cover the thick gate oxide film formation region; 상기 감광막패턴을 마스크로 상기 얇은 게이트산화막 형성영역의 산화막을 일부 제거하여 서로 다른 두께를 갖는 게이트산화막을 형성하는 공정과,Forming a gate oxide film having a different thickness by removing a portion of the oxide film of the thin gate oxide film forming region using the photoresist pattern as a mask; 상기 감광막패턴을 제거하는 공정과,Removing the photoresist pattern; 상기 서로 다른 두께를 갖는 게이트산화막 표면을 세정하는 공정을 구비한 게이트산화막 형성방법.And a step of cleaning the surfaces of the gate oxide films having different thicknesses. 청구항 1에 있어서,The method according to claim 1, 상기 감광막패턴을 제거한 후에 상기 서로 다른 두께를 갖는 게이트산화막 상에 잔류된 감광막을 제거하기 위한 에슁공정을 추가시킨 것이 특징인 게이트산화막 형성방법.And an etching process for removing the photoresist film remaining on the gate oxide film having different thicknesses after removing the photoresist pattern. 청구항 2에 있어서,The method according to claim 2, 상기 에슁공정은 O3또는 H2SO4와 H2O2의 혼합액이 이용된 것이 특징인 게이트산화막 형성방법.The etching step is a gate oxide film forming method characterized in that the mixture of O 3 or H 2 SO 4 and H 2 O 2 was used. 청구항 1에 있어서,The method according to claim 1, 상기 세정 공정은 NH4OH +H2O2+ H2O 를 혼합한 혼합액이 이용된 것이 특징인 게이트산화막 형성방법.The cleaning process is a gate oxide film forming method characterized in that a mixture of NH 4 OH + H 2 O 2 + H 2 O was used.
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Publication number Priority date Publication date Assignee Title
KR20030057282A (en) * 2001-12-28 2003-07-04 미쓰비시덴키 가부시키가이샤 Semiconductor device and manufacturing method thereof
KR100466209B1 (en) * 2002-07-08 2005-01-13 매그나칩 반도체 유한회사 Method of manufacturing semiconductor device
KR100723467B1 (en) * 2001-01-17 2007-05-30 삼성전자주식회사 Method of forming gate oxide by partial etching

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JPH02284461A (en) * 1989-04-26 1990-11-21 Fujitsu Ltd Manufacture of semiconductor device
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JPS59194472A (en) * 1983-04-19 1984-11-05 Sanyo Electric Co Ltd Forming method of gate oxidized film
JPH02284461A (en) * 1989-04-26 1990-11-21 Fujitsu Ltd Manufacture of semiconductor device
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Publication number Priority date Publication date Assignee Title
KR100723467B1 (en) * 2001-01-17 2007-05-30 삼성전자주식회사 Method of forming gate oxide by partial etching
KR20030057282A (en) * 2001-12-28 2003-07-04 미쓰비시덴키 가부시키가이샤 Semiconductor device and manufacturing method thereof
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