JPS6150331A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device manufacturing method with which the width of an electrode and the width between the end of the electrode and the interface of a P-N junction can be suppressed in an excellent controllability by a method wherein an electrode layer is formed on a semiconductor substrate, and an etching mask and an etching process are improved. CONSTITUTION:An electrode 2 is formed (a) on the whole surface of an N type semiconductor substrate 1, and after an etching is performed (c) using an electrode etching mask 5, a silicon oxide film 6 is formed thereon by performing a CVD method without removing the electrode etching mask 5. Then, an etching is performed on the silicon oxide film 6 by performing an etching method having a physical sputtering effect, an ion implantation mask 4 is formed (e), P type impurities are ion-implanted, and an ion-implanted layer 3 is formed (f). As an alignment operation is not necessary for the ion implantation mask 4 formed as above, it is not subjected to a technical restriction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a novel method for manufacturing a semiconductor device using PM junction characteristics.

Conventional configurations and their problems In semiconductor devices using PM junction characteristics, there are often
There arises a need to manufacture a semiconductor device having a structure as shown in FIG. That is, the N-type semiconductor substrate 1 (
Here, for convenience of explanation, it is assumed to be N type. A semiconductor device based on an N-type semiconductor substrate will be described below as an example. ) has a structure in which an electrode 2 is formed on top of the electrode 2 and a P-type ion entry layer 3 is formed around it, and the PN junction interface should not reach the edge of the electrode 2 but should be as close as possible. It is a request.

A typical example of an attempt to implement such an fx request using a conventional method will be described below.

(Conventional example 1) Conventional example 1 will be explained using FIG. 2.

In this case, first, an ion implantation mask 4 is formed on the N-type semiconductor substrate 1 (a), and a p-type impurity is ion-implanted to form an ion-implanted layer (1)).

Next, after removing the ion implantation mask 4, an electrode 2 is formed on the entire surface of the N-type semiconductor substrate 1 and the ion implantation layer 3.
), an electrode etching mask 5 is formed on the electrode 2 (d), the electrode 2 is etched, and finally the electrode etching mask 6 is removed (e).

However, in this method, although the width of the electrode 2 and the width of the region of the N-type semiconductor substrate 1 sandwiched between the ion-implanted layers 3VC can be relatively strictly controlled, when forming the electrode etching mask 6, the width of the ion-implanted V-1 (hereinafter referred to as
This type of operation is called an alignment operation).

(Conventional example 2) Conventional example 2 will be explained using FIG. 3.

In this case, first, [, the entire surface of the N-type semiconductor substrate 1'
t['! very,. ), electrode. Top, electrode;
.

After forming the etching mask 6 (b), the electrode 2 is etched. At this time, the electrode 2 level is to some extent (ion implantation layer 3
After forming the PM bonding interface and the edge of the electrode 2, over-etching is performed in the lateral direction to a desired width (C). Finally, using the electrode layer/framework mask 6 as the ion implantation mask 4, P-type impurities are ion-implanted to form the ion implantation layer 3, and then the ion implantation mask 4 is removed (d).

Compared to Conventional Example 1, this method does not require an alignment operation, and since the electrode etching mask 5 also serves as the ion implantation mask 4, only one phosphorography process is required when forming the mask. has advantages. However, in order to prevent the end of the electrode 2 from reaching the PN junction interface, when etching the electrode 2, an operation of over-etching in the lateral direction is performed. In this regard, conventional example 1
Although it is possible to reduce the width by controlling the width from the edge of the electrode 2 to the PN junction interface by performing an alignment operation, it is difficult to say that the controllability is good. I can't say enough good things about the controllability of its width. This is because the lateral heave, the speed at which the border advances, and the shape of its front surface.
It is greatly affected by the adhesion strength between the electrode 2 and the N-type semiconductor substrate 1 and the electrode etching mask 6, the thickness of the electrode 2, etc., and lacks reproducibility, and it is by no means easy to detect the end point of the desired lateral over-etching width. This is because there is no such thing.

As described above in Conventional Sections 1 and 2, there are advantages and disadvantages in meeting the required requirements, and it is desirable to establish a better manufacturing method.

Purpose of the Invention In order to solve the problems shown in the explanation of the conventional example, the present invention provides a KH, which does not require an alignment operation and has good controllability of the electrode width and the width from the end of the electrode to the PN junction interface. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can reduce the amount of energy required.

Structure of the Invention The present invention involves forming an electrode layer on an epitaxial layer or an amorphous layer of a semiconductor substrate, performing nealing using an etching mask as a mask, and then removing the electrode layer and the etching mask. First, a thin film having the same quality as the electrode etching mask is formed over the entire surface by CVD.

Next, by using an etching method having a physical sputtering effect or the like, etching is performed to leave a uniform thin film with high precision on the electrode layer and on the side surfaces of the electrode without using an etching mask. Finally, ion implantation is performed using the thin film formed as described above as a mask.

Description of examples An embodiment of the present invention will be described using FIG. 4.

First, an electrode 2 with a thickness of about 0.5 μm is formed on the entire surface of the N-type semiconductor substrate 1 (1 degree). After forming the mask pattern on the entire surface through a phosphorography process (b), the electrode 2 is etched (0).Then, without removing the electrode etching mask 5, a CVD method is applied thereon. A silicon oxide film 6 is formed.In this embodiment, a plasma CVD method or a photo CVD method, which is considered to have a large side surface adhesion effect among the CVN methods, is used.
When a silicon oxide film 6 having a thickness of about 0.8 μm in the high etching direction was formed using the etching method, a uniform silicon oxide film 6 with a thickness of about 0.5 μm was also formed on the side surfaces of the electrode 2 and the electrode etching mask 6. was able to be formed (d). Furthermore, by forming the silicon oxide film 6 without removing the electrode etching mask 5, the electrode etching mask 5 can be removed.
In addition to eliminating the removal process of N-type semiconductor substrate 1,
The thickness of the thin film on electrode 2 is greater than the thickness of the thin film on top.
There is an advantage that the thickness can be increased by the thickness of the electrode etching mask 5. The specific effects of this will be discussed later.

After forming the silicon oxide film 6, physical shaving 1 is performed without using an etching mask.
Effect 16"y f 7 f method 1"1・pa 1°'
I Etch the oxide film 6 to form the ion implantation mask 4 (e). As an etching method having a physical sputtering effect, the RIE method or H method is characterized in that it causes little damage to the surface of the N-type semiconductor substrate 1 and can perform etching with high selectivity with respect to the H-type semiconductor substrate 1.
This was done using the FtIBE method. Furthermore, since it has a physical sputtering effect, it is etched almost in the height direction in the direction in which the etching progresses, so it can be formed on the side surfaces of the electrode 2 and the electrode etching mask 6 after etching without using an etching mask. There is almost no change in the thickness of the silicon oxide film 6 compared to that before etching. That is, the thickness of the portion of the ion implantation mask 4 formed on the side surface of the electrode 2 can be determined at the time of forming the silicon oxide film 6 by the C1VD method, and its controllability is better than that of the conventional example. The controllability of the width formed by the lateral overetching effect as shown in FIG.

Furthermore, it can be said that this example is superior to Conventional Example 2 from the viewpoint of not using the lateral overetching effect and from the viewpoint of controllability of the width of the electrode 20.

By the way, due to the advantages mentioned above in forming the silicon oxide film e by the CVD method, after etching the silicon oxide film 6, the electrode etching mask 5 remains on the electrode 2 with the original thickness remaining. In addition, when ion implantation is performed in a later process, the electrode etching mask 5 alone can sufficiently play the role of an ion implantation mask, and regardless of the thickness of the electrode 2, the implanted ions can be implanted into the N-type layer directly under the electrode 2. This provides a specific effect of being able to prevent intrusion into the semiconductor substrate 1.

The ion implantation mask 4 formed as described above does not require an alignment operation unlike the conventional example 1 in its formation process, and therefore has the advantage of not being subject to any technical constraints arising from this.

Finally, P-type impurities are ion-implanted to form the ion-implanted layer 3.
After forming the ion implantation mask 4, the ion implantation mask 4 is removed (f).

At this time, since the ion implantation is performed using the ion implantation mask 4, the ion implantation method may be an ion implantation method using a non-focused ion beam. In the present invention, an electrode layer is formed on the surface of a semiconductor substrate or an amorphous layer, and after etching, a homogeneous layer is formed by CVD without removing the thin film used as a etching mask. Forming a thin film, and performing ion implantation using an ion implantation mask formed by etching the thin film using an etching method that has a physical spattering effect, eliminating the need for alignment operations. The electrode width and the width from the edge of the electrode to the PM bonding interface can be controlled with good control.
This provides a concrete effect in that the width to the N-junction interface can be suppressed to be smaller than the width that can be achieved by alignment operations.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a semiconductor device using iPN junction characteristics, Figure 2 (Δ) to (e) is a process cross-sectional view showing the manufacturing method of the conventional example, and Figure 3 is (&) to (d) H. FIGS. 4A to 4F are process sectional views showing another conventional manufacturing method, and FIGS. 4A to 4F are process sectional views showing the manufacturing method of the present invention. 1. N-type semiconductor substrate, 2...electrode, 3...
...Ion implantation layer, 4. Ion implantation mask, 6...
・Electrode etching mask, 6. ・Silicon oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 2 @ Figure 4

Claims (2)

[Claims] (1) Forming an electrode layer on the first layer of one conductivity type, forming a first thin film having an arbitrary pattern on this electrode layer,
A step of etching the exposed portion of the electrode using this first thin film as a mask, a step of forming a second thin film of the same quality as the first thin film on the entire surface by CVD, and a step of physically sputtering the second thin film. A method for manufacturing a semiconductor device, comprising the steps of performing vertical etching using an etching method according to the present invention, and performing ion implantation using the first and second thin films as masks, and forming a conductive type diffusion layer in the first layer. (2) An etching method that has a physical sputtering effect is RIE (Reactive Ion Etching).
) method or RIBE (ReactiveIonBeamE
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is a tch-ing method.