JPS62120017A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62120017A JPS62120017A JP26025785A JP26025785A JPS62120017A JP S62120017 A JPS62120017 A JP S62120017A JP 26025785 A JP26025785 A JP 26025785A JP 26025785 A JP26025785 A JP 26025785A JP S62120017 A JPS62120017 A JP S62120017A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- semiconductor layer
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装この製造方法であって、異方性エツチングによ
り開口部の絶縁膜の側壁に半導体層を形成しておき、し
かる後に半導体基板上に半導体層をエピタキシャル成長
させることにより、ファセットの生じない選択エピタキ
シャル層の形成を可能とする。[Detailed Description of the Invention] [Summary] This method of manufacturing a semiconductor device includes forming a semiconductor layer on the sidewall of an insulating film in an opening by anisotropic etching, and then epitaxially growing the semiconductor layer on a semiconductor substrate. By doing so, it is possible to form a selective epitaxial layer without generating facets.
本発明は半導体装置の製造方法に関するものであり、更
に詳しく言えば絶縁膜を開口して露出した半導体基板上
に半導体層を形成する半導体装置の製造方法に関するも
のである。The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device in which a semiconductor layer is formed on an exposed semiconductor substrate by opening an insulating film.
従来の絶縁膜による素子分離の方法として、E−FOX
法、絶縁膜埋込み法9選択エピタキシャル成長法がある
。このうちE−FOX法はいわゆるバーズ・ピークが発
生して実質的に素子分離用絶縁膜の占有面積が大きくな
り、素子の高集積化が図れない点で問題がある。絶縁膜
埋込み法はE−FOX法のような欠点はないが、溝中に
形成せた絶縁物をエッチバックするなど平坦化技術を要
し、煩雑である。E-FOX is a conventional method of element isolation using an insulating film.
There are 9 selective epitaxial growth methods. Among these methods, the E-FOX method has a problem in that a so-called bird's peak occurs and the area occupied by the element isolation insulating film becomes substantially large, making it impossible to achieve high integration of the elements. Although the insulating film embedding method does not have the drawbacks of the E-FOX method, it requires a planarization technique such as etching back the insulator formed in the trench, and is complicated.
これに対し、選択エピタキシャル成長法はE−FOX法
のような欠点がなく素子の高集結化に好適であるし、ま
た絶縁膜埋め込み法のようにエピタキシャル成長後に半
導体層をエッチバックする必要もなく製造工程が簡単で
ある。On the other hand, the selective epitaxial growth method does not have the disadvantages of the E-FOX method, and is suitable for highly concentrating devices, and unlike the insulating film embedding method, there is no need to etch back the semiconductor layer after epitaxial growth. is easy.
第2図は従来の選択エピタキシャル法を説明する断面図
であり、1はSI大基板2は5102膜。FIG. 2 is a cross-sectional view illustrating the conventional selective epitaxial method, in which 1 is an SI large substrate 2 is a 5102 film.
3はSi基板l上にエピタキシャル成長によって形成さ
れたエピタキシャルSAPである。3 is an epitaxial SAP formed by epitaxial growth on a Si substrate l.
ところで第2図に示すように、従来の選択エピタキシャ
ル法によれば成長時に起こる5102膜2とエピタキシ
ャルS1層3との間の摩擦抵抗によりファセットが発生
することがあるが、この部分に素子が形成されると耐圧
不良など素子の欠陥の原因となることがある。By the way, as shown in FIG. 2, according to the conventional selective epitaxial method, facets may occur due to the frictional resistance between the 5102 film 2 and the epitaxial S1 layer 3 that occurs during growth. If this occurs, it may cause device defects such as poor breakdown voltage.
本発明はかかる従来例の問題点に鑑み創作されたもので
あり、ファセットが発生しない選択エピタキシャル成長
層を形成する半導体装置の製造方法の提供を目的とする
。The present invention was created in view of the problems of the conventional method, and an object of the present invention is to provide a method for manufacturing a semiconductor device that forms a selective epitaxial growth layer in which facets do not occur.
本発明は半導体基板上に絶縁膜を形成した後、該絶縁膜
を開口して半導体基板の一部を露出させる工程と、前記
露出部を含め全面に第1の半導体層を形成する工程と、
前記第1の半導体層を異方性エツチングすることにより
、前記開口部の絶縁膜の側壁にのみ該第2の半導体層を
残存させる工程と、前記開口部に底部の露出している半
導体基板上に第2の半導体層をエピタキシャル成長させ
る工程とによりなることを特徴とする。The present invention includes a step of forming an insulating film on a semiconductor substrate, and then opening the insulating film to expose a part of the semiconductor substrate; and a step of forming a first semiconductor layer on the entire surface including the exposed portion.
etching the first semiconductor layer anisotropically to leave the second semiconductor layer only on the sidewall of the insulating film in the opening; and etching the second semiconductor layer on the semiconductor substrate whose bottom is exposed in the opening. and epitaxially growing a second semiconductor layer.
本発明の構成によれば、エピタキシャル成長によって第
2の半導体層を形成する前に、異方性エツチングにより
、第1の半導体層を絶縁膜の側壁に残しておく0次に露
出した半導体基板上に第2の半導体層をエピタキシャル
成長するとき、該半導体層と絶縁膜の側壁に形成された
第1の半導体層との摩擦抵抗は比較的少ないので、ファ
セットは発生しない。According to the structure of the present invention, before forming the second semiconductor layer by epitaxial growth, the first semiconductor layer is left on the sidewall of the insulating film by anisotropic etching. When the second semiconductor layer is epitaxially grown, there is relatively little frictional resistance between the semiconductor layer and the first semiconductor layer formed on the sidewall of the insulating film, so no facets are generated.
次に図を参照しながら本発明の実施例について説明する
。第1図は本発明の実施例に係る半導体装lの製造方法
を説明する断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device 1 according to an embodiment of the present invention.
(工程1)
まず81基板l上に5102膜2を被着し、その後パタ
ーニングして開口部4を形成する。(Step 1) First, a 5102 film 2 is deposited on an 81 substrate l, and then patterned to form an opening 4.
(工程2)
次にCVD技術により、開口部4を含めて全面に薄い多
結晶Si層5を形成する。(Step 2) Next, a thin polycrystalline Si layer 5 is formed over the entire surface including the opening 4 by CVD technology.
(工程3) 次に多結晶51層5を異方性エツチングする。(Step 3) Next, the polycrystalline 51 layer 5 is anisotropically etched.
これによりs、o2膜2の側壁にのみ多結晶S1層5が
残存する。As a result, the polycrystalline S1 layer 5 remains only on the sidewalls of the S, O2 film 2.
(工程4)
次に開口部4の底の露出しているSi基板l上にエピタ
キシャル成長させることにより、単結晶のエピタキシャ
ル成長31層6を成長する。ここでエピタキシャル成長
S1層6と5102膜2の側壁に形成されている多結晶
Si層5との摩擦抵抗は比較的小さいので、従来例のよ
うなファセットの発生を防止することができる。(Step 4) Next, a single crystal epitaxial growth 31 layer 6 is grown by epitaxially growing on the Si substrate l exposed at the bottom of the opening 4. Here, since the frictional resistance between the epitaxially grown S1 layer 6 and the polycrystalline Si layer 5 formed on the side wall of the 5102 film 2 is relatively small, the generation of facets as in the conventional example can be prevented.
従ってエピタキシャル成長51層6に素子を形成する場
合にも、ファセットを原因とする素子の劣化および不良
の防止が可能となる。Therefore, even when forming an element on the epitaxially grown layer 6, it is possible to prevent element deterioration and defects caused by facets.
以上説明したように、本発明によれば絶縁膜の側壁に第
2の半導体膜を形成するという簡単な構成により、素子
の不良原因となるファセットの発生を防止することが可
滝となる。As described above, according to the present invention, the simple structure of forming the second semiconductor film on the sidewall of the insulating film makes it possible to prevent the occurrence of facets that may cause device failure.
第1図は本発明の実施例に係る半導体装nの製造方法を
説明する断面図であり、第2図は従来例の半導体装置の
製造方法を説明する断面図である。
l・・・Si基板(半導体基板)
2・・・S、0211!I2
4・・・開口部
5・・・多結晶Si層(第1の半導体層)6・・・エピ
タキシャル成長S L R(第2の半導体層)
′づr\、
代理人 弁理士 井桁、貞・−゛i
二、7
Sil孜I
Slム1
オ(15日月のう→(乙イろり新、江1図第亘図FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device n according to an embodiment of the present invention, and FIG. 2 is a sectional view illustrating a method of manufacturing a conventional semiconductor device. l...Si substrate (semiconductor substrate) 2...S, 0211! I2 4...Opening 5...Polycrystalline Si layer (first semiconductor layer) 6...Epitaxial growth SLR (second semiconductor layer) 'zr\, Agent Patent attorney Igeta, Sada. -゛i 2, 7 Sil Kei Slmu 1 O (15th Moon no U → (Otsuirorishin, E1 Figure 1
Claims (1)
て半導体基板の一部を露出させる工程と、 前記露出部を含め全面に第1の半導体層を形成する工程
と、 前記第1の半導体層を異方性エッチングすることにより
、前記開口部の絶縁膜の側壁にのみ該第2の半導体層を
残存させる工程と、 前記開口部に底部の露出している半導体基板上に第2の
半導体層をエピタキシャル成長させる工程とによりなる
ことを特徴とする半導体装置の製造方法。[Claims] A step of forming an insulating film on a semiconductor substrate and then opening the insulating film to expose a part of the semiconductor substrate, and forming a first semiconductor layer on the entire surface including the exposed part. a step of anisotropically etching the first semiconductor layer so that the second semiconductor layer remains only on the sidewall of the insulating film in the opening; a bottom portion of the first semiconductor layer is exposed in the opening; A method for manufacturing a semiconductor device, comprising the step of epitaxially growing a second semiconductor layer on a semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26025785A JPS62120017A (en) | 1985-11-20 | 1985-11-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26025785A JPS62120017A (en) | 1985-11-20 | 1985-11-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62120017A true JPS62120017A (en) | 1987-06-01 |
Family
ID=17345532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26025785A Pending JPS62120017A (en) | 1985-11-20 | 1985-11-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62120017A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007220808A (en) * | 2006-02-15 | 2007-08-30 | Toshiba Corp | Semiconductor device and its manufacturing method |
-
1985
- 1985-11-20 JP JP26025785A patent/JPS62120017A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007220808A (en) * | 2006-02-15 | 2007-08-30 | Toshiba Corp | Semiconductor device and its manufacturing method |
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