JPS6149450A - 半導体用リ−ドフレ−ム - Google Patents

半導体用リ−ドフレ−ム

Info

Publication number
JPS6149450A
JPS6149450A JP59172048A JP17204884A JPS6149450A JP S6149450 A JPS6149450 A JP S6149450A JP 59172048 A JP59172048 A JP 59172048A JP 17204884 A JP17204884 A JP 17204884A JP S6149450 A JPS6149450 A JP S6149450A
Authority
JP
Japan
Prior art keywords
layer
alloy
copper
lead frame
alloy layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59172048A
Other languages
English (en)
Inventor
Osamu Yoshioka
修 吉岡
Ryozo Yamagishi
山岸 良三
Norio Okabe
則夫 岡部
Hideaki Sato
英昭 里
Sadao Nagayama
長山 定夫
Yoshiaki Wakashima
若島 喜昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Hitachi Ltd
Original Assignee
Hitachi Cable Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd, Hitachi Ltd filed Critical Hitachi Cable Ltd
Priority to JP59172048A priority Critical patent/JPS6149450A/ja
Publication of JPS6149450A publication Critical patent/JPS6149450A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
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    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はIC等半導体装置に用いられる半導体用リード
フレームに関する。
[従来の技術] 一般に樹脂をモールドしてなるICパッケージを製造す
る場合、例えばSiチップからなる半導体素子をリード
フレームに接合するペレットボンディングおよびSiチ
ップとリードフレームとを金の極細線等で配線するワイ
ヤボンディングを行なう。そしてこれらの配線部に樹脂
をモールドしてICパッケージを製造する。リードフレ
ーム材には、アンバー(Fe −36%Ni)、コバー
ル(Fe、、−29%Nt−19%Co)、4270イ
(Fe−42%Ni>などの鉄系合金材が主に使用され
るが、これらの材料は比較的高価であることから、最近
はより安価な銅または銅合金材が使用されるようになっ
てきている。
一方リードフレームには、ペレットボンディングおよび
ワイヤボンディング時に安定した接合を得るため、一般
にめっき等により表面に銀層が設けられるが、貴金属の
量を減らす意味から最近はこの銀層をリードフレームの
必要部分く半導体素子固定部および内部リード端子部)
にのみ設けることが行なわれている。しかし、このため
、銅または銅合金材からなるリードフレームの場合、ペ
レットボンディング、ワイヤボンディングおよび樹脂モ
ールド時にそれぞれ熱処理を受けると、銀層て覆われた
部分以外の銅面において酸化が進行し、脆い酸化膜が形
成される。銅の酸化膜は、銅素地との密着性が弱く、こ
のため樹脂をモールドした場合湿気(水分)がすき間を
通って浸入し、半導体素子表面の配線を腐食しやすくす
る欠点がある。
この欠点を改良するため、銅表面に防錆効果を有するN
i層を設けて銅の酸化を防止した構造のリードフレーム
が提案されている。(特開昭54−34760)Lかし
、一般にI−Cパッケージは電子機器に組み込む際の接
合性を確保するため、リードフレームの外部リード端子
部に溶融半田あるいは錫めっき層を設けるが、前記リー
ドフレームによれば、Ni層がその表面に強固な酸化膜
を形成するため、外部リード端子部の溶融半田ぬれ性を
低下させる欠点がある。そこで、さらに前記Ni層を半
田ぬれ性の良好なNi−Sn合金層に替えたり、Ni層
上にNi −Sn合金層を設けた構造のリードフレーム
が提案されている。(特開昭54−81777) [発明が解決しようとする問題点コ しかしながら、前記リードフレームによれば、Ni−S
n合金層は銀との密着性が悪く、特にめっきによる銀層
が剥離しやすい欠点がある。また、ICパッケージを低
温長時間劣化すると、銅とNiまたはNi−’Sn合金
との間に脆い金属間化合物が成長し、これが原因となっ
て曲げ等の加工が加わることにより外部リード端子部の
半田あるいは錫めっき層が剥離しやすい欠点があること
が分かった。
本発明の目的は、前記した従来技術の欠点を解消し、銀
層および半田または銀めっき層との接合性を改良するこ
とにより著しく信頼性に優れたICパッケージを製造す
ることができる半導体用リードフレームを提供すること
にある。
[問題を解決するための手段] 上記目的を達成するため、本発明のリードフレームは、
銅または銅合金からなる金属基体上にBまたはPを含有
するN1合金層を下地層として設けた後、Ni−Sn合
金またはCo−Sn合金層を設け、次いで半導体素子固
定部および半導体素子と金属線で配線される内部リード
端子部に銅または銅合金層、および銀層を順次設けたも
のである。
[作用] 上記において、BまたはPを含有するNi合金層は普通
電気めっきまたは化学めっきにより設ける。その組成は
、Pを含有するNi合金層の場合は、Pの含有量は0.
3〜15重量%、通常は約8重量%である。また、Bを
含有するNi合金層の場合は、Bの含有量は0.1〜3
重量%、通常は約0.3重量%である。B、P以外には
、CO2Fe。
Sn、Wなどの元素を含有しても良い。このようにBま
たはPを含有するNi合金層は、低温長時間劣化しても
金属基体である銅または銅合金との間に脆い金属間化合
物を生成せず、前記鋼または銅合金およびNi −Sn
合金またはCo−Sn合金層とそれぞれ緊密に接合する
。また、溶融半日または錫に対するぬれ性もきわめて良
好である。
上記において、銅または銅合金層は、Ni−GO合金ま
たはC0−Sn含金層と銀層との間に存在して両金属と
容易に接着しやすいため、接着剤的な効果を発揮して銀
層の接合性、特に接合強度を著しく改善する。
Ni−Sn合金またはGO−Sn合金は、Niよりも半
田付性に優れた耐食性の合金であり、そして何よりも樹
脂との密着性に優れた合金である。
[実施例] 次に添付図面を参照し、本発明半導体用リードフレーム
の実施例を説明する。
第2図はプレスにより所望のパターンに打抜かれたIC
リードフレームの平面図、第1図はペレットボンディン
グおよびワイヤボンディング後のICリードフレームの
一部断面図である。
第1図によれば、銅合金からなる金属基体1上にその全
表面にp−N+合金層11を下地層として設けた後、N
i−Sn合金層2を設ける。そして、半導体素子固定部
7および3iペレツトの半導体素子4とAIJ線5で配
線される内部リード端子部8に、それぞれ銅層12を中
間層として設けた後、銀層3を表面に設ける。このあと
ICパッケージを製造する場合は、第3図のように配線
部を樹脂モールド21して製造する。なお、6は半導体
素子4をペレットボンディングするために使用されるA
Qペースト等のロウ材である。
この第1図の構造のリードフレームについて具体例を説
明すると、厚さ0,254.の銅合金からなる金属基体
1上に、P−Ni合金めつき浴(亜リン酸含有電気P−
Niめっき浴)を用いた電気めっき法により厚さ1μの
P−Ni合金層11を設け、ざらにNi −8μ合金め
つき浴(ビロリン酸浴)を用いた電気めっき法により厚
さ0゜5μのNi−8μ合金層2を設ける。次に、半導
体素子固定部7および内部リード端子部8に、それぞれ
シアン化銅めっき浴を用いた電気めっき法により厚さ0
.1μの銅層12を設けた後、この銅層12の上にシア
ン化銀めっき浴を用いた電気めっき法により厚さ3μの
銀層3を設ける。最後にシアン浴中で陽極的に余分、な
銅層12を溶解除去して、(リードフレームを作成する
一方、ここで上記実施例と比較するため、従来例に係る
リードフレームを作成したので、これを第3図を用いて
説明する。すなわち、第3図において、銅合金からなる
金属基体1上に電気めっきによりその全表面にNi−8
μ合金層2を設け、このNi−8μ合金層2上に電気め
っきにより部分的に銀層3を設けてリードフレームを作
成した。
第3図ではさらにロウ材6を用いて半導体素子4を半導
体素子固定部7にベレットボンディングし、前記半導体
素子4と内部リード端子部8の銀層3をAu線5で配線
し、これらの配線部を樹脂モールド21してICパッケ
ージを製造した。
ここで、上記実施例に係るリードフレームと従来例に係
るリードフレームの特性を比較するため、それぞれ次の
方法により評価を行ない結果を表に示した。
イ、リードフレームを大気中400″CX2分間加熱劣
化後、粘着テープビーリング法により銀層3の密着性を
調べた。判定は、Oが剥離せず、×が剥離したである。
口、樹脂モールド21により封止した後、外部端子部9
にこれを曲げて溶融半田めっき層を設けたICパッケー
ジを大気中150°CX100〜500hr加熱劣化し
、再び外部リード端子部9を曲げて前記半田めっき層が
剥離するか否かを調べると共に、金属間化合物の成長の
有無を確認した。判定は、Oが半田めっき層剥離せず、
△が半田めっき層一層剥離、×が半田めっき層剥離した
である。
ハ、大気中400℃×2分間加熱後のリードフレームを
樹脂モールドし、リードフレームと樹脂との密着性を引
張強さをもって調べた。判定は、○は引張強さ7に’j
f/cr1以上で密着性良好、△が引張強さ7〜5Kg
f/crJで密着性やや良、Xが引張強さ5に9f/c
M未満で密着性が不良である。
[発明の効果] 以上のように、本発明の半導体用リードフレームによれ
ば、Ni−Sn合金はCo−8l1合金層の下地層とし
てBまたはPを含有するNi層を設け、ざらにNi−S
n合金またはCo−Sn合金層と銀層との間に銅または
銅合金層を中間層として設けたから、上記表からも明ら
かなように従来のリードフレームと比較して高温短R間
または低温短時間加熱劣化後の特性の低下が著しく少な
く、銀層の密着性、半田の剥離強度および樹脂との密着
性を改善することによりIC等のパッケージの信頼性を
著しく向上させることができる。
【図面の簡単な説明】
第1図は本発明の一実施例に係る半導体用リードフレー
ムの一部断面図、第2図は半導体用り一ドフレームの平
面図、第3図は従来例に係るICパッケージの一部断面
図である。 1;金属基体、2:1−Sn合金層、3;銀層、4:半
導体素子、5;Au線、6;ロウ材、7;半導体素子固
定部、8:内部り〜ド端子部、9;外部リード端子部、
11;P−N合金層、12;銅層、21;樹脂モールド
・。

Claims (1)

    【特許請求の範囲】
  1. (1)銅または銅合金からなる金属基体上にBまたはP
    を含有するNi合金層を下地層として設けた後、Ni−
    Sn合金またはCo−Sn合金層を設け、次いで半導体
    素子固定部および半導体素子と金属線で配線される内部
    リード端子部に銅または銅合金層、および銀層を順次設
    けてなることを特徴とする半導体用リードフレーム。
JP59172048A 1984-08-17 1984-08-17 半導体用リ−ドフレ−ム Pending JPS6149450A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59172048A JPS6149450A (ja) 1984-08-17 1984-08-17 半導体用リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59172048A JPS6149450A (ja) 1984-08-17 1984-08-17 半導体用リ−ドフレ−ム

Publications (1)

Publication Number Publication Date
JPS6149450A true JPS6149450A (ja) 1986-03-11

Family

ID=15934565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59172048A Pending JPS6149450A (ja) 1984-08-17 1984-08-17 半導体用リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS6149450A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077116A (ja) * 1993-06-19 1995-01-10 Riidomitsuku Kk 半導体装置用リードフレーム
US5704494A (en) * 1995-06-16 1998-01-06 Nihon Plast Co., Ltd. Disc holder
US5782361A (en) * 1995-06-26 1998-07-21 Kakizaki Manufacturing Co., Ltd. Thin-plate supporting container
US6613451B1 (en) * 1998-09-11 2003-09-02 Nippon Mining & Metals Co., Ltd. Metallic material
US6696753B2 (en) 2002-05-17 2004-02-24 Denso Corporation Enhancement of wire bondability in semiconductor device package
DE4313980B4 (de) * 1992-04-28 2005-08-04 Denso Corp., Kariya Integrierte Hybridschaltung und Verfahren zu deren Herstellung
JP2016025244A (ja) * 2014-07-22 2016-02-08 Shマテリアル株式会社 リードフレーム及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4313980B4 (de) * 1992-04-28 2005-08-04 Denso Corp., Kariya Integrierte Hybridschaltung und Verfahren zu deren Herstellung
JPH077116A (ja) * 1993-06-19 1995-01-10 Riidomitsuku Kk 半導体装置用リードフレーム
US5704494A (en) * 1995-06-16 1998-01-06 Nihon Plast Co., Ltd. Disc holder
US5782361A (en) * 1995-06-26 1998-07-21 Kakizaki Manufacturing Co., Ltd. Thin-plate supporting container
US6613451B1 (en) * 1998-09-11 2003-09-02 Nippon Mining & Metals Co., Ltd. Metallic material
US6696753B2 (en) 2002-05-17 2004-02-24 Denso Corporation Enhancement of wire bondability in semiconductor device package
JP2016025244A (ja) * 2014-07-22 2016-02-08 Shマテリアル株式会社 リードフレーム及びその製造方法

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