JPS6148742B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a priority determination method used in an information processing apparatus employing a microprogram control method.

Generally, in this type of information processing apparatus, there are a plurality of types of interrupt signals, and when various types of interrupt signals are generated, the interrupt processing is executed for the one with the highest priority among them.

Conventionally, the priority for interrupt processing at this time was all determined by hardware.
Therefore, the conventional method has had the disadvantage of complicating the hardware configuration.

The present invention has been made in view of the above-mentioned circumstances, and is made by effectively using firmware to determine priorities for multiple types of interrupt processing requests.
The purpose of this paper is to provide a priority determination method that reduces the burden on hardware.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 101 denotes a control storage unit (hereinafter P-
102 is an auxiliary control storage section (hereinafter referred to as E-ROM) in which the microaddress of the second step in a normal microinstruction is stored; 103 is the microaddress or microaddress read from this E-ROM 102; A register (hereinafter referred to as E-REG) 104 temporarily stores branch microinstruction designation addresses generated by interrupt signals ( _TYPE A, B, C) classified by type (TYPE A, B, C), which will be described later. ROM address register (hereinafter referred to as RA) that specifies the address of the microstep, 105 is E-REG103
a selector that selects and outputs one of the addresses stored in the RA 103, the branch destination address (RD) read from the P-ROM 101, the OP code (operation code), and the address stored in the RA 103;
A decoder 106 decodes control data read from the P-ROM 101.

FIG _. 2 shows the main structure of the present invention, which corresponds to the part surrounded by the dotted line in _FIG .
- When an interrupt occurs, the output line of the ROM 102, E/I, prohibits the output of the E-ROM 102 until the interrupt processing is completed based on the interrupt check timing, and instead enables the output of the gate described later. Interrupt control signal for T _YPE
A, B, and C are interrupt signals obtained when a large number of interrupt signals are classified into three groups according to priority, and here, the interrupt signal level or priority for each group is expressed as T _YPE A>T _YPE B> _TYPEC . G ₁ , G ₂ , G ₃ are the interrupt signals _TYPE A,
B and C are input separately, and the above interrupt control signal E/I is input in common.
This is a gate that outputs a signal "1" when there is an interrupt signal _TYPE A that is unique to itself when I indicates that there is an interrupt, and this gate G ₁ , G ₂ , G ₃
The output is the output line AL ₀ of the E-ROM102 above.
~ AL ₁₁ (in the figure, G ₁ is connected to AL ₉ , G ₂ is connected to AL ₁₀ , and G ₃ is connected to AL ₁₁ ) by wire OR.

FIG. 3 shows the storage part in the P-ROM 101, which is the gist of the present invention. At addresses 1 to 7, there are branch microinstructions (Bu-
C, Bu-B, Bu-A) are stored (hereinafter this storage part Z will be referred to as the branch microinstruction table),
In addition, addresses 4 to 7 of the table Z above are placed at addresses A to An.
an interrupt processing routine of _TYPE A specified by the branch microinstruction Bu-A stored at the address;
Addresses B to Bn contain interrupt processing routines of TYPE B specified by the branch microinstruction Bu-B stored in addresses 2 and 3 of table Z, _and interrupt processing routines C to Bn.
At address Cn, an interrupt processing routine of _TYPE C specified by the branch microinstruction Bu-C stored at address 1 of table Z is stored.

To describe the operation with reference to the time chart shown in FIG. 4, in the final microstep X of a certain instruction processing, the OP code of the next instruction is output from the selector 105, and the P-ROM 101 access reads the control data in the first step of the instruction,
Further, an interrupt check timing (IRCT) is generated and an input strobe signal of the E-REG 103 is generated. Next, in the first microstep Y of instruction processing, the contents of E-REG103 (the second step microaddress of the instruction) are transferred to the selector 1.
05, the contents of the E-REG 103 become the source address of the P-ROM 101, and the P-ROM 101 is accessed based on this. Also, in other steps, +1 was added.
The content of RA 103 or the branch destination address (RD) in the branch instruction read from P-ROM 101 becomes the source address of P-ROM 101.

Now, to explain in detail the operation in the final step of the instruction, in this final step (X), as mentioned above, the interrupt check timing (IRCT) and the input strobe signal of the E-REG 103 are generated, but at this time, the interrupt control signal E If /I indicates that there is no interrupt, the output of the E-ROM 102 becomes valid, and the microaddress read from the E-ROM 102 (second step microaddress of the instruction) is strobed into the E-REG 103. Furthermore, when the interrupt control signal E/I indicates that there is an interrupt, the output of the E-ROM 102 is prohibited, and instead of this, the interrupt signal T
Logic signals output from gates G ₁ , G ₂ , and G ₃ receiving _YPEs A, B, and C are strobed to E-REG 103 as addresses of P-ROM 101 . That is, for example, when the interrupt signal _TYPEC is generated, "1" is output from the gate _G3 and the E-ROM
The signal contents on the output lines AL ₉ , AL ₁₀ , AL ₁₁ of 102 are “0, 0, 1” indicating address 1,
Furthermore, when the interrupt signals _TYPE B and C are generated, "1" is output from the gates G ₂ and G ₃ , and the signal contents on the output lines AL ₉ , AL ₁₀ and AL ₁₁ are "0" and "1" indicating the address 3, respectively. 1, 1”, and if interrupt signals _TYPE A, B, and C are occurring together, the gate
“1” is output from G ₁ , G ₂ , G ₃ and the output line
The signal contents at AL ₉ , AL ₁₀ , and AL ₁₁ are "1, 1, 1" indicating address 7, and the signal contents (address) according to the generation status of such type-specific interrupt signals are strobed to the E-REG 103. Ru. At this point, priority processing has not yet been performed. Therefore, in the first step (Y) of the command, E-
The contents of REG 103 are output from the selector 105, and the P-ROM 101 is accessed based on this contents. However, when an interrupt occurs, the output of the E-ROM 102 is prohibited as described above, and instead, a type-specific interrupt is Since the signal content (address) corresponding to the signal generation state is stored in the E-REG 103, access to the P-REG 101 is from 1 to
This is performed for the branch microinstruction table (Z portion) at address 7. For example, interrupt signal _TYPE A,
If B has occurred, address 6 of the P-ROM 101 is accessed, and the branch microinstruction Bu is stored at address 6.
-A is stored, the program jumps to the _TYPE A interrupt processing routine, and the _TYPE B interrupt signal, which has a lower priority than the _TYPE A interrupt signal, is ignored. Also, if interrupt signals _TYPE B and C are generated, address 3 of P-ROM 101 is accessed,
Since the branch microinstruction (Bu-B) is stored at address 3, the program jumps to the _TYPE B interrupt processing routine, and the _TYPE C interrupt signal, which has a lower priority than the _TYPE B interrupt signal, is ignored. Ru. When an interrupt occurs in this way, the state of the type-specific interrupt signal (T _YPE A, B, C) at that time becomes the address of the branch microinstruction table in the P-ROM 101, and it is retrieved based on this address. The branch microinstruction specifies an interrupt processing routine for the interrupt signal with the highest priority among the generated interrupt signals.
Therefore, the hardware for determining priorities for various interrupt processing requests is significantly simplified.

As described in detail above, according to the present invention, it is possible to provide a priority determination formula that can realize priority determination for a plurality of types of interrupt processing requests with a simple hardware configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the main structure of FIG. 1 in detail, and FIG. FIG. 4 is a diagram showing an instruction table and an accompanying interrupt processing routine, and is a time chart for explaining the operation in the above embodiment. 101... Control storage unit (P-ROM), 102...
... Auxiliary control storage unit (E-ROM), 103 ... Register (E-REG), 104 ... ROM address register (RA), 105 ... Decoder, AL ₀ to _{AL 11} ...
Output line, G ₁ , G ₂ , G ₃ ... gate.

Claims (1)

[Claims] 1. Store multiple types of interrupt processing branch instructions in a predetermined area in the control storage unit, and perform interrupt processing with the highest priority based on the input state of the interrupt signal, starting from the address specified by each branch instruction. means for storing a routine; means for directing a plurality of types of interrupt signals to a portion of the address lines of the control storage section according to a predetermined priority; and input states of the interrupt signals guided by the means; and means for reading a corresponding interrupt processing branch instruction from the address of the control storage section obtained based on the above, and reading a corresponding highest priority interrupt processing routine based on the read branch instruction. Priority determination method.