JPS6161413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to data processing when areas with different privilege levels are provided in the main memory of a computer.

Data processing equipment typically has multiple operating modes with different privilege levels, with lower privilege levels disallowing the execution of instructions that affect the system operating environment, and higher privilege levels disallowing the execution of instructions that affect the operating environment of the system. Configure to allow use of instructions.
Instructions in operating modes with different privilege levels are stored in different areas within the main memory, and the present invention relates to transition control when program execution control is passed across different areas.

An example of a conventional device of this type is shown in FIG. In FIG. 1, 1 is an instruction address register, 2 is a main memory, and 2, 4, and 5 are different areas, and the different areas have different privilege levels. 6 is an instruction stored at one address in the main memory 2, 7 is a buffer register that stores the instruction 6, and 8 is a code section indicating the type of instruction in the buffer register 7 (in the example in FIG. A code indicating that the instruction is a branch instruction is stored.), 9
1 is a branch address section storing a branch destination address when the instruction in the buffer register 7 is a branch instruction; 10 is a comparator; and 11 is a signal line.

The upper few bits of the address indicating the location of an instruction stored in main memory 2 indicate the area to which the instruction belongs, and as mentioned earlier, this area is divided according to privilege level. do. For example, if main memory 2 is composed of n = 2 ^N areas, the area can be specified by the upper N bits of the address, and in the example shown in Figure 1, the branch destination area number is If the branch source area number is smaller than or equal to the branch source area number, the branch is valid and the branch instruction is executed normally, but if the branch destination area number is greater than the branch source area number, execution of the branch instruction is inhibited. do.

In the example shown in FIG. 1, the address of instruction address register 1 specifies instruction 6, and instruction 6 is once input to buffer register 7. If the code part 8 is decoded here, it can be seen that this instruction 6 is a branch instruction. In the case of a branch instruction, the comparator 10 checks whether the area indicated by the address in the instruction address register 1 and the area indicated by the branch destination address in the branch address section 9 are the same. In normal cases, it is not necessary to compare all addresses with comparator 9, and as in the example explained earlier, n=
If there are ^2N areas and the area is specified by the upper N bits of the address, only these N bits need to be compared. Furthermore, as in the above example, if the branch is valid if the branch destination area number is smaller than or equal to the branch source area number, the number indicated by the N bit of the instruction address register 1 and the number indicated by the N bit of the branch address field 9 are If the latter number is equal to or smaller than the former number, the branch instruction held in the buffer register 7 is executed;
If not, the comparator 10 outputs an error signal to the signal line 11, and execution of the branch instruction is inhibited.

Conventional devices are configured as described above, so when passing control to a certain area using a branch instruction, for example, control is passed from an area whose number is greater than or equal to the number of that area. It is possible to set the branch instruction to be valid in all cases, and not execute in all other cases, but for branches from other areas, any area specified in advance, regardless of the order of area numbers. There was a drawback that it was not possible to arbitrarily set in advance for each area the settings to allow branching from this area and to prohibit branching from other areas.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones. Branch control information is provided for each area of the main memory, and the validity of the branch is checked using this information, and branching is performed between each area. It is an object of the present invention to provide a data processing device that can arbitrarily set in advance whether or not the data is valid.

Embodiments of the invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. Branch validity check section 15 is a signal line. The branch control information table 12 has an entry corresponding to each area of the main memory. Therefore, when the number of areas is n, it has n entries, and each entry corresponds to the number of areas (n ) has a bit length of n
The logic of each bit is set in advance depending on whether branching from the corresponding area is permitted or prohibited. For example, area-1
If you want to allow branching from area 3 and prohibit branching from area -24, set the logic of the first bit to ``1''.
The logic of the second bit is set to "0". Further, the entries in the branch control information table 12 are read out via the branch control information table reading section 13 using the upper N bits (2 ^N =n) of the branch address section 9 . In the branch control information table 12, branching from the self area is always permitted, so the bit corresponding to the self area is always set to logic "1", and this is so to speak redundant information, so the branch control information table 12 From the above, it can be said that this is a table that stores information about whether or not to allow branching from each area other than the self-area, but in reality, it is a table that stores information about whether or not to allow branching from each area other than the self-area, but in reality, it corresponds to the self-area in order to make the table easier to read. It also contains bits.

Next, the operation of the circuit shown in FIG. 2 will be explained. Instruction 6 is read at the address of instruction address register 1, inputted to buffer register 7, and when the code section 8 is decoded and the contents of buffer register 7 is found to be a branch instruction, comparator 10 reads instruction 6 from the instruction address register. Comparing the address of 1 and the address of branch address section 9 is similar to the operation of the circuit shown in FIG. Further, if a numerical example similar to that explained with reference to FIG. 1 is used, only the upper N bits of the instruction address register 1 and the upper N bits of the branch address section 9 need to be compared. However, this comparison only compares whether or not the N bits of both match. If they match, the branch is in the same area, so the branch instruction in buffer register 7 is executed; if they do not match, the branch instruction is executed in a different area. This means branching to signal line 1.
A signal is output to the branch control information table reading section 13 and the branch validity checking section 14 to start their operations. The branch control information table reading section 13 reads the entry corresponding to the branch destination area from the branch control information table 12 using the upper N bits of the branch address section 9, and sends it to the branch validity checking section 14. The branch validity check unit 14 checks the branch source area (upper N of the instruction address register 1) in the sent entry.
Check whether this branch is valid by examining the logic of the bit corresponding to
Execute the branch instruction, and if it is not valid, signal line 15
The buffer register 7 outputs an error signal to suppress the execution of the instruction in the buffer register 7.

Since the above control is performed, according to the present invention, when focusing on a certain area, the areas where branching to that area is possible and the areas where branching is not possible are arbitrarily set in advance, regardless of the privilege level. control flexibility can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional device.
FIG. 2 is a block diagram showing one embodiment of the present invention. 1...Instruction address register, 2...Main memory,
3, 4, 5... Area of main memory, 6... Instruction on main memory, 7... Buffer register, 8... Code part of buffer register, 9... Branch address part of buffer register, 10 ... comparator, 12 ... branch control information table, 13 ... branch control information table reading section, 14 ... branch validity checking section. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A branch control information table that divides the computer's main memory into multiple areas and stores information on whether or not to permit branching from each area other than the area for each area, and There is an instruction address register that stores the address of the instruction to be read, a buffer register that stores the instruction read according to the address of the contents of this instruction address register, and an instruction stored in this buffer register that is a branch instruction. At some point, a part of the contents of the instruction address register is compared with a part of the branch address part in the contents of the buffer register, and the area of the main memory defined by the instruction address register is compared with the area of the buffer register. A comparator detects whether or not the areas of the main memory defined by the branch address field are the same, and a comparator detects whether or not the areas of the main memory defined by the branch address field are the same, and the corresponding branch control information table is detected based on the contents of the branch address field of the buffer register. A branch control information table reading section reads out the information of the area, and when the output of the comparator indicates that the areas are not the same, the branch control information table reading section reads out the information of the area. and a branch validity check section for checking branch control information for the area defined by the buffer register and determining whether or not to execute the branch indicated by the contents of the buffer register.