JP3454854B2 - Memory management device and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management device and method for controlling memory access.

[0002]

2. Description of the Related Art In recent years, with the development of network technology and parallel computer technology, a method has been spreading in which a plurality of programs share data and cooperate to perform processing, such as server / client type programming. It was

In this system, each program is
Since they are placed in different address spaces using the virtual memory technology, data must be exchanged through the operating system (OS) in order to share the data, and the processing is performed by the OS overhead. It had the drawback of slowing down the speed.

Therefore, a method is also used in which a plurality of threads, which are execution subjects, are run in one address space, and data is shared between the threads without the overhead of the OS.

Since this method does not originally consider protection between threads, it is necessary to adopt a method with a large overhead in order to protect the data used by one thread from another thread.

That is, a different address space is assigned to each thread by using the protection function of each address space,
Only the part that can be accessed by the thread will be placed in each address space. This has a large overhead and is not practical. The above is the first problem,
In other words, the type of access permitted for each thread in one program cannot be changed.

In order to create an address space for each thread, a page table must be prepared for each virtual space, and the same program must be placed in the same position in different address spaces. Then, even for areas that can be accessed in common by multiple threads, all threads that are allowed access have the same logic-
Since it is necessary to duplicate the physical address conversion information in the page table, the memory used as the page table is wasted.

Of course, as long as the permitted access methods of the areas commonly accessed by a plurality of threads are the same, those threads can share one page table portion and the memory used as a page table can be shared. Waste can be eliminated, but even in this case TLB
When a page table cache such as (Translation Look-aside Buffer) is used, waste occurs and the average speed of address translation is reduced.

To explain the reason, first, since one entry in the page table cache has a pair of page table information and thread number, if the thread is different, the page table information is exactly the same. Will use a different cache entry.

Therefore, the same logical-physical address pair but different thread numbers occupy a plurality of entries in the cache, and the types of physical addresses that can be stored in the page table cache are reduced. As much as the size of the cache is reduced, the speed of address translation is reduced.

Further, since the information for the same page placed in a plurality of page tables must be managed, the paging process becomes complicated. For example, if multiple threads are mapping the same physical page to their virtual address spaces and you try to page out that page, all virtual spaces that map that physical page will be searched for and It is necessary to invalidate the corresponding page table entry.

Further, at the time of page-in, it is necessary to correct the entry of the page table corresponding to the page in all address spaces sharing the physical page to be page-in. These processing times are added to the average address conversion time. The above is the second problem, namely, the problem that the page table and the cache memory of the page table are wasted, and the management becomes complicated and inefficient.

Further, as another method, it is effective for some applications to divide one address space into a plurality of areas and change the authority of the thread depending on which area of the program the thread is executing. Is. For example, the data in area A can be changed only by the thread executing the program in another area B (the thread executing the program in area C cannot change the data in area A). By doing so, it becomes possible to change the data in the area A while maintaining a certain condition. Database data in area A,
If an access routine for accessing the data is put in the area B by a database program, the database data is protected in the database processing, and the OS is
Because you can access that data without going through
High-speed access is possible.

However, in the conventional memory management device (for example, the Intel 80486 processor), the range of the program executed by one thread is limited by using the segment method or the like, and is different by using the call gate. Although it was possible to change the access authority by moving to the access level, the access level has an order relation, and when the level increases, all areas accessible below that level can be accessed, and Since the number of levels is limited by hardware, there is a drawback that it lacks flexibility such that only the control of access rights having an order relation such as an application program, an OS and a kernel can be used.

The above is the third problem, that is, when programs and data are arranged in a plurality of areas in one address space, the type of access permitted for each area cannot be flexibly changed. It is a point.

[0016]

As described above, in the conventional memory management device, when protection is performed among a plurality of execution subjects (threads) executing in one address space,
Since there are many address spaces that map the same physical page, when paging is performed, all address spaces are searched, the ones to which the page is mapped are searched, and the paging process is performed for them. There is a first problem that the overhead is large because it must be done.

Further, since many entries in the page table for the same physical address are occupied, address translation for other physical addresses is hindered, and the page table entry is shared by a plurality of programs. There is a drawback that it is invalidated regardless of whether it has been done, and unnecessary processing is performed to fill the entry. In addition, when the correctness of the access right possessed by a plurality of programs must be simultaneously checked, there is a drawback in that the processing involved in the checking becomes complicated. That is, there is a second problem that the same information is plurally stored in the page table and the page table cache, the memory is wasted, the effect of the cache is weakened, and the efficiency is inefficient.

Further, dividing one address space into complicated areas and changing the authority of the thread depending on which area of the program the thread is executing means that the conventional memory management device is flexible. There was a third problem that it could not be done.

The present invention has been made in view of the above circumstances, and manages an address space shared by a plurality of programs, can appropriately control access authority for memory access, and can also perform address translation. It is an object to provide a memory management device that does not extend time.

[0020]

A memory management apparatus according to the present invention which solves the first problem described above activates a plurality of threads (execution subjects) to execute programs allocated to a virtual space in parallel. Is provided in the computer for converting the logical address to the physical address,
Means for storing the number of the thread currently executing the program, means for storing information indicating which thread can access the logical address, and a thread having the thread number attempts to access the logical address. In this case, a verification means for verifying whether or not the thread trying to access is authorized to access by using the information indicating whether the access is possible, and the validity of the access is guaranteed by this verification means. In this case, the conversion result from the logical address to the physical address is output.

A memory management device according to the present invention which solves the second problem described above is provided in a computer that executes a program assigned to a virtual space, and is provided for a plurality of addresses held in an address translation table. A means for detecting a match with an instructed address and outputting an address paired with the instructed address when the match is detected, each of the address pairs in the address conversion table; A means for storing a plurality of access protection information, and a thread (execution subject) from a position in the virtual space of the program being executed or executing the program with reference to the plurality of access protection information. It is characterized by comprising means for verifying whether or not access to the designated address is permitted, and means for outputting the verification result. To.

A memory management device according to the present invention which solves the third problem described above is provided in a computer that executes a program allocated to a virtual space divided into a plurality of areas, and is used to convert a logical address to a physical address. A means for performing conversion, which detects a region in which a program accessing the logical address is located, and a program in which the logical address is located in the virtual space. Means for storing information indicating accessibility, and access from the area where the access instruction is placed using the information indicating accessibility when an access instruction to the logical address appears during program execution And a verification means for verifying whether or not is valid, and when the validity of the access is guaranteed by this verification means, the logic And outputs a conversion result from the dress to physical addresses.

[0023]

According to the first aspect of the present invention, since there is information indicating whether or not each thread can access each area (position) in the address space in the memory management device, the currently executing thread can be identified. By verifying whether the currently executing thread has the right to access the area (position) of the access destination, access control for each different thread in the same address space becomes possible.

Here, a thread is an execution subject, and C
It is a unit of proportion of PU. That is, the OS manages information for controlling the current execution in addition to the memory such as the register of the CPU for each thread number. The OS has a memory area for saving these pieces of information, and when switching threads, the contents of this area and the registers of the CPU are exchanged to realize execution switching. Also called the context.

According to the second aspect of the invention, a plurality of access protection information can be held corresponding to each entry of the page table (correspondence table of logical addresses and physical addresses) in the memory management device. The memory usage of the page table and its cache is greatly reduced, and the efficiency is improved, as compared with a system that can hold only a single access information as in the method.

According to the third aspect of the invention, the memory management device has information indicating from which area each area (position) of the address space can be accessed, and the area currently being executed can be identified. It is possible to verify whether the currently executing program has the right to access the area (position) of the access destination, and it is possible to perform access control for different areas in the same address space.

[0027]

【Example】

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of the memory management device of the same embodiment. In this case, the memory management device 1
Is the address translation device 2, TLB (Translation Look-as
ide Buffer) checking device 3, thread number storage unit 4,
It is composed of a protection fault signal generation circuit including an OR gate 5.

Then, the memory management device 1 receives a logical page number from the CPU (not shown), that is, the upper 20 bits of the logical address, the logical address at which the instruction currently being executed exists, that is, the program counter PC one instruction before (hereinafter LPC). Abbreviated) and the 3 bits 13 of the memory access mode of the CPU are fetched, and the physical page number, that is, the upper 20 bits 14 of the physical address
Is output. In this case, the currently executed thread number is stored in the thread number storage unit 4, and the upper 20 bits 11 of the logical address, the upper 20 bits 12 of the LPC, and the memory access mode 3 of the CPU are set.
The currently executed thread number stored in bit 13 and the thread number storage unit 4 is simultaneously given to the address translation device 2 and the TLB check device 3 so that the two modules perform the same address translation in parallel. Become.

Here, the address translation device 2 translates a logical page number into a physical page number using a page table (address translation table existing in the main memory). On the other hand, the TLB checking device 3 checks whether or not the target logical address exists in the correspondence between the logical address and the physical address cached in the TLB, and when found, outputs the physical page number corresponding to it. , Sends a TLB hit of 16 to the address translation device 2.

When the address translation device 2 receives the TLB hit 16, the address translation operation for translating the logical page number into the physical page number is stopped. Also, T
The LB check device 3 sets the target logical page number to T
When the address is not found in the LB, the TLBmiss signal line 17 is asserted, the translation by the address translation device 2 is waited for, and the entry in the address translation table at the third stage, which is the final stage, is found. , Its contents are stored in the TLB, and the physical page number is output from it. When it is determined that the page table entry corresponding to the target logical address does not exist in the address translation device 2, a page fault 18 is generated and the CP
Interrupt U. Further, when it is found that access to the address is not permitted during address translation in either of the modules, a protection fault 19 is generated and the CPU is interrupted.

FIG. 2 shows a schematic configuration of the TLB check device 3. In this case, the components of the entry of the TLB 31 are the logical page number 311 and the physical page number 3
12, five flags 313 and 31 indicating page attributes
4, 315, 316, 317 and 3 sets of thread number 3
18, LPC upper 20 bits 319, and a set of permissions of RWX (R indicates a read right, W indicates a write right, and X indicates an execute right), which is the type of access permitted to these threads. In the following description, a set of the thread number 318, the LPC upper 20 bits 319, and the RWX permission will be referred to as an access control list, or ACL for short. This ALC indicates what kind of access is permitted to the logical page to be accessed when which program is executing code on which logical page.

In this case, the TLB entry further has a flag area, the flag (V) 313 indicates a valid flag indicating whether the TLB entry is valid, and the flag (D) 314 indicates whether the page has been changed. A dirty flag, a flag (R) 315 is a referenced flag indicating whether the page has been accessed, and a flag (M) 316 is a more flag indicating whether or not the ACL for the page exists in a group other than the three sets existing in the TLB, and a flag ( E) 317 includes an enable flag E indicating whether or not to check the ACL of the page. Further, the ACL has three flags 320, 321, and 322 for the thread number 318 and the LPC upper 20 bits 319. In this case, the flag (PE) 320 indicates whether or not to compare the thread numbers, the flag (TE) 321 indicates whether or not to perform comparison by the upper 20 bits of the LPC, and the flag (B) 322 indicates the thread number. It indicates whether to check only the matching of thread numbers or to check the magnitude relationship of thread numbers when performing comparison.

Therefore, the logical page number of 2 from the outside
When the entry of TLB 31 is specified by 0 bit 11, 20 bits of thread number, upper 20 of LPC
Bit 12 and 3 bits 13 of the access mode of the CPU are connected by the couplers 32 and 33, and the output 331 of 43 bits
Is obtained, and this is compared with the ACL cached in the TLB 31 by using the three comparators 34, 35 and 36. Here, the upper 20 bits 12 of the LPC is an example of the area number of the area of the virtual space described later.

FIG. 3 shows a schematic configuration of the comparators 34, 35 and 36. In this case, the comparators 34, 35, 36
Are the same as each other, so that only the comparator 34 will be described here. It is composed of adders 341 and 342, AND gates 343 to 346, OR gates 347 and 348, and NOR gates 349 and 350.

Then, such a comparator 34 has an ACL
By setting the flag (PE) 320 of 1 to 0, it is possible to omit the check of the access condition by the thread number, and to give common access permission to all threads. Further, when the flag (TE) 321 is set to 0, the access condition is not determined based on the LPC value, and the thread having the thread number written in the ACL entry has the page regardless of the LPC value. Allows you to give permission to. Further, when the flag (B) 322 is set to 1, it is assumed that the access condition by the thread number is satisfied when the currently executed thread number is greater than or equal to the ACL program number, and the flag (B) 322 is set. When is 0, the access condition by the thread number is satisfied only when the two thread numbers are equal.
Further, by setting the flag (B) 322 to 1, the thread number is used as a level in ring protection, and a stronger right is given to a thread having a large thread number.

The comparator 32 has two output signal lines 351 and 352. Here, the output signal line 35
In the output of 2, the thread number of the thread currently being executed matches the thread number written in the ACL,
And it is asserted when the upper 20 bits of the previous program counter PC (LPC) matches the upper 20 bits of the program counter LPC in the ACL.
That is, the condition of memory access by the CPU is A
It is shown that it matches the CL condition.
Further, the output of the output signal line 351 is asserted when the output of the output signal line 352 is asserted and the memory access by the CPU is of a type permitted by the ACL. That is, if the output of the output signal line 351 is asserted, the memory access is permitted.

Then, returning to FIG. 2, each of the comparators 34, 3
If the result of ORing the outputs of the output signal lines 351 of 5 and 36 is 1, it means that the access is permitted by one of the three ACLs in the TLB entry.
Physical page number 14 is enabled and TLB hit signal line 16 is asserted. In addition, each comparator 34, 35,
If the result of the logical sum of the outputs of the output signal lines 352 of 36 is 1 and the result of the logical sum of the outputs of the output signal line 351 is 0, among the three ACLs in the TLB entry, There are some memory access conditions that match the memory access conditions, but the memory access mode by the CPU is
It indicates that the type was not allowed by the CL. In this case, the signal line 38 is asserted and the protection fault 191 is asserted.

The result of the logical sum of the outputs of the output signal lines 352 of the comparators 34, 35 and 36 is 0, and TL
When the more flag 316 of the B entry is 0, it indicates that there is no ACL that matches the current memory access condition. In this case, the signal line 40 is asserted and the protection fault 191 is asserted.

Enable flag 317 of TLB entry
, The signal line 41 is asserted and the TLB hit signal line 16 is asserted. Therefore, the physical page number 14 is output regardless of the ACL check. Also,
If TLB does not hit, TL as described above
The Bmiss signal line 17 is asserted. Since there is a possibility that the physical page number will be known by the address translation device 2 operating at the same time, the ACL is checked at the same time as waiting for the result.

Further, when the TLB is hit but the ACL entry is not hit and the more bit (M) 316 is 1, the ACLmiss signal line 20 is asserted. The ACL is checked by the address translation device 2 operating at the same time. Next, FIG. 4 shows a schematic configuration of the address translation device 2.

In this case, the first-stage address translation device 2
The first-stage address translation device 22 and the third-stage address translation device 23 are included. Then, such an address translation device 2 takes in 20 bits 15 of the thread number, upper 20 bits 12 of the LPC, 3 bits 13 of the access mode of the CPU and 20 bits 11 of the logical page number, and takes 20 bits of the logical page number. The page table entry 24 of the physical page corresponding to 11 is output. Further, when the TLB hit 16 and the protection fault 191 are received, the address translation is stopped. Furthermore, in the middle of address translation, if a physical page corresponding to the target logical page exists, but it is found that the access mode is of a type that is not permitted, a protection fault 192 is output and the address translation is performed. When it is determined that the physical page corresponding to the target logical page does not exist in the middle of, the page fault 18 is output. The first-stage address translation device 21 determines the entry of the first-stage page table using the root pointer 25 and the upper 7 bits 111 of the logical page number.

In the second stage address translation unit 22, the first address 26 of the second stage page table found by the first stage address translation unit 21 and the 7 bits from the upper 8th bit to the upper 13th bit of the logical page number are used. The entry number 112 in the page table shown is used to determine the entry in the second page table.

In the third stage address translation device 23, the entry number 113 in the page table indicated by the top address 27 of the third stage page table and the lower 6 bits of the logical page number found by the second stage address translation device 22.
Is used to determine the entry in the third page table.
FIG. 5 shows a schematic configuration of the first-stage address translation device 21 and the second-stage address translation device 22.

In this case, the address translation devices 21, 22
Is the 20th bit of the thread number 15 and the upper 20 of the LPC
43-bit signal line 211 that connects bit 12 and CPU access mode bit 3 13; TLB hit 1
6, 7-bit portion 111 of consecutive logical page numbers
(112), route pointer 25 (start address 26)
Is taken in, and the 7-bit portion 111 (112) in which the logical page number is continuous and the root pointer 25 (start address 26) are combined by the address combiner 212, whereby the page table entry 213 corresponding to this logical page number is stored. I'm trying to get the address.

The page table entry 213 is provided with a pointer 2131 to the next level page table, three types of flags 2132 to 2134, three sets of ACLs, and the remaining ACLs when the ACL for the page table entry exceeds three sets. It is composed of a pointer 2135 that points to the place where

Here, three types of flags 2132 to 213 are set.
The valid flag (V) 2132 out of 4 indicates whether the page table entry is valid. The more flag (M) 2133 indicates whether or not the ACL corresponding to the page exists in a group other than the three sets existing in the page table entry. Enable flag (E) 2134
Indicates whether to check the ACL.

When the position of the page table entry is determined, the contents of the valid flag 2132 are checked and this value is set to 0.
If so, the page fault 18 is output, the address translation stop device 227 is activated, and the address translation is stopped.

Further, the input of the 43-bit signal line 211 and the contents 214 of the three ACLs 214, 215 and 216 are simultaneously compared by using the three comparators 217, 218 and 219, and access is permitted according to the result of this comparison. If so, signal 220 is asserted and the value of pointer 2131 to the next level page table is enabled. If it is determined that the access is not permitted, the signal 221 is asserted and the protection fault 192 is output.

On the other hand, an AC that matches the current access condition
If L is not found among the three, the more flag 2133 is checked. Then, the more flag 2133
Is 0, it means that there is no other ACL, so that the access is not permitted, the signal 223 is asserted, and the protection fault 19
2 will be output. Further, when the more flag 2133 is 1, it means that there is another ACL, so the signal 224 is asserted, and the ACL switching device 2
25 of the next page table entry 226 pointed to by the next ACL pointer 2135.
The group is switched to L and the comparison is performed again.

In this case, if there is no more ACL set pointed to by the pointer 2135 that matches the current access condition, the more bit 226.
It is checked whether 2 is 1, and if it is 1, the ACL switching device 225 switches again to the ACL set of the next page table entry pointed to by the pointer 2261 to the next ACL, and re-comparisons are performed. In addition, TLB hit 16
When the address conversion is received, the address conversion stop device 227 stops the conversion process. FIG. 6 shows a schematic configuration of the third-stage address translation device 23.

In this case, the address translation device 23 uses 20 bits 15 of the thread number and 1 higher 20 bits of the LPC.
2, the 43-bit signal line 231, which connects the 3 bits 13 of the CPU access mode, the TLB hit 16, the lower 6-bit portion 113 of the logical page number, and the start address 27 are taken in, and the lower logical page number By synthesizing the 6-bit portion 113 and the head address 27 by the address synthesizer 232, the address of the page table entry 233 corresponding to this logical page number is obtained.

The page table entry 233 has a physical page number 2331 and five types of flags 2332 to 233.
6 and 3 sets of ACLs, and a pointer 2337 pointing to the place where the remaining ACLs are placed when the ACLs for the page table entries exceed 3 sets.

Here, three types of flags 2132 to 213 are set.
The valid flag (V) 2332 of 4 indicates whether the page table entry is valid. The dirty flag (D) 2333 indicates whether the page has been changed. The referenced flag (R) 2334 indicates whether or not the page is accessed. A more flag (M) 2335 indicates whether or not the ACL corresponding to the page exists in a group other than the three sets existing in the page table entry. Then, the enable flag (E) 23
Reference numeral 36 indicates whether to check the ACL.

When the position of the page table entry is determined, the content of the valid flag 2332 is checked and this value is 0.
If so, the page fault 18 is output, the address translation stop device 247 is activated, and the address translation is stopped.

Further, the input of the 43-bit signal line 231 and the contents 234, 235, 236 of the three ACLs are simultaneously compared by using the three comparators 237, 238, 239, and access is permitted according to the result of this comparison. Signal 240 is asserted, the set of physical page number 2331 and flags 2332 to 2336, and three ACs.
A 192-bit output 2338, which is the concatenation of the L contents 234-236, is enabled. If the access is found to be unauthorized, the signal 241 is asserted and the protection fault 192 is output.

On the other hand, an AC that matches the current access condition
If L is not found among the three, check the more flag 2335. If the more flag 2335 is 0, it means that there is no other ACL, so that access is not permitted, and the signal 24
2 is asserted, and the protection fault 192 is output. If the more flag 2335 is 1, it means that there is another ACL, so the signal 243 is asserted, and the ACL switching device 245.
Is used to switch to the ACL set of the next page table entry 246 pointed to by the pointer 2337 to the next ACL, and the comparison is performed again.

In this case, if there is no more ACL set pointed to by the pointer 2135 that matches the current access condition, the more bit 226.
It is checked whether 2 is 1, and if it is 1, the ACL switching device 245 switches to the ACL set pointed to by the pointer 2461 to the next ACL and the comparison is performed again.

FIG. 7 shows a state in which access is permitted by comparison after switching the ACL set once. The same parts as those in FIG. 6 are designated by the same reference numerals. ing. In this case, the page table entry 233
Physical page number 2331 and flags 2332 to 2336
Output and a 192-bit output 24 obtained by concatenating the three ACL contents 247 to 249 of the page table entry 246.
62 will be enabled.

In this embodiment, the ACL described in the entry of the page table in the memory management device is fixed to the upper 20 bits of the LPC, but in this case, the size of the access source area is fixed. If the size of a region is variable or a plurality of regions can be collectively expressed by one ACL, flexibility increases. In that case, as shown in FIG. 12, a mask area 322 (maximum number of bits equal to the number of LPC upper bits) is further provided in one ACL, and comparison is performed according to this mask. If a similar mask area is further added to the thread number in the ACL, it is possible to control access by grouping a plurality of threads.

Further, although the subtracters 341 and 342 are used to compare the thread number and the LPC in the configuration of the comparator for verifying the access right in FIG. 3, even if this is replaced with a logical operation unit. Good. In this case, as an example, an AND operator is used instead of the subtractor 342. The upper part of the address space is arranged in a system such as an OS, and the lower part is arranged in an application program. LPC
If the upper 20 bits 319 contain hexadecimal 80000, the value of the LPC upper 20 bits 12 is 80 hexadecimal.
When it is 000 or more, the output of the AND operator becomes 1. In other words, access from system programs is allowed,
Access from the application program is denied. In this way, it becomes possible to replace various logic operation units and combinations thereof.

Further, in the present embodiment, the address translation device of three stages is used to obtain the physical address from the logical address, and the ACL check is performed in each stage, but the ACL check is performed only in the final stage. It is also possible to adopt a configuration in which ACL check is not performed in the first and second stages. [Example 2]

As described above, in the first embodiment, the means for solving the first, second and third problems of the prior art are collectively shown.
Here, of the above-described embodiments, means for solving the first problem of the related art will be taken out and described as a second embodiment. First, the determination of access authority will be described.

In FIG. 8, a plurality of threads 81 and 82 exist in the logical address space 80. The page table 85 is a part of FIG.
The thread 81 having the thread number 1 tries to execute the instruction 83 for accessing the memory at a certain address. Here, the instruction 83 means to load the data at address 1234 in hexadecimal notation. First, from the page table 85, the entry corresponding to the page where the address to be accessed exists is selected. Next, the thread number detection unit 86 detects the currently executing thread number and selects the entry of the protection information having the thread number that matches this thread number.

The type of access permitted in the thread, which is written in this entry, is input to the access type detection unit 84. 84 detects whether or not the type of access being executed is included in the types of access permitted to the thread, and sends the result to the physical address / protection fault signal output unit 87. When access is permitted, the 87 outputs the physical page number corresponding to the number of the logical page to be accessed and the offset within the logical page as a physical address. When access is not permitted, a protection fault signal is output.

According to the contents of the page table 85 in FIG. 8, the page having the logical page number 1 can be read and written by thread 1 but cannot be executed, and cannot be read and written by thread 2, but can be executed. It is supposed to be. In this way, different access privileges can be given to multiple threads running in one address space.

More specifically, when a thread tries to access a certain logical page, the entry corresponding to the logical page in the page table is selected, and whether the logical page is valid or not is determined. The page fault detection unit 88 detects whether or not the physical memory is allocated by the flag, and if it is invalid or not allocated, an interrupt signal is generated as a page fault.

In other cases, a comparator is used to determine whether or not there is a plurality of fields of thread numbers which are permitted to be accessed in the entry and which match the thread number of the currently executed thread. Use to detect. When a plurality of comparators are prepared and compared in parallel, the time required for comparison is the time required for one comparison.

If there is no matching field,
An interrupt signal is output as a protection fault. If there is a matching field, check whether the type of access the thread is trying to do is included in the type of access allowed for that thread.
Detect using a comparator. The comparison time can be shortened by performing this comparison at the same time as detecting the matching of the thread numbers. If inclusion is not detected, an interrupt signal is output as a protection fault. When the inclusion is detected, the physical page number corresponding to the logical page being accessed is output.

When the OS switches the thread to be executed in one address space by scheduling, the number of the thread under execution stored in the thread number storage section in the memory management device is changed. As a result, at the time of subsequent address translation, the thread number after the change and the thread number that can access the logical page are checked for coincidence. Since the page tables relating to a plurality of threads executing in one address space are gathered together, when the OS performs paging, the logical table of the corresponding entry of the page table is
It suffices to rewrite the part of the physical address corresponding to the part of the physical address and update the flag indicating whether or not the physical page corresponding to the entry exists. [Embodiment 3] Further, in the first embodiment, the third embodiment
A means for solving the above problem will be taken out and explained as a third embodiment. First, the determination of access authority will be described.

In FIG. 9, the logical address space 90 is
It is divided into a plurality of regions 91, 92, 93. The page table 96 is a part of FIG. When an instruction 94 for accessing a memory at a certain address is executed while the program in the area 91 is being executed, first, the entry corresponding to the page where the address to be accessed exists is selected from the page table 96. Be done. Next, the area number detection unit 97 detects the area number of the area in which the program currently being executed is present, and selects the entry of the protection information having the area number that matches this area number.

The type of access permitted in the program in the area written in this entry is input to the access type detection unit 95. 95 detects whether the type of access being executed is included in the types of access permitted to the program in the area, and sends the result to the physical address / protection fault signal output unit 98. . When the access is permitted, the 98 outputs the physical page number corresponding to the logical page number to be accessed and the offset in the logical page as a physical address. When access is not permitted, a protection fault signal is output.

According to the contents of the page table 96 of FIG. 9, the page having the logical page number 10 cannot be read / written from the area 1 but can be executed, and the page can be read / written from the area 2 but cannot be executed. Has become. In this way, different access rights can be given to multiple programs in one logical address space.

The size of the area into which the logical address space is divided may be any unit such as 1 byte unit, page unit or 1 megabyte unit. Also, the page size may be determined as desired.

More specifically, when the access authority is changed depending on the area where the program executed by the thread is placed, the address at which the instruction being executed exists, that is, the number of high-order bits of the immediately preceding program counter. Is used as the number of the region of the program currently being executed.

First, the page fault detection unit 99 detects whether or not the logical page to be accessed is valid, and whether or not the physical memory is allocated when it is valid, and if it is invalid or allocated. If not, generate an interrupt signal as a page fault.

Next, the area number of the area in which the program to be accessed is placed and the logic in the page table--
A comparator is used to detect whether or not the numbers of the access-permitted areas stored for each correspondence of physical addresses match. If there is no matching area number, an interrupt signal is output as a protection fault. When there is a matching number, the comparator detects whether the type of access to be executed from now on is included in the types of access permitted from the area. If the inclusion is not detected, an interrupt signal is output as a protection fault. When the inclusion is detected, the number of the physical page corresponding to the logical page being accessed is output. [Fourth Embodiment] Further, a modified example of the part of the first embodiment which solves the third problem of the conventional art will be described as a fourth embodiment. First, the determination of access authority will be described.

In FIG. 10, logical address space 100
Is divided into a plurality of areas 101, 102, 103. If the instruction 104 for accessing the memory at a certain address is executed while the program in the area 101 is being executed, the area number detecting unit 108 detects the area number of the area where the program currently being executed exists. Next, using the area number, the ACL table 10
7. Select the ACL entry for the corresponding region number of 7. Next, the protection information entry having the page number where the address to be accessed exists is selected.

The type of access permitted for the access destination page written in this entry is input to the access type detection unit 105. 105 detects whether or not the type of access being executed is included in the type of access permitted for the page of the access destination, and if not, outputs a protection fault signal.

According to the contents of the ACL table 107 in FIG. 10, the logical page number 1 starts from the area having the area number 1.
0 cannot be read / written, but can be executed only, and logical page number 11 can be read / written, but cannot be executed. In this way, different access rights can be given to multiple programs in one logical address space.

The size of the area into which the logical address space is divided may be any unit such as 1 byte unit, page unit or 1 megabyte unit. Also, the page size may be determined as desired.

More specifically, when the access authority is changed depending on the area where the program executed by the thread is placed, the address at which the instruction being executed exists, that is, the number of high-order bits of the immediately preceding program counter. Or is used as the number of the region of the program currently being executed.

First, the page fault detection unit 110 detects whether the logical page to be accessed is valid and, if valid, whether physical memory is allocated, by the page fault detection unit 110. If or unassigned, generate an interrupt signal as a page fault.

Next, the logical page number of the access destination and the number of the logical page of the ACL table 107, which is stored for each area number of the area in which the program to be accessed is placed, are permitted. A match is detected using a comparator. If there is no matching logical page number, an interrupt signal is output as a protection fault. If there is a matching number,
A comparator is used to detect whether the type of access that is about to be executed is included in the types of access permitted for the page. If the inclusion is not detected, an interrupt signal is output as a protection fault. When it is detected that the protection fault signal is included because it is not output, the physical address output unit 109 outputs the physical page number corresponding to the logical page being accessed.

The ACL table 10 shown in FIG.
Although the ACL entry in 7 is described as a pair of the logical page number of the access destination and the type of access to the page, it may be described as a pair of the area number of the access destination and the type of access to the area. In that case, as shown in FIG. 11, the ACL table 107 is changed to 112, and the newly provided area number detection unit 111 detects the area number corresponding to the address of the access destination, and the AC
Select the corresponding entry in the L table 112. Subsequent processing is the same as in the case of FIG.

In the third embodiment, the verification method of whether the program in the area 1 can access the logical address in the area 2 is used. In the present embodiment, the program in the area 1 is executed while the program in the area 2 is being executed. Although the verification method of whether or not the logical address of can be accessed is adopted, a verification method in which both are integrated can also be adopted by constructing the page table using hash. Further, the page table 106 and the ACL table 107 are separately provided in the present embodiment in order to save the memory capacity.

As described above, according to the first to fourth embodiments, a plurality of threads sharing the logical address space can execute a memory access by executing a program in a plurality of areas. , A plurality of ACLs are stored in correspondence with one entry in the TLB or page table, so that many entries do not occupy the same physical address. You will not have duplicate address pairs. Therefore, the amount of memory occupied by the page table is reduced. Further, the range of logical addresses stored in the TLB (page table cache) is widened, and the TLB hit rate can be improved. Further, it is possible to simultaneously compare each of the plurality of ACLs in the TLB or the page table with the set of the thread number of the thread currently being executed and the area number in which the program being executed is placed. Therefore, the address conversion time can be made equivalent to that of the conventional memory management device.

Further, according to the above-mentioned embodiment, it is possible to divide the miss generated during the search of the TLB into the address miss and the ACL miss, and the part for storing the TLB address and the ACL are separated. The stored portion can be independently replaced with the information in the page table. As a result, even if all the ACLs for the logical page corresponding to the entry cannot be stored in one entry of the TLB, it is possible to replace only the ACL part without invalidating the entry. Therefore, the time required to process the TLB miss can be shortened. This is especially
This is effective when the number of areas in which threads or programs that share a logical address are placed is larger than the number that can be stored in one entry.

In the above-described embodiment, a set of thread numbers and area numbers and types of access permitted to each set are combined for each of a plurality of ACLs held by the page table. However, it is also possible to store only one type of access that is commonly permitted for multiple thread number and area number pairs, or it is possible to store area numbers and types of access for multiple thread numbers. May be commonly stored, or the thread number and the type of access permitted for a plurality of area numbers may be commonly stored. Fine-grained access right control can be performed by storing the access method that is individually permitted for each thread or area. On the other hand, if you store one access method that is shared by a set of threads or areas that allow access, the access right can be controlled. The control is less precise,
The amount of memory used for the page table can be saved.

Further, in the above embodiment, the minimum unit of protection is the physical page unit, but any size can be used as long as it can be managed by the memory management device, and it can be changed like a segment. It may be the amount.

In addition, the second invention of holding a plurality of ACLs in one entry of the page table held by the TLB is applicable not only to how information is stored, but also As the contents of ACL,
The above thread number and LPC upper 20 that is the area number
The present invention can be applied to other than the bit set, and can be implemented by variously changing the configurations of the signal generating circuits and the control circuits, and how to give various control signals. Further, by dividing the page table and the ACL table separately as in the fourth embodiment, it is possible to reduce the total memory amount.

Further, according to the above-described embodiment, in order to verify the correctness of the access right, it is possible to provide not only the number for identifying the thread but also the entry of access information indicating the memory access method for each thread. Therefore, it becomes possible to perform fine access right control for memory access.

Further, according to the above-described embodiment, it is possible to mask all or part of the thread number or area number for each memory access and perform grouping to detect coincidence. This allows for grouped access rights control for memory accesses. Therefore, efficient access right control can be performed.

Further, according to the above embodiment, it is assumed that not only the matching of the thread number or the area number is detected, but also the matching is obtained when the predetermined logical operation result is true such as the magnitude relationship is established. It is possible to perform relative access right control between programs or threads for memory access.

[0095]

Since the present invention is constructed as described above, it has the following effects.

First, by providing a means for storing information on which thread can access the logical address in correspondence with the logical-physical address in the page table, execution in one address space is performed. Multiple threads can be protected without wasting the amount of memory used for the page table.

Further, if a plurality of access protection information is stored for one logical-physical address pair, the amount of memory used for storing one logical-physical address correspondence is reduced, so that the TLB is used. Since the number of logical-physical address correspondences that can be placed in the cache increases and the cache hit rate increases, the average address translation time is shortened.

Then, one address space is divided into a plurality of areas, and when a program existing in which area is executed for one logical-physical address correspondence in the page table, that logical address is By providing a means for storing one or more pieces of information indicating whether or not access is possible, it is possible to give different access rights to a plurality of programs existing in one address space. Therefore, in order to access certain data, be sure to
It can only be done via a certain access program.

Further, when one address space is divided into a plurality of areas and a plurality of threads are executed, which thread is placed in which area in correspondence with the logical-physical address correspondence in the page table. By providing a means for storing the information as to whether the logical page is accessible while the program being executed is being executed, the effects described above are achieved at the same time.

If a plurality of pieces of information indicating whether or not the access is possible are verified in parallel, even if there are a plurality of pieces of protection information for one logical-physical address correspondence, the access right check is protected. It can be done in the same time as if there was only one piece of information.

When checking the legitimacy of access by checking the match between the thread number in the information indicating which thread is accessible and the thread number of the thread that is trying to access, a part of the thread number is With the masking function, thread numbers can be grouped, so the amount of information that must be placed in the page table and the check time can be saved when you want to give the same privilege to multiple threads. .

Similarly, at the time of verification, it is considered that the thread number in the information indicating which thread is accessible and the thread number match based on the result of the logical operation of the thread number of the thread to be accessed. Since the thread number can be grouped by providing the copying function, it is possible to save the amount of information and check time that must be placed in the page table when the same authority is given to multiple threads. I can. Such grouping can be similarly realized for area numbers.

Furthermore, the miss that occurred during the search of the TLB (page table cache) is referred to as an address miss.
It becomes possible to divide into ACL (protected information) mistakes,
Further, the part storing the address of the TLB and the part storing the ACL can be independently replaced with the information in the page table. As a result, even if all the ACLs for the logical page cannot be stored in the entry corresponding to one logical page of the TLB, it is possible to replace only the ACL part without invalidating the entry. Therefore, it is possible to shorten the time required to process the TLB miss and the time required to process the protected information miss.

As described above, according to the present invention, the time required for one-time address conversion is the same as that of the conventional one, the hit rate of the page table is improved, and the time taken for miss processing can be shortened. Also, the protection when a plurality of threads execute an address space divided into a plurality of areas can be flexibly managed by the thread number and the area number without OS intervention. .

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a memory management device of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a TLB check device used in the embodiment shown in FIG.

3 is a diagram showing a schematic configuration of a comparator used in the TLB checking device shown in FIG.

4 is a diagram showing a schematic configuration of an address translation device used in the embodiment shown in FIG.

5 is a diagram showing a schematic configuration of first-stage and second-stage address translation devices used in the address translation device shown in FIG.

6 is a diagram showing a schematic configuration of a third-stage address translation device used in the address translation device shown in FIG.

7 is a diagram for explaining the operation of the address translation device shown in FIG.

FIG. 8 is a schematic configuration diagram showing a second embodiment of the memory management device of the present invention.

FIG. 9 is a schematic configuration diagram showing a third embodiment of the memory management device of the present invention.

FIG. 10 is a schematic configuration diagram showing a fourth embodiment of the memory management device of the present invention.

FIG. 11 is a schematic configuration diagram showing a modification of the fourth embodiment.

FIG. 12 is a diagram showing an example of a configuration for masking all or part of a thread number or a region number.

[Explanation of symbols]

1 ... Memory management device 2 ... Address translation device 3 ... TLB check device 4 ... Thread number storage unit 21, 22, 23 ... Address translator 25 ... Route pointer 212, 232 ... Address synthesizer 217-219, 237-239 ... Comparison 225, 245 ... ACL switching device 227, 247 ... Address translation stopping device 31 ... TLB 32, 33 ... Concatenator 34, 35, 36 ... Comparator 80, 90, 100 ... Logical address space 81, 82 ... Threads 83, 94 , 104 ... Instructions to be executed 84, 95, 105 ... Access type detection units 85, 96, 106 ... Page table 86 ... Thread number detection units 87, 98 ... Physical address / protection fault signal output units 88, 99, 110 ... Page fault detection units 91, 92, 93, 101, 102, 103 ... Areas 97, 108 ... Number detection section 107 of area including address where instruction to be executed ACL table 109 ... Physical address output section 111 ... Number detection section of area including address of destination to be accessed

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Nosue 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center, Inc. (72) Inventor Kenichi Maeda Komukai-shiba, Saiwai-ku, Kawasaki-shi, Kanagawa No. 1 in Toshiba Research & Development Center (72) Inventor Hideo Segawa Komukai Toshiba Town, Komu-ku, Kawasaki City, Kanagawa No. 1 In Toshiba Research & Development Center (72) Inventor Toshio Okamoto Komukai, Kawasaki-shi, Kanagawa Prefecture Toshiba Town No. 1 within Toshiba Research & Development Center Co., Ltd. (56) Reference JP-A-3-228156 (JP, A) JP-A-3-154949 (JP, A) JP-A-3-244054 (JP, A) Kaihei 3-220647 (JP, A) Lee RB. , Precision Architecture, IEEE E COMPUTER, USA, IEEE E, January 1989, Vol. 22, No. 1, p. 78-91 (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 12/08-12/10 G06F 9/46 G06F 12/14

Claims (11)

(57) [Claims] 1. A memory management device for converting a logical address to a physical address, the memory management device being provided in a computer for activating a plurality of threads to execute programs allocated to a virtual space in parallel. The thread number storage means for storing the thread number of the executing thread and the thread number storage means corresponding to one logical page specified by the logical address.
Stores multiple pieces of information, including red numbers, indicating whether access is possible
Possible entry storage means and a thread stored in the thread number storage means When a thread having a thread number attempts to access the logical address, a thread stored in the thread number storage means
Before, which is specified by the link number and the logical address.
The access information stored in the entry storage means is used to access this access information .
A memory management, comprising: a red means for verifying the legitimacy of the access, and outputting the conversion result from the logical address to the physical address when the legitimacy of the access is guaranteed by the verifier. apparatus. 2. The verification means masks all or a part of the thread number of the thread that is trying to access or the thread number in the information indicating whether the thread is accessible, and 2. The memory management device according to claim 1, further comprising means for checking a match between the two. 3. The verification means performs a predetermined logical operation on the thread number of the thread trying to access and the thread number in the information indicating whether the access is possible, and the result of the logical operation. 2. The memory management device according to claim 1, further comprising means for determining whether the thread numbers match each other in accordance with the above. 4. A memory management device provided in a computer for executing a program allocated to a virtual space divided into a plurality of areas, for converting a logical address to a physical address, wherein the logical address is the virtual address. Means for storing information indicating which area in the space is accessible by the program, and this access instruction is placed when an access instruction to the logical address appears during execution of the program. the validity of the access from the area where there are possible the access
And a verification means for verifying using the information indicating whether or not the memory management is characterized by outputting the conversion result from the logical address to the physical address when the validity of the access is guaranteed by the verification means. apparatus. 5. The verification means is an area number of an area where the program to be accessed is placed,
5. The memory management device according to claim 4, further comprising means for masking all or a part of the area number in the information indicating whether the area is accessible and checking for a match between the area numbers. 6. The verification means performs a predetermined logical operation on an area number of an area in which the program to be accessed is placed and an area number in the information indicating whether the access is possible, 5. The memory management device according to claim 4, further comprising means for determining whether the area numbers match according to the result of the logical operation. 7. A theory for instructing a plurality of logical addresses provided in a computer that executes a program assigned to a virtual space and held in an address translation table.
Detects a match between the physical address, a memory management unit having means for said match outputs the instructed physical address becomes the logic address and pairs when detected, the address pair in said address conversion table for each accession including the number of execution subject running the program
Information indicating whether the access is permitted or not and / or the logical address
Where the reply is located in the virtual space
Access, which is information indicating whether it is accessible from the RAM
Means for multiple stores scan protection information, based on said plurality of access protection information, the designated argument from the position of the virtual space of the running program
Whether or not access to the physical address is allowed, and /
Alternatively, the memory is provided with means for determining whether or not access to the designated logical address by the execution subject executing the program is permitted, and means for outputting the determination result. Management device. 8. A theory for instructing a plurality of logical addresses stored in an address conversion table, which is provided in a computer that executes a program allocated to a virtual space.
Memory having detected a match with the physical address, and means for said match outputs the instructed physical address becomes the logic address and pairs when detected, and a cache memory to put a portion of said address translation table A management device, which is provided in the address conversion table, and for each address pair, the number of the executing subject who is executing the program
Information indicating whether or not access is possible, and / or before
The logical address is located in which area of the virtual space
Information that indicates whether the
A first storage unit for storing a plurality of variable pieces of access protection information; and a pair of logical pages identified by logical addresses for each address pair provided in the cache memory .
Accordingly, the number of the executing subject who is executing the program is included.
Information indicating access permission and / or the logic
The address where the address is located in the virtual space.
The information that indicates whether it is accessible from the program
Second storage means capable of storing up to a fixed number of pieces of access protection information, and based on the access protection information of the second storage means, it is determined whether or not access to the designated address is permitted. If the determination means and the determination means cannot make a determination, the contents of the second storage means in the cache memory are replaced with a part of the contents of the first storage means in the address conversion table <br / And a memory management device. 9. A memory management method for performing conversion from a first address to a second address in a computer that activates a plurality of threads to execute programs allocated to a virtual space in parallel. Corresponds to one logical page specified by one address
A plurality of pieces of access permission / prohibition information indicating the permission / prohibition of access including the thread number, the thread number of the thread currently executing the program is stored, and the stored thread number and the first address are stored.
One of the access permission / denial information is specified and
Based on the access permission information, the access
Determining whether or not to permit access to the thread that is trying to do so, and outputting the conversion result from the first address to the second address when determining that the access is permitted. . 10. A memory management method for performing conversion from a first address to a second address in a computer that executes a program allocated to a virtual space divided into a plurality of areas, wherein the first address Stores access permission / prohibition information indicating which area in the virtual space is accessible from the program, and stores the area where the program accessing the first address is located. Detecting whether or not access to the first address from the detected area is permitted, based on the access permission / prohibition information, and if it is determined that the access is permitted, A memory management method comprising outputting a conversion result from one address to a second address. 11. A means for storing a plurality of entries including a logical address and a physical address corresponding to the logical address, and a plurality of programs for each of a plurality of programs permitted to access the logical address corresponding to each of the entries. /> means for memorize the access control information, when attempting to access the logical address to which the currently executing program, corresponding to the given virtual address Surua
Means for detecting whether or not there is a plurality of stored access control information corresponding to the entry that matches the information regarding the program being executed, and detecting that there is A memory for outputting a notification to that effect, and a means for outputting the physical address stored in correspondence with the certain logical address when the notification is output. Management device.