JP3454854B2 - Memory management device and method - Google Patents

Memory management device and method

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Publication number
JP3454854B2
JP3454854B2 JP00393793A JP393793A JP3454854B2 JP 3454854 B2 JP3454854 B2 JP 3454854B2 JP 00393793 A JP00393793 A JP 00393793A JP 393793 A JP393793 A JP 393793A JP 3454854 B2 JP3454854 B2 JP 3454854B2
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Japan
Prior art keywords
address
access
thread
program
number
Prior art date
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Application number
JP00393793A
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Japanese (ja)
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JPH05257811A (en
Inventor
賢一 前田
利夫 岡本
光男 斎藤
滋博 浅野
英生 瀬川
承昊 申
浩志 野末
Original Assignee
株式会社東芝
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Publication date
Priority to JP4-26040 priority Critical
Priority to JP2604092 priority
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP00393793A priority patent/JP3454854B2/en
Priority claimed from US08/021,098 external-priority patent/US5627987A/en
Publication of JPH05257811A publication Critical patent/JPH05257811A/en
Publication of JP3454854B2 publication Critical patent/JP3454854B2/en
Application granted granted Critical
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls memory access.
Memory management device And method It is about. [0002] In recent years, the development of network technology and parallel
With the development of computer technology, for example, server-client type
Multiple programs, like programming
The method of sharing, coordinating, and proceeding with processing has spread
Was. In this system, each program is:
In a separate address space using virtual memory technology
Operating system to share data
Data must be exchanged via the system (OS)
Processing speed is slow due to the overhead of the OS.
There was a disadvantage that it would be. [0004] Therefore, in one address space, the execution
Run multiple threads that are the body and transfer data between threads
Sharing is done without OS overhead
Has also been done. This method originally provides protection between threads.
Because a thread is not thinking,
If you try to protect data from other threads,
You have to take a big way of Bahead. That is, a protection function for each address space is provided.
Use to allocate a separate address space for each thread,
Access each address space from the thread
Only the parts that can be put will be placed. This is quite over
The head is large and not practical. The above is the first problem.
In other words, the number of applications allowed for each thread in one program
Access type cannot be changed.
You. Further, an address space is created for each thread.
Use a page table for each virtual space
The same program must have different addresses
It must be in the same position in space, but this
The area that can be accessed in common by multiple threads.
However, all the threads to which access is permitted have the same logical-
Physical address translation information is duplicated in the page table
Use as a page table because you must have it
Memory is wasted. [0008] Of course, common access by multiple threads
Access areas are the same,
For example, in those threads, one page table part
Can be shared and used as a page table
It is possible to eliminate waste, but even in this case, TLB
A page table such as (Translation Look-aside Buffer)
Waste when using cache
And reduce the average speed of address translation. The reason will be described first.
One entry in the table cache is the information in the page table.
Information and thread number
Are different, even if the page table information is exactly the same,
Will use the cache entry. Therefore, the same logical-physical address pair is
As expected, those with different thread numbers are
Will occupy the page entry
The types of physical addresses that can be stored in the
Gone and cache size was reduced
In the same way as described above, a reduction in the speed of address translation occurs. [0011] Furthermore, it is placed in a plurality of page tables
I have to manage information for the same page
Therefore, there is a problem that the paging process becomes complicated.
You. For example, multiple threads can use the same physical page
When mapping to the virtual address space of
If you try to page out a page, that physical page
Find all virtual spaces that map
Invalidate the page table entry corresponding to the page
Processing is required. [0012] Also, when the page in, the page in.
All addresses that share the physical page being attempted are empty
Page table entry corresponding to the page in between
Must be fixed. These processing times are average
Is added to the conversion time. The above is the second problem.
Of the page table and the page table cache
Memory is wasted and management becomes complicated and inefficient
There is a problem. Further, as another method, one address is empty.
The thread is divided into multiple areas, and the thread
Depending on whether the thread is running
Changing the limit depends on the application
Is valid. For example, you can change the data in area A
Is a program executing a program in another area B.
Red only (executing program in area C
Thread cannot change the data in area A)
For example, the data in the area A is changed while maintaining certain conditions.
It becomes possible. Data of database in area A,
In the area B, access to the data
Access routines can be used for database processing.
To protect the data in the database, and
You can access that data without going through
High-speed access becomes possible. However, a conventional memory management device (for example,
Intel's 80486 processor)
The range of programs executed by the
Use a call gate
Access by moving to a different access level
The permissions could be changed, but the access levels were
Have a relationship, if the level goes up, it will be below that level
That all areas accessible by
And the number of levels is limited by hardware
Application programs and the OS
Access rights with an order relationship such as the kernel
The disadvantage of lack of flexibility is that only control can be used.
there were. The above is the third problem, namely, one address.
Program, data, etc. in multiple areas
When placed, the type of access allowed for each area is flexible
The problem is that it cannot be changed to. [0016] As described above, the conventional memory
Multiple memory management units running in one address space
If you try to protect between the executing entities (threads) of
If there are many address spaces mapping the same physical page
When paging, all ads are
Searching for the address space, the page is mapped
Find things and process them for paging.
That the overhead is large.
There was one problem. In addition, a page is assigned to the same physical address.
Others to occupy many entries in the table
Address translation for physical addresses.
Page table entries can be
Has been disabled, regardless of whether
No, unnecessary processing is performed to fill the entry.
There were drawbacks. In addition, the access
The right of the right to be checked at the same time
However, it is said that the processing related to the inspection becomes complicated.
There were drawbacks. In other words, page tables and page tables
The same information is stored multiple times in the
Is wasted, caches are less effective, and inefficient
There was a second problem. Further, one address space is made into a complicated area.
By dividing the thread,
Change the thread's privileges depending on
Means that conventional memory management devices cannot flexibly
There was a third problem. The present invention has been made in view of the above circumstances.
Management of address space shared by multiple programs
To control access privileges for memory access
Can be performed properly, and the address conversion time can be reduced.
Aim to provide a memory management device that does not extend
Target. [0020] The first problem is solved.
The memory management device according to the present invention includes a plurality of threads.
(Executing subject) is started and the professional assigned to the virtual space
Programs that execute programs in parallel.
Address to physical address,
Remember the number of the thread currently executing the program
And which thread accesses the logical address.
Means for storing information indicating whether the thread is possible, and the thread number
Thread with access attempts to access the logical address
In the case where the
The right to access the thread you are trying to access
Verification means for verifying whether or not there is
If the validity of access is guaranteed by means,
Output the conversion result from physical address to physical address.
And features. According to the present invention, which solves the above second problem,
The memory management device is a program assigned to the virtual space.
Address conversion table provided in the computer that executes the
Address specified for multiple addresses held in
A match with the dress, and when the match is detected,
Means for outputting an address that is paired with the specified address
And wherein in the address conversion table,
Multiple access protection information for each address pair
Means for storing and referring to the plurality of access protection information
And the position of the running program in the virtual space
Or by the thread executing the program (the subject of execution)
Whether access to the specified address is permitted
And a means for outputting the verification result.
It is characterized by having. According to the present invention, which solves the third problem,
The memory management device is a virtual space divided into multiple areas.
Provided in the computer that executes the assigned program
That translates logical addresses to physical addresses.
A program for accessing the logical address.
For detecting the area where the system is located
Where the logical address is located in the virtual space.
Information that can be accessed from the program
Means for storing the logical address during program execution
Is accessible if an access command to access
Area where the access instruction is located using information representing
Verification means to verify whether access from the
Provided, and the validity of access is assured by this verification means.
Is changed from the logical address to the physical address.
And outputting a conversion result. According to the first aspect, an address is added to the memory management device.
Address for each thread for each area (position) in the
Information indicating whether or not the
The currently executing thread can access it.
Verify that you have permission to access the destination area (location)
By doing, different threads in the same address space
Can be controlled. Here, a thread is an execution subject, and C
It is a unit of PU allocation. In other words, the OS is the thread number
Each time the current execution is executed in a memory other than the CPU register, etc.
Manage information to control. This information is deleted during OS.
When switching threads, there is a memory area to save.
The contents of the area and the CPU registers etc.
To switch the execution. Also called context
You. According to the second invention, the memory management device includes
Page table (correspondence between logical address and physical address)
Multiple access protection information corresponding to each entry in
Can be held in a single
Compared to one that can only hold access information
Page table and its cache memory usage
Is greatly reduced and efficiency is improved. According to the third invention, in the memory management device,
For each area (position) in the address space,
Information that indicates whether the
Area so that the currently running program can access it.
Check that you have permission to access the destination area (location).
Authentication for each different area in the same address space.
Access control becomes possible. [Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings.
I do. FIG. 1 shows the whole memory management device of the embodiment.
2 shows the configuration. In this case, the memory management device 1
Is the address translation device 2, TLB (Translation Look-as
ide Buffer) Check device 3, thread number storage 4,
Protection fault signal generation circuit consisting of OR gate 5
It is composed of The memory management device 1 is not shown.
From the CPU to the logical page number, that is, the logical address
20 bits 11, the logical address where the instruction currently being executed exists
Dress, that is, the program counter PC one instruction before (hereinafter
Upper 20 bits of lower LPC), CPU memo
3 bits 13 of the re-access mode are fetched and
Page number, that is, the upper 20 bits 14 of the physical address
Is output. In this case,
The thread number to be stored in the thread number storage 4
The upper 20 bits 11 of the logical address, above the LPC
20 bits 12; 3 for CPU memory access mode
Bit 13 and stored in the thread number storage 4
The currently executing thread number is
2 and the TLB check device 3 at the same time,
Modules perform the same address translation in parallel.
You. Here, the address translator 2 operates as a page
Table (address conversion table existing in main memory)
To convert logical page numbers to physical page numbers. one
On the other hand, the TLB check device 3 is cached in the TLB.
Target in the correspondence between the logical address and the physical address
Checks if a logical address exists and finds it
Output the physical page number corresponding to
And 16 TLB hits to the address translator 2
send. Then, the address translator 2 makes a TLB hit.
When the logical page number is received, the physical page number is
Abort the address translation operation to translate to a number. Also, T
The LB check device 3 sets the target logical page number to T
If not found in LB, TLBmiss signal line
17 is asserted, and the translation is performed by the address translator 2.
Waiting to be performed, the final stage, the third stage address
When a translation table entry is found,
Save the contents in TLB and output the physical page number from it
I do. In the address translator 2, the target logical address
That there is no corresponding page table entry
If it is found, a page fault 18 is generated and the CP
Interrupt U. Also, smell one of both modules
During address translation,
If it turns out that the process is not allowed,
An action fault 19 occurs and interrupts the CPU. FIG. 2 is a schematic configuration of the TLB check device 3.
It is shown. In this case, the entry of the TLB 31
The components are a logical page number 311, a physical page number 3
12, five flags 313 and 31 indicating page attributes
4, 315, 316, 317 and three sets of thread numbers 3
18, LPC upper 20 bits 319, these threads
RWX (R is a read
Permission, W indicates write permission, and X indicates execution permission).
It consists of a set of sessions. In the following description, the thread
Code number 318, LPC upper 20 bits 319, RWX
Access permission list
G, for short, will be called ACL. This ALC is
Program is executing code on which logical page
The logical page you are about to access.
And what kind of access is allowed
It is shown. In this case, the TLB entry further includes
(V) 313 is a TLB entry
Flag, flag indicating whether is valid
(D) 314 is a dirty flag indicating whether the page has been changed.
Lag, flag (R) 315 indicates whether the page was accessed
And a flag (M) 316 indicating
The ACL for the page exists in a group other than the three sets in the TLB.
The more flag indicating whether or not there is, the flag (E) 317 is
Rice indicating whether to check the ACL of the page
Cable flag E. In addition, the ACL
For bit number 318 and upper 20 bits of LPC 319
It has three flags 320, 321 and 322. This
In the case of, the flag (PE) 320 compares the thread numbers.
Indicates whether or not to perform, and the flag (TE) 321 is on the LPC
A flag indicating whether or not to perform comparison using the 20th bit.
(B) 322 is a thread when comparing thread numbers.
Only match the thread number, or
Indicates whether to examine the magnitude relationship. Thus, the external logical page number 2
The entry of the TLB 31 is specified by the 0 bit 11
And the 20 bits 15 of the thread number and the upper 20 of the LPC
Bit 12 and CPU access mode 3 bit 13
43-bit output 331 connected by the connectors 32 and 33
Which is cached in TLB 31
Comparison with ACL uses three comparators 34, 35, 36
Will be performed. Here, the upper 20 bits of LPC
Is an example of an area number of a virtual space area described later.
is there. FIG. 3 is a schematic diagram of the comparators 34, 35 and 36.
It shows the result. In this case, the comparators 34, 35, 36
Are exactly the same, so here
If only the adders 341 and 342,
343-346, OR gates 347, 348, Noage
Ports 349 and 350. The comparator 34 has an ACL
By setting the flag (PE) 320 of the
Check of access conditions by
Can give common permissions to all threads
I am trying to. Also, the flag (TE) 321 is set to 0
In this case, the access condition is determined based on the LPC value.
In other words, the thread number written in the ACL entry
Thread has the page regardless of the value of LPC
To be able to give permission to
You. When the flag (B) 322 is set to 1, the current
The thread number being executed is the program number of the ACL
Access by thread number when greater than or equal to
Flag (B) 322 is satisfied.
If it is 0, the thread will only run if the two thread numbers are equal.
In this case, the access condition based on the code number is satisfied.
Also, by setting the flag (B) 322 to 1, the thread
Thread number as a level in ring protection,
Empowers threads with higher thread numbers
I am trying to. The comparator 32 has two output signal lines.
351 and 352 are provided. Here, the output signal line 35
The output of 2 is the thread number of the currently executing thread.
No. and the thread number written in the ACL match,
And the higher rank of the previous program counter PC (LPC)
20 bits above the program counter LPC in the ACL
Asserted when the value matches the value of the 20th bit.
That is, the condition of the memory access by the CPU
It is shown that the condition matches the condition of CL.
The output of the output signal line 351 is connected to the output signal line 352.
Output asserted and memory access by CPU
Were of the type allowed by the ACL
Sometimes asserted. That is, the output of the output signal line 351
Is asserted, memory access is allowed
become. Returning to FIG. 2, each of the comparators 34, 3
5, the logical sum of the outputs of the output signal lines 351
If the result is 1, three ACLs in the TLB entry
Access will be granted by one of the
Enables physical page number 14 and TLB hit signal
Line 16 is asserted. Further, each of the comparators 34, 35,
The result of ORing the outputs of the 36 output signal lines 352 is
1, the logical sum of the outputs of the output signal lines 351
If the result is 0, the three ACLs in the TLB entry are
There is one that matches the current memory access condition
However, the mode of memory access by the CPU is
That it was of a type not allowed by CL
Is shown. In this case, the signal line 38 is asserted.
Then, a protection fault 191 is asserted. The output signals of the comparators 34, 35, 36
The result of the OR of the output of the line 352 is 0, and TL
If the more flag 316 of the B entry is 0, the current mail
That there is no ACL that matches the memory access condition
Is shown. In this case, the signal line 40 is asserted,
The protection fault 191 is asserted. Enable flag 317 of TLB entry
Is zero, the signal line 41 is asserted and the TLB
The reset signal line 16 is asserted. Therefore, ACL checks
The physical page number 14 is output irrespective of the block. Also,
If the TLB does not hit, the TL
The Bmiss signal line 17 is asserted. Working at the same time
The physical page number is determined by the address translator 2
And wait for the result
The ACL is checked. Further, TLB was hit, but ACL
Does not hit the entry and more bit (M) 316
In the case of 1, the ACLmiss signal line 20 is asserted. same
ACL is operated by the address translator 2 operating at the time.
Checked. Next, FIG.
The schematic configuration is shown. In this case, the first stage address translator 2
1. Second-stage address translation device 22, third-stage address
And a conversion unit 23. And this
Such an address translation device 2 has a thread number of 20 bits.
15, the upper 20 bits of LPC 12, CPU access
13 bits for the logical mode and 20 bits for the logical page number
11 to the logical page number 20 bit 11
Output page table entry 24 of the corresponding physical page
I am trying to do it. In addition, TLB hit 16,
If an action fault 191 is received,
The exchange is also stopped. In addition, address translation
Physical page corresponding to the target logical page
Exists but the mode of access is not allowed
If it turns out to be a protection
192 is output, and the target
It turns out that the physical page corresponding to the physical page does not exist
Output page fault 18
I have. In the first-stage address translation device 21, the route port
The interface 25 and the upper 7 bits 111 of the logical page number are used.
Thus, the entry of the first-stage page table is determined. In the second stage address translator 22, the first stage
The second stage page text found by the address translator 21
Address 26 and upper 8 bits of logical page number
Indicated by 7 bits from the first bit to the upper 13 bits
Using the entry number 112 in the page table
The entry of the second page table is determined. In the third stage address translator 23, the second stage
Third-level page text found by the address translator 22
Address 27 and the lower 6 bits of the logical page number
Entry number 113 in the page table indicated by
Is used to determine an entry in the third page table.
FIG. 5 shows a first-stage address translation device 21 and a second-stage address translation device.
1 shows a schematic configuration of the address translation device 22 of FIG. In this case, the address translators 21 and 22
Is the 20 bits 15 of the thread number, the upper 20
Bit 12, 3 bits of CPU access mode
43-bit connected signal line 211, TLB hit 1
6, a continuous 7-bit portion 111 of the logical page number
(112), route pointer 25 (head address 26)
Of the logical page number
Part 111 (112), route pointer 25 (point
The head address 26) is synthesized by the address synthesizer 212.
And the page table for this logical page number
The address of the entry 213 is obtained. The page table entry 213 stores the next level.
Pointer 2131 to three page tables
2132 to 2134, three sets of ACLs,
Remaining when the ACL for the bull entry exceeds 3 sets
Pointer 2135 that points to where the ACL of
Therefore, it is constituted. Here, three types of flags 2132 to 213 are set.
4, the valid flag (V) 2132 indicates the page
Indicates whether the entry is valid. More flag
(M) 2133 indicates that the ACL corresponding to the page is a page.
Is there any other than the three sets in the table entry?
No. Enable flag (E) 2134
Indicates whether to check the ACL. The position of the page table entry is determined
And the contents of the valid flag 2132 are checked.
If so, output page fault 18 and perform address translation
The suspending device 227 is activated to suspend the address translation. The input of the 43-bit signal line 211 is
The three ACL contents 214, 215, and 216 are divided into three ratios.
At the same time using comparators 217, 218, and 219.
The comparison shows that access is allowed.
Signal 220 is asserted and the next level page
The value of the pointer 2131 to the table is enabled
You. Also, if access is found to be unauthorized
Indicates that the signal 221 was asserted and the protection fault
192 is output. On the other hand, an AC that matches the current access condition
If L is not found among the three,
Check the flag 2133. And the more flag 2133
Is 0, indicating that there is no other ACL
Access will not be granted,
No. 223 is asserted and protection fault 19
2 will be output. Also, the mower flag 2133 is
If it is 1, then another ACL exists.
Therefore, the signal 224 is asserted and the ACL switching device 2
25, using pointer 2135 to the next ACL
AC of designated next page table entry 226
The comparison is performed again after switching to the set of L. In this case, the pointer 2135 indicates
Matches the current access condition in the set of ACLs
If there was nothing more to do,
Check whether 2 is 1 and if it is 1, reselect the ACL switch.
225 by pointer 261 to the next ACL.
Switch to the next page table entry ACL set
Change and compare again. In addition, TLB hit 16
Is received by the address translation suspending device 227
The conversion process will be stopped. FIG. 6 shows the third stage.
3 shows a schematic configuration of a dress conversion device 23. In this case, the address translator 23
20 bits of data number, upper 20 bits of LPC 1
2. Connect 3 bits 13 of CPU access mode
43-bit signal line 231, TLB hit 16, logic
Lower 6 bits portion 113 of page number, start address
27, the lower 6 bits of the logical page number.
The address part 113 and the start address 27 are combined.
By combining the logical page number with the logical page number
Get the address of the corresponding page table entry 233
I am trying to. The page table entry 233 contains a physical page.
Page number 2331, five types of flags 2332 to 233
6, 3 sets of ACLs, for their page table entries
If the number of ACLs exceeds three, the remaining ACLs
Is composed of a pointer 2337 that points
You. Here, three types of flags 2132 to 213 are set.
Valid flag (V) 2332 of 4 is page table
Indicates whether the entry is valid. Dirty hula
(D) 2333 indicates whether the page has been changed or not.
I have. Referenced flag (R) 2334 is on page
This indicates whether or not access has been made. Moaf
Lag (M) 2335 is the page corresponding to the ACL.
Whether there is any other than the three sets in the table entry
Is shown. Then, the enable flag (E) 23
Reference numeral 36 indicates whether to check the ACL. The position of the page table entry is determined
And the contents of the valid flag 2332 are checked.
If so, output page fault 18 and perform address translation
The stopping device 247 is activated to stop the address conversion. The input of the 43-bit signal line 231 is
The three ACL contents 234, 235, and 236 are divided into three ratios.
At the same time using comparators 237, 238, and 239.
The comparison shows that access is allowed.
Signal 240 is asserted and the physical page number
A set of 2331 and flags 2332 to 2336 and three ACs
A 192-bit output linking the contents 234 to 236 of L
2338 is enabled. Also, access is denied
Signal 241 is asserted.
Then, a protection fault 192 is output. On the other hand, an AC that matches the current access condition
If L is not found among the three,
Check the flag 2335. More flag 2335 is 0
If it does, it means there is no other ACL
Therefore, access is not permitted, and the signal 24
2 is asserted and protection fault 192 is exited.
To be able to help. Also, the mower flag 2335 is 1
If there are other ACLs, there are other ACLs
The signal 243 is asserted, and the ACL switching device 245
Is indicated by the pointer 2337 to the next ACL using
Of the ACL of the next page table entry 246
Switch to a set and compare again. In this case, the pointer 2135 indicates
Matches the current access condition in the set of ACLs
If there was nothing more to do,
Check whether 2 is 1 and if it is 1, reselect the ACL switch.
With the pointer 246 to the next ACL
Switch to the set of ACLs pointed to
become. FIG. 7 shows the ratio after switching the ACL set once.
If the comparison shows that access is allowed
The same parts as those in FIG. 6 are denoted by the same reference numerals.
Is shown. In this case, the page table entry 233
Physical page number 2331 and flags 2332 to 2336
And the three ACLs of the page table entry 246
192 bit output 24 with contents 247 to 249 concatenated
62 will be enabled. In this embodiment, the pages in the memory management device
ACL described in the table entry is higher than LPC
20 bits fixed, but in this case, the access source area
Is fixed in size. Variable or multiple area sizes
If you can express all the areas in one ACL,
Increase. In that case, as shown in FIG.
Furthermore, the mask area 322 (up to the same as the number of upper bits of the LPC)
Bits), and compare according to this mask.
You can do it. The same applies to the thread number in the ACL.
Multiple threads can be grouped if additional mask areas are added.
It is possible to perform access control in a loop. In FIG. 3, the access right is verified.
Comparing the thread number and LPC with the configuration of the comparator
In this case, the subtracters 341 and 342 are used.
It may be replaced with a logical operation unit. In this case, for example,
An AND operator is used instead of the operator 342. And ad
The upper part of the address space is for systems such as OS, and the lower part is for applications.
Configuration to be placed in the application program. LPC
80000 in hexadecimal number in upper 20 bits 319
The LPC upper 20 bits 12 value is 80 in hexadecimal
In the case of 000 or more, the output of the AND operator becomes 1. One
In other words, access from system programs is allowed,
Access from the application program is denied
It is. In this way, various logic units and their combinations are
It becomes possible to change. In this embodiment, the logical address is
Uses a three-stage address translator to determine the physical address
And ACL checks are performed at each stage.
However, only the last stage performs an ACL check, and the first and second stages
In this case, a configuration in which the ACL is not checked may be adopted. [Embodiment 2] In the first embodiment, the conventional first and second embodiments
2. Means for solving the third problem have been shown together.
Here, of the above embodiments, the first conventional problem is solved.
A second embodiment will be described as a second embodiment. Ma
The determination of the access authority will be described. Referring to FIG. 8, in the logical address space 80,
Has a plurality of threads 81 and 82. Pe
The table 85 is a part of FIG.
A thread 81 having a thread number 1
Attempt to execute instruction 83 to access memory. This
Here, the instruction 83 is the data of the address 1234 in hexadecimal notation.
Means loading. First, the page table
The address to be accessed exists in the file 85
The entry corresponding to the page to be selected is selected. Next, thread
The thread number currently being executed by the
Number is detected and the thread number that matches this thread number
The entry of the protection information having the number is selected. The thread written in this entry
The type of access allowed to the data
The data is input to the unit 84. 84 is the access being executed
Is included in the type of access allowed to the thread
Is detected, and the result is
It is sent to the action / fault signal output unit 87. 87
If access is allowed, access is being attempted
The physical page number corresponding to the logical page number and the logical page number
Output as physical address with offset within page
Power. If access is not allowed, protection
Outputs a fault signal. According to the contents of page table 85 in FIG.
And the page whose logical page number is 1 is thread 1.
Can read and write, but cannot execute.
Can not read and write, but can execute, etc.
ing. In this way, multiple addresses running in one address space
Separate permissions for a number of threads.
Can be. More specifically, there is a thread.
When trying to access a logical page, the page table
Of the entries corresponding to the logical page are selected.
First, whether the logical page is valid,
If physical memory is allocated
If the page fault detection unit 88 detects the lag,
If invalid or unassigned, the page
Generates an interrupt signal as default. In other cases, multiple entries are included in the entry.
A field containing the number of threads that are allowed to access
Code that matches the currently executing thread number
Is detected using a comparator. Comparison
If you prepare multiple units and compare them in parallel, the time for comparison
Requires only one comparison time. If there is no matching field,
Outputs an interrupt signal as a protection fault
You. If there is a match, the thread returns
The type of access being attempted is not allowed for the thread.
Is included in the type of access being granted,
Detect using a comparator. This comparison is based on the thread number
Shortening the comparison time by performing a match at the same time as detecting a match
Can be shrunk. Must be detected
If a protection fault occurs, an interrupt signal is output.
Power. If it is detected that
Physical page number corresponding to the logical page being
Output. When the OS performs scheduling, one OS
When switching threads to execute in the address space
Is stored in the thread number storage unit in the memory management device.
Have changed the number of running threads. This
In the subsequent address translation, the changed thread number is used.
Number and the thread number that can access the logical page
We will look for a match. In one address space
The page table for multiple threads to execute
When the OS performs paging because it is united
Is the logical-of the corresponding entry in the page table.
Write the physical address part of the corresponding part of the physical address.
Replacement, there is a physical page corresponding to the entry
It is only necessary to update the flag indicating whether or not. [Embodiment 3] Furthermore, of the first embodiment, the conventional third
The means for solving the above problem is taken out as the third embodiment.
Will be explained. First, the access authority determination will be described.
You. In FIG. 9, the logical address space 90 is
It is divided into a plurality of areas 91, 92, 93. page
The table 96 is obtained by extracting a part of FIG. Territory
During execution of the program in the area 91,
Attempting to execute instruction 94 to access memory
To access from the page table 96
The entry corresponding to the page where the address exists is selected
It is. Next, the current execution is performed by the area number detection unit 97.
Detect the area number of the area where the program is being updated
Protection information with an area number that matches this area number
Is selected. The area written in this entry
The types of access allowed to programs in the
It is input to the access type detection unit 95. 95 executed
The type of access that is being performed is
Check whether the access type is
And outputs the result to the physical address / protection format.
To the default signal output unit 98. 98 is allowed access
The number of the logical page being accessed.
Number of the physical page corresponding to the issue and off in the logical page
The set is combined and output as a physical address. Access
If the fault is not allowed, a protection fault signal is issued.
Output. According to the contents of page table 96 in FIG.
And the page whose logical page number is 10
Cannot read and write, but can execute, and read from area 2.
It can be written but cannot be executed. This
As shown, multiple programs in one logical address space
Can be given different access rights. It should be noted that the area for dividing the logical address space is
The size is 1 byte unit, page unit, 1 megabyte unit
Any unit, such as rank, may be used. Also on the page
You can decide the size as you like. More specifically, the thread is executed
Depending on the area where the running program is located.
To change access privileges, change the address where the instruction being executed exists.
Address, that is, the most significant bits of the previous program counter
Is the number of the currently executed program area.
To use. First, the logical page to be accessed is
Is enabled, and if so, physical memory is allocated.
Page is determined by a flag.
Is detected by the default detection unit 99.
If not, an interrupt signal is generated as a page fault.
Occurs. Next, an access program is placed.
Area number of the area that is
The access that is stored for each physical address
Use a comparator to check whether the number of the allowed area matches
To detect. If there is no matching area number,
An interrupt signal is output as an operation fault. Match
If there is a number that is going to be executed
Type of access that is allowed from the area
Use a comparator to detect
You. If it is not detected,
Outputs an interrupt signal as default. Included
Is detected, the logical page being accessed is
Output the number of the physical page corresponding to the page. [Embodiment 4] Furthermore, of the first embodiment, the conventional third
A modified example of the part that solves the problem will be described as a fourth embodiment.
I will tell. First, the determination of the access authority will be described. In FIG. 10, logical address space 100
Is divided into a plurality of areas 101, 102, 103
You. While executing a program in the area 101, an address
To execute the instruction 104 to access the memory of the
Then, the current execution by the area number detection unit 108 is performed.
Area number of the area where one program exists
You. Next, the ACL table 10 is used by using the area number.
7 is selected. Next
Page number where the address to be accessed exists
Is selected as the entry of protection information having Access destination written in this entry
The type of access allowed to the page is the type of access
It is input to the class detection unit 105. 105 is being executed
Type of access to the page
Even if it detects whether it is included in the type of access allowed
If not allowed, output protection fault signal
I do. According to the contents of ACL table 107 in FIG.
Then, from the area whose area number is 1, the logical page number 1
0 cannot be read / written but can only be executed, logical page
Read and write to number 11, but not executable
Has become. Thus, in one logical address space
Give different access rights to multiple programs
Can be done. It should be noted that the area for dividing the logical address space is
The size is 1 byte unit, page unit, 1 megabyte unit
Any unit, such as rank, may be used. Also on the page
You can decide the size as you like. More specifically, when a thread executes
Depending on the area where the current program is located.
To change the address, change the address where the instruction being executed exists.
, That is, how many high-order bits of the previous program counter
Is the number of the currently executed program area.
To use. First, the logical page to be accessed is
Is enabled, and if so, physical memory is allocated.
Of the page table 106 as to whether or not
Page fault detection unit 110 detects
If invalid or unassigned, the page
Generates an interrupt signal as default. Next, the logical page number of the access destination
And the program to be accessed in the ACL table 107.
Is stored for each area number of the area where the program is located.
Whether the number of the logical page that allows access matches
Is detected using a comparator. Matching logical page
If there is no number, a protection fault will be issued.
Outputs the nested signal. If there is a matching number,
The type of access that is about to be performed
Included in the types of access allowed to
Is detected using a comparator. This included
Is not detected, it is assigned as a protection fault.
Outputs the nested signal. Protection fault signal
When it is detected that it is included because it is not output
Is the physical page corresponding to the logical page being accessed.
The page number is output from the physical address output unit 109. The ACL table 10 shown in FIG.
The ACL entry in 7 is the logical page number of the access destination and
The type of access to the page
The access destination area number and the access to that area.
May be described as a pair of the type of the resource. In that case, as shown in FIG.
The bellow ACL table 107 is changed to 112
And the newly provided area number detecting unit 111
The area number corresponding to the access destination address is detected,
Select the corresponding entry in the L table 112. after
Is the same as that in FIG. In the third embodiment, the logical address in the area 2 is
You can access the dress from the program in area 1.
In this embodiment, the verification method of whether
Access to the logical address in area 2 while executing
Verification method is used, but page
Combine the two by constructing the bull using hash
The verification method described above can also be adopted. In this embodiment, the page table
Table 106 and ACL table 107 are provided separately.
This is to save memory capacity. As described above, according to the first to fourth embodiments,
For example, multiple threads sharing the logical address space
By running programs located in several areas
TLB and page text for memory access
Multiple ACLs are stored in one entry in the
To the same physical address.
Occupy many entries, and
Bird has duplicate logical and physical address pairs
Disappears. So the page table occupies notes
The amount of ri is reduced. In addition, TLB (key of page table)
The range of logical addresses stored in the
And the TLB hit rate can be improved. Ma
Each of multiple ACLs in TLB and page table
And the thread number of the currently executing thread
Comparison of the set of area numbers where the program
Can be done simultaneously. For this reason, address translation
The time can be equivalent to a conventional memory management device. According to the above embodiment, the TLB is searched.
Mistakes occurred during address mistakes and ACL mistakes
And TLB address can be
The part for storing and the part for storing ACL are
It can be replaced with the information in the table. to this
Therefore, in one entry of the TLB,
Cannot store all ACLs for the corresponding logical page
Even if the entry is not invalidated,
Can be replaced. Therefore, TLB miss processing
The time required for processing can be shortened. This is especially
Of threads or programs that share logical addresses
The number of placed areas can be stored in one entry.
This is effective when the number is larger than In the above embodiment, the page table is
Thread number and area for multiple ACLs to be stored
Each pair of numbers and the type of access allowed to that pair
Is shown, but multiple threads
Access that is permitted in common for the pair of number and area number
May be stored as a single type.
Area number and type of access allowed for thread number
Even if each class is stored in common, even if multiple area numbers
Thread number and type of access to be allowed are common to each one
You may memorize it. Allowed individually for each thread or region
Fine-grained access rights by remembering the access method
Can control, while allowing threads or regions to allow access
One access method that is allowed to be shared by a set of areas is stored
If you do so, the granularity of access right control will be somewhat reduced,
Saves the amount of memory used as page tables
You. In the above embodiment, the minimum protection unit is
Page, but large enough to be managed by the memory management device.
No matter what size the unit is,
It may be a variable amount like a segment. Other page tables held by the TLB
Of multiple ACLs in one entry
The invention of No. 2 is applicable to any case where information is stored.
In addition to being applicable,
The above thread number and the upper 20 LPCs that are area numbers
It can be applied to other than the set of bits.
Circuit and control circuit configuration, how to apply various control signals, etc.
Can also be implemented with various changes. Moreover, in Example 4
Page table and ACL table separately
Thereby, the total memory amount can be reduced. Also, according to the above embodiment, the access right
A number that identifies the thread to verify correctness
Not only that, but also an
Access information entries,
Perform fine-grained access right control for reaccess
It becomes possible. According to the above embodiment, the memory access
All or part of the thread number or area number for each thread
Matching can be performed by masking and grouping
It becomes. This is grouped for memory access
Access right control can be performed. Therefore, efficiency
Access right control can be performed. Further, according to the above embodiment, the thread number
Alternatively, not only can the area number match be detected, but also
When a predetermined logical operation result is true, for example,
A match can be obtained, and
Relative access between programs or between threads
Rights control can be performed. The present invention is configured as described above.
Therefore, the following effects can be obtained. First, the logical-physical address in the page table
Which thread has its logical address
A means to store information on whether or not
To execute multiple addresses in one address space.
Use thread protection for page tables
Can be done without wasting the amount of memory
come. Further, for one logical-physical address pair,
If multiple pieces of access protection information are stored in
-Memory used to store physical address mappings
Logic that can be placed in the TLB because the amount of
-Cache hits due to increased number of physical address correspondences
Increase the average address translation time.
You. Then, one address space is divided into a plurality of areas.
Into one logical-physical address in the page table.
Programs that exist in which areas
Access to the logical address when executed
Means for storing one or more pieces of information
Multiple programs in one address space
Can be given different access rights. This
Therefore, in order to access certain data,
Only through certain access programs
You can do so. Further, one address space is divided into a plurality of areas.
If you want to split and run multiple threads,
For the logical-physical address correspondence in the
Thread executes the program in which area
The logical page can be accessed when
By providing a means for storing the information
A solid effect is achieved at the same time. A plurality of information indicating whether or not the above access is possible.
If the information is verified in parallel, one logical-physical address
Access rights even if there is more than one protected information
Check in the same time as when there is only one protection information
Can do it. Note that which thread can be accessed is indicated.
The thread number in the information and the
Check the matching thread number of the thread
Mask part of the thread number when verifying validity
Grouping of thread numbers is possible if equipped
Given the same privileges to multiple threads
Information that must be placed in the page table when
The amount and check time can be saved. Similarly, at the time of verification, which thread is accessed
The thread number in the information indicating whether
About the thread number of the thread you are trying to
Assume that thread numbers match based on the result of logical operation
Thread number grouping
Same for multiple threads
Must be placed in the page table if you want to grant
The amount of unnecessary information and check time can be saved
You. Such grouping is the same for area numbers
Can be realized. Further, TLB (cache of page table)
Mistakes that occurred during the search), address mistakes,
ACL (protection information) errors can be divided,
Also, a part for storing the address of the TLB and an ACL are stored.
The part to be stored is independently replaced with the information in the page table.
Can be obtained. As a result, one logical page of the TLB
In the entry corresponding to the logical page
Even if all the ACLs cannot be stored,
You can replace only the ACL part without invalidating
You. Therefore, the time required to process a TLB miss and the protection information
It is possible to reduce the time required for processing a report error. As described above, according to the present invention, one address
Conversion time is the same as before.
The hit rate is improved, and the time required for miss processing can be reduced
Therefore, address translation time can be reduced as a whole.
And multiple threads are divided into multiple areas.
Protection when executing the allocated address space, thread number
Flexible management without OS intervention by using
And can be done.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram showing one embodiment of a memory management device of the present invention. FIG. 2 is a diagram showing a schematic configuration of a TLB check device used in the embodiment shown in FIG. 1; FIG. 3 is a diagram showing a schematic configuration of a comparator used in the TLB check device shown in FIG. 2; FIG. 4 is a diagram showing a schematic configuration of an address translation device used in the embodiment shown in FIG. 1; FIG. 5 is a diagram showing a schematic configuration of a first-stage and second-stage address translation device used in the address translation device shown in FIG. 4; FIG. 6 is a diagram showing a schematic configuration of a third-stage address translation device used in the address translation device shown in FIG. 4; FIG. 7 is a view for explaining the operation of the address translation device shown in FIG. 6; FIG. 8 is a schematic configuration diagram showing a second embodiment of the memory management device of the present invention. FIG. 9 is a schematic configuration diagram showing a third embodiment of the memory management device of the present invention. FIG. 10 is a schematic configuration diagram showing a fourth embodiment of the memory management device of the present invention. FIG. 11 is a schematic configuration diagram showing a modification of the fourth embodiment. FIG. 12 is a diagram showing an example of a configuration for masking all or a part of a thread number or an area number. [Description of Signs] 1 Memory management device 2 Address conversion device 3 TLB check device 4 Thread number storage units 21, 22, 23 Address converter 25 Route pointers 212, 232 Address synthesizers 217 to 219 237 to 239 comparators 225, 245 ACL switching devices 227, 247 address conversion suspending device 31 TLB 32, 33 couplers 34, 35, 36 comparators 80, 90, 100 logical address spaces 81, 82 ... Threads 83, 94, 104 ... Instructions 84, 95, 105 to be executed ... Access type detectors 85, 96, 106 ... Page table 86 ... Thread number detectors 87, 98 ... Physical address / protection fault signal output Units 88, 99, 110: Page fault detection units 91, 92, 93, 101, 1 2, 103: Areas 97, 108: Number detection units 107, 112 of the area including the address where the instruction to be executed exists: ACL table 109: Physical address output unit 111: Number of the area including the address to be accessed Number detector

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroshi Nozue 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the R & D Center (72) Inventor Kenichi Maeda Ken-ichi Maeda Toshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba Corporation R & D Center (72) Inventor Hideo Segawa 1 Toshiba Corporation R & D Center (72) Inventor Toshio Okamoto Toshio Komukai, Kawasaki City, Kanagawa Prefecture No. 1, Toshiba Town Inside the Research and Development Center, Toshiba Corporation (56) References JP-A-3-228156 (JP, A) JP-A-3-154949 (JP, A) JP-A-3-244054 (JP, A) Kaihei 3-220647 (JP, A) Lee RB. , Precision Architecture, IEEE COMPUTER, USA, IEEE E, January 1989, Vol. 22, No. 1, p. 78-91 (58) Field surveyed (Int.Cl. 7 , DB name) G06F 12/08-12/10 G06F 9/46 G06F 12/14

Claims (1)

  1. (57) [Claim 1] A memory that is provided in a computer that activates a plurality of threads to execute a program allocated to a virtual space in parallel, and that converts a logical address to a physical address. A management device, comprising: a thread number storage means for storing a thread number of a thread which is currently executing a program; and a thread corresponding to one logical page specified by a logical address.
    Stores multiple pieces of information including red numbers indicating whether access is permitted
    An entry storage means capable, thread thread with the thread number is stored in the thread number storage means when trying to access the logical address, which is stored in the thread number storage means
    , Which is specified by the read number and the logical address.
    Using the information indicating whether or not the access is stored, which is stored in the entry storage means ,
    And a verification means for verifying the validity of the access of the red, and when the validity of the access is assured by the verification means, outputting a conversion result from the logical address to the physical address. apparatus. 2. The method according to claim 1, wherein the verifying unit masks all or a part of the thread number of the thread to be accessed or the thread number in the information indicating whether or not the thread can be accessed. 2. The memory management device according to claim 1, further comprising: means for checking whether or not there is a match. 3. The verification means performs a predetermined logical operation on the thread number of the thread to be accessed and the thread number in the information indicating whether the access is possible, and obtains a result of the logical operation. 2. The memory management device according to claim 1, further comprising means for judging whether the thread numbers match according to the following. 4. A memory management device provided in a computer that executes a program allocated to a virtual space divided into a plurality of areas and performs a conversion from a logical address to a physical address, wherein the logical address is the virtual address. Means for storing information indicating in which area of the space the program can be accessed; and, when an access instruction to the logical address appears during execution of the program, the access instruction is stored. The validity of access from the area where the
    Verifying means for verifying using information indicating whether the logical address is converted into a physical address when the validity of the access is guaranteed by the verifying means. apparatus. 5. The verification means includes: an area number of an area where the program to be accessed is located;
    5. The memory management device according to claim 4, further comprising means for masking all or a part of the area number in the information indicating whether or not the access is possible and checking whether the area numbers match. 6. The verification means performs a predetermined logical operation on an area number of an area where the program to be accessed is located and an area number in the information indicating whether the program is accessible. 5. The memory management device according to claim 4, further comprising means for judging a match between the area numbers according to a result of the logical operation. 7. provided to the computer for executing a program assigned to the virtual space, is instructed for a plurality of logical addresses stored in the address translation table logical
    Detects a match between the physical address, a memory management unit having means for said match outputs the instructed physical address becomes the logic address and pairs when detected, the address pair in said address conversion table for each accession including the number of execution subject running the program
    Information indicating whether access is possible, and / or the logical
    Where the program is located in any area of the virtual space.
    Access that is information indicating whether the
    Means for multiple stores scan protection information, based on said plurality of access protection information, the designated argument from the position of the virtual space of the running program
    Whether access to the physical address is permitted, and / or
    A memory for determining whether or not access to the specified logical address by an execution entity executing the program is permitted; and a means for outputting the determination result. Management device. 8. provided to the computer for executing a program assigned to the virtual space, is instructed for a plurality of logical addresses stored in the address translation table logical
    A memory for detecting a match with a physical address and outputting a physical address that is paired with the specified logical address when the match is detected; and a cache memory for storing a part of the address translation table. A management device, provided in the address conversion table, for each of the address pairs, a number of an execution subject executing the program.
    And / or information indicating whether access is allowed
    Where in the virtual space the logical address is located
    Information that indicates whether the program can be accessed
    First storage means for storing a plurality of variable pieces of access protection information; and a plurality of address protection information provided in the cache memory .
    In response, contains the number of the executing entity executing the program
    Information indicating whether access is possible or / and the logic
    Where the address is located in any area of the virtual space.
    Information that indicates whether the program can be accessed
    A second storage unit capable of storing a plurality of access protection information up to a fixed number, and determining whether access to the specified address is permitted based on the access protection information of the second storage unit. Determining means, and when the determination is not possible , replacing the contents of the second storage means in the cache memory with a part of the contents of the first storage means in the address translation table. A memory management device comprising: 9. A memory management method for performing a conversion from a first address to a second address in a computer that executes a program allocated to a virtual space in parallel by activating a plurality of threads, Corresponding to one logical page specified by one address
    A plurality of access permission / non-permission information including a thread number indicating access permission / non-permission , a thread number of a thread currently executing a program is stored, and the stored thread number and the first address are used.
    One from the plurality of access permission / denial information
    Based on the access permission information, the access
    Determining whether to permit access to a thread that is trying to perform, and outputting a conversion result from the first address to a second address when it is determined that the access is permitted. . 10. A memory management method for performing a conversion from a first address to a second address in a computer that executes a program allocated to a virtual space divided into a plurality of areas, the method comprising: Stores access permission / prohibition information indicating from which area in the virtual space the program is accessible, and stores the area where the program accessing the first address is located. Detecting whether access to the first address from the detected area is permitted is determined based on the access permission / prohibition information, and if it is determined that the access is permitted, A memory management method comprising: outputting a conversion result from one address to a second address. 11. A means for storing a plurality of entries including a logical address and a physical address corresponding to the logical address, and for each of the plurality of programs which are permitted to access the logical address corresponding to each of the entries. /> means for memorize the access control information, when attempting to access the logical address to which the currently executing program, corresponding to the given virtual address Surua
    Means for detecting whether there is any of the plurality of stored access control information corresponding to the entry corresponding to the information on the program being executed, and A memory for outputting a notification to that effect when the notification is made, and a means for outputting the physical address stored corresponding to the certain logical address when the notification is output. Management device.
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US08/021,098 US5627987A (en) 1991-11-29 1993-02-23 Memory management and protection system for virtual memory in computer system
US08/753,944 US5890189A (en) 1991-11-29 1996-12-03 Memory management and protection system for virtual memory in computer system

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001005726A (en) 1999-04-20 2001-01-12 Nec Corp Memory address space expanding device and storage medium stored with program
US7290112B2 (en) * 2004-09-30 2007-10-30 International Business Machines Corporation System and method for virtualization of processor resources
JP2007122305A (en) * 2005-10-27 2007-05-17 Hitachi Ltd Virtual machine system
US9390031B2 (en) * 2005-12-30 2016-07-12 Intel Corporation Page coloring to associate memory pages with programs
US7844781B2 (en) * 2006-02-23 2010-11-30 International Business Machines Corporation Method, apparatus, and computer program product for accessing process local storage of another process
US7882318B2 (en) 2006-09-29 2011-02-01 Intel Corporation Tamper protection of software agents operating in a vitual technology environment methods and apparatuses
JP2009104555A (en) * 2007-10-25 2009-05-14 Intel Corp Method and apparatus for preventing alteration of software agent operating in vt environment
JP5225003B2 (en) * 2008-10-01 2013-07-03 キヤノン株式会社 Memory protection method, information processing device, memory protection program, and recording medium containing memory protection program
JP5845902B2 (en) * 2012-01-04 2016-01-20 トヨタ自動車株式会社 Information processing apparatus and memory access management method
US8938602B2 (en) * 2012-08-02 2015-01-20 Qualcomm Incorporated Multiple sets of attribute fields within a single page table entry
US9330026B2 (en) * 2013-03-05 2016-05-03 Qualcomm Incorporated Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (HWTW)
JP2018073301A (en) * 2016-11-02 2018-05-10 日立オートモティブシステムズ株式会社 Vehicle controller

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Lee R B.,Precision Architecture,IEEE COMPUTER,米国,IEEE,1989年 1月,Vol.22,No.1,p.78−91

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