JPS6148247A - Fault detection system of data transfer system - Google Patents

Abstract

PURPOSE:To attain retrieval of disturbance in a signal on a data bus by returning again a detected data to the tramission side when a parity error is detected in a signal on the data bus. CONSTITUTION:When a parity error detection signal 4 goes to logical 1, and a data detecting the parity error is fetched to a D13 register 13 by using AND among the signal 4, an output ST2 from a shift register 14 and an inverted signal of the clock signal 2 at an inverter 102. The D13 register 13 is connected to a processor control section 10 through an internal data bus 22 so as to attain reading. Thus, if a parity error takes place, the state of disturbance of data is analyzed by reading the D13 register 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for detecting a data bus abnormality in a data processing device. In particular, it relates to a bit disorder search method.

[Conventional technology]

Conventionally, as a data bus checking method, a method is known in which the detection of a parity error by a parity check of the data section is reported to a higher-level device, a lower-level device, or another processor. In recent years, systems have been used in which the highway (HW) automatically retries when a parity error occurs.

[Problem that the invention seeks to solve]

However, in this method, even if an abnormality is detected, it is not possible to search how the data bus is disturbed, that is, which bit is disturbed, so it is not possible to take sufficient measures.

The present invention improves this, and when an abnormality is detected,
The purpose of this invention is to provide a method that allows a host device to know the contents of the abnormality.

[Means for solving problems]

According to the present invention, data detected as a parity error is sent back to the sending side again, thereby making it possible to precisely search for signal disturbances on the data bus.

The present invention sends data including a barity bit from a first processor to a second processor, instructs the second processor to start sending the data, and also causes the second processor to take in data from the first processor. Perform a parity check on the imported data. If there is an abnormality, the second processor sends the received data back to the data bus, and the first processor takes in the data sent to the data bus.

[Effect]

If it is detected that there is a parity error in the data on the data bus, the data is sent back to the sending side on the same bus, and the receiving side can receive this data. To make it possible to search for disturbances correctly and to enable effective solutions to disturbances.

〔Example〕

Next, the present invention will be explained with reference to the embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. The driver 11 of the processor A, which is coupled to the D10 register 51 and driver 55 of the processor B via the data bus 1, is coupled to the output of the processor control unit 10. Furthermore, the output of the DI2 register 12 inputted by the data bus 1 is inputted to the processor control section 10 through the DI3I3 register 13. One output 1 of the processor control unit 10
0a (the other outgoing) month Ob is input to processor B which supplies clock signal 2. ) is input to the driver 11 via the inverter 101 and to the shift register 14 and this shift register 52 of processor B. The output of inverter 102 is coupled to DI3I3 register 13 and processor control unit 10 via AND gate 103, and also coupled to parity checker 54 and Nant gate 203 of processor B. The output of the DTO register 51 of processor B is sent to the DII register 53.
via the parity checker 54 and driver 5
Combine with 5. Coupled to parity checker 54 and driver 55. The output of parity checker 54 is coupled to driver 55 via Nant gate 203. The clock signal and STO signal via inverter 201 are coupled to register 53 via AND gate 202.

Processors A and B of the apparatus of the present invention are connected by a data bus 1, and data transfer between processors A and B is carried out by this data bus 1.

Clock signal 2 from processor A to processor B
and a BOP signal 3 instructing data transfer.

Further, processor B supplies processor A with a parity error detection signal 4 indicating that a parity error has been detected. FIG. 2 is a time chart of signals of various parts during normal operation of the apparatus according to the embodiment of the present invention. This will be explained in more detail with reference to FIGS. 1 and 2.

The data flow from processor A to processor B is as follows.

Data from the processor control section 10 controlling the processor A is connected to the driver 11 via a data line 21. The output signal of the driver 11, ie, the output to the data bus 1, is brought into an "enabled" state by the BOP signal 3 instructing data transfer. BOP signal 3 indicates that the data on the data bus is valid. Moreover, this BOP signal 3 is synchronized with the clock signal 2,
And the IT portion is output. BOP signal 3 makes driver 11 "active" (via inverter 101) as described above.

Clock signal 2 is sent to the DIO register 51 of processor B.
The data on the data bus 1 is always fetched.

STO, STI, and ST2 signals representing stages are generated from the BOP signal 3 via a shift register 52.

Data is taken into the DIO register 53 by performing the logical product (AND gate 202) of the aforementioned STo and the clock signal obtained by inverting the clock signal 2 by the inverter 201.

The data taken into the Dll register 53 is checked by a parity checker 54.

If the parity check result is normal, the parity error detection signal 4 is logic "0".

Next, a description will be given with reference to FIGS. 1 and 3.

In this case, the operation is performed when a parity error is detected.

In the cycle of the output STO from the shift register 52, Dl
When a parity error is detected in the data (including the parity bit) taken into the l register 53, the parity error detection signal 4 becomes logic "1".

When parity error signal 4 becomes “1”, NAND (NA
ND) The output of the driver 55 becomes "enabled" only during the ST1 cycle via the gate 203, and the contents of the Dll register 53 are sent onto the data bus 1. This data is the same data received by processor A.

The operation of the processor A when the parity error detection signal 4 becomes logic "1" will be described below.

Data is always loaded into the DI2 register 12 of processor A using clock signal 2 (rising edge of clock signal 2), similarly to the DIO register 51 of processor B. Furthermore, the shift register 14 on the processor A side operates similarly to the shift register 52 on the processor B side.

When the parity error detection signal 4 becomes logic "1", the logical product of this signal, the output ST2 from the shift register 4, and the signal obtained by inverting the clock signal 2 by the inverter 02 (AND gate 103) is used to register the DI3 register 3.
The data (including the parity bit) in which a parity error has been detected is captured. This DI3 register 3 is connected to the processor control unit 10 by an internal data bus 22 and can be read.

When a parity error occurs, the data disturbance situation can be analyzed by reading this D'13 register.

〔Effect of the invention〕

As explained above, in the present invention, when there is a parity error in a signal on a data bus, the data is retransferred onto the same data bus and a register is provided to capture this data. It has an effect that can be used effectively in analyzing disturbances.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a time chart of each part of the embodiment device during normal operation. FIG. 3 is a time chart when a parity error is detected. 1...Data bus (including parity bit), 2...
・Clock signal line, 3...Data transfer instruction (BOP)
Signal line, 4... Parity error detection signal line, 11...
・Driver, 12...DI2 register, 13...D
I3I3 register 1.22...internal data bus, 10
... Processor control unit, 14... Shift register,
101.1o2... Inverter, 103... NAND gate, 51... DIO register, 53
...Dll register, 52...Shift register, 5
4...Parity checker, 55...Driver, 2
01...Inverter, 202...And (AND)
Gate, 203...NAND gate.

Claims (1)

[Claims] (1) A first processor, a second processor, and a data bus connecting the first and second processors, and transmitting data including a parity bit to the data bus to the first processor. and the second processor includes means for detecting a parity error in data received from the data bus, and means for notifying the first processor of the parity error detected by the means. In the data transfer method, the second processor includes means for sending the received data as is to the data bus when the parity error detecting means detects an error; , comprising means for receiving data sent from the second processor to the data bus after being notified of the parity error, and means for analyzing the error from the data received by the means. Anomaly detection method for data transfer method.