JPS6148045A - Pseudo fault generating system - Google Patents

Abstract

PURPOSE:To simplify a debugging or a test relating to a fault processing of a program by providing a window which can control by a program whether an interruption is permitted or not, concerning the interruption due to the fault. CONSTITUTION:The program to be tested indicates a permission to the window 1b only in a partition to be tested. At a time of t0, the program enters a partition except the test object, and executes an instruction I1 for indicating an impermission to the window 1b. Thereafter, at the time of t2, an instruction I2 for activating a suspected fault is performed, and a bit in question of an interrupting cell 2a is set at a hold condition. At the time of t4, an instruction I3 for indicating a permission to the window 1b is executed and immediately, the interruption due to the pseudofault is generated and a test relating to the fault processing of the program to be tested is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a pseudo fault generation method in a computer system in which a fault is reported to a central processing unit by an interrupt.

[Prior art]

Conventionally, in computer systems where faults are reported to the central processing unit by interrupt K, debugging and testing of parts related to fault handling of programs involves artificially short-circuiting specific parts of logic circuits, or detecting faults as if a fault had occurred. A method has been implemented in which a failure is caused in a pseudo manner by executing a device diagnostic instruction that causes the central processing unit ff1lc to cause such an interrupt operation. In the former method, it is impossible to identify the part of the program where an interrupt occurs due to a failure because it involves human intervention, and in the latter method, the device diagnostic instruction is usually a privileged instruction, and there is an interrupt that prevents the interrupt. Unless the i-splash register is used, it is difficult to use it for debugging or testing parts related to fault handling WK during normal program execution, such as when an interrupt due to a pseudo fault occurs immediately upon execution of the instruction. Further, the interrupt mask register is used by the operating system as a system control means, and its contents cannot be changed for the purpose of normal program debugging or testing. Therefore, all of the conventional methods have extremely large restrictions on the timing of occurrence of interrupts due to pseudo-faults, and have the disadvantage that they cannot be used for comprehensive debugging or testing of parts related to fault handling in normal programs.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks, relax constraints on the timing of interrupt generation due to pseudo faults, and
It is an object of the present invention to provide a pseudo-fault generation method that can improve the ease of debugging and testing parts related to fault handling of programs.

[Structure of the invention]

The pseudo-failure generating method of the present invention is effective only for failure-related interrupts to the central processing unit, and includes a window indicating whether or not to permit interrupts caused by failures, and a window indicating whether to permit or disallow the interrupts caused by the failure. and a activating means for activating the pseudo-occurrence of a failure, and only when permission is indicated in the window after the activating means activates the occurrence of the failure. When a failure is reported by an interrupt K and the window indicates that permission is not permitted, reporting of the failure by interrupting the central processing unit is suspended until permission is indicated by the setting means.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a computer system to which the pseudo fault generation method of the present invention is applied. The computer system of this embodiment is composed of a central processing unit Xt, 1, a channel control device 3, a main storage device 4, and a system control device R2 connected to each of these devices 1-3. Further, the system control device 2 has an interrupt cell 2a that is accessible from the channel control device 3 and the central processing device 1 and holds an interrupt request to the central processing device 1.
The central processing unit l is provided with an interrupt mask register la that selects which of the interrupt requests pending in the interrupt cell 2a should be received by the central processing unit 1, and an interrupt mask register la that selects which of the interrupt requests to the central processing unit 1 should be received. A window 1b is provided that is effective only for failure-related items and indicates whether or not to permit interruptions due to failures. The interrupt cell 2a has a bit position corresponding to each interrupt, and an interrupt due to a failure also occupies a specific bit position of the interrupt cell 2a. The interrupt mask register 1a has bit positions having the same arrangement as the interrupt cell 2a, and similarly there are bit positions for interrupts due to failures. The activation means for activating the pseudo-occurrence of a failure turns on the relevant bit of interrupt controller A/2a (pending state).
It can be done.

There is also a setting means that allows the window 1b to indicate whether or not to permit interruptions due to failures. In this embodiment, these are all provided as instructions from the central processing unit 1.

FIG. 2 is a flowchart showing interrupt processing by the central processing unit 10. First, it is determined whether an interrupt is pending in the interrupt cell 2a (step 11).

If the interrupt is pending, check the interrupt Rζ register la and window 1b in steps 12 and 13), and if the interrupt is a fault and the interrupt due to this fault is to be permitted, clear the corresponding bit in the interrupt cell 2a ( Step 14) Performs interrupt processing (Step 15), and in other cases, executes the next instruction without performing interrupt processing (
Step 16).

FIG. 3 is a time chart showing the flow of testing a portion of the program related to fault handling according to this embodiment. The program under test 2 has window 1 only for the test section.
b indicates permission. Time t.

At the point in time, the program enters the non-test target section and executes instruction II to indicate disapproval in window 1b.

Thereafter, at time t2, instruction (2) for activating a pseudo failure is executed, and the relevant bit of the interrupt cell 2a is set to a pending state. At time 40, the instruction 3 for indicating permission to the window 1b is executed, and immediately an interruption due to a pseudo failure occurs, and the part of the test program related to the failure handling is tested. In this embodiment, the period in which the interrupt mask register 1a is off (interrupts are prohibited) is from time t1 to time t13, so it has no effect on the occurrence of an interrupt due to a pseudo failure at time t4. The off state continues from time t3 to beyond time 4 (and during that time, interrupts due to pseudo failures are also suspended.

Note that in this embodiment, an interrupt due to a failure is sent to the interrupt cell 2a.
Although we have discussed the case where the interrupt is handled as an external interrupt processed by the interrupt mask register 1a, the same situation applies even when the interrupt due to a failure is handled as an internal interrupt.

〔Effect of the invention〕

The present invention provides a window that allows the program to control whether or not to permit interrupts caused by faults, so constraints on the timing of interrupts caused by pseudo faults are relaxed, and the parts of the program related to fault handling are relaxed. It helps when debugging and testing becomes easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a 31L computer system to which the pseudo-failure generating method of the present invention is applied, and FIG. 2 shows interrupt processing of the central processing unit 1 of the computer system shown in FIG. Flow Chart FIG. 3 is a time chart showing the flow of testing of the portion related to fault handling of the program in the embodiment of FIG. i1. 1...Central processing unit 2...System control device 3...Channel device 4...Main storage device Ia...Interrupt mask register 1b...Window 2a...Interrupt cell. Patent applicant: NEC Corporation, -m-

Claims (1)

[Claims] In a computer system in which a fault is reported to a central processing unit by an interrupt, a window is effective only for fault-related interrupts to the central processing unit and indicates whether or not to permit interrupts due to faults; comprising a setting means for causing the window to indicate the permission or disapproval, and a starting means for starting a pseudo-occurrence of a failure,
After the occurrence of a fault is activated by the activation means, the fault is reported by an interrupt to the central processing unit only when permission is indicated in the window, and when denial is indicated in the window; A pseudo-failure generation method, characterized in that reporting of a failure due to an interrupt to a central processing unit is suspended until permission is indicated by the setting means.