JPS6139136A - Inspection system of information processor - Google Patents

Inspection system of information processor

Info

Publication number
JPS6139136A
JPS6139136A JP16047884A JP16047884A JPS6139136A JP S6139136 A JPS6139136 A JP S6139136A JP 16047884 A JP16047884 A JP 16047884A JP 16047884 A JP16047884 A JP 16047884A JP S6139136 A JPS6139136 A JP S6139136A
Authority
JP
Japan
Prior art keywords
test
test execution
operating system
task
tested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16047884A
Other languages
Japanese (ja)
Inventor
Mamoru Ishibashi
石橋 守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16047884A priority Critical patent/JPS6139136A/en
Publication of JPS6139136A publication Critical patent/JPS6139136A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/004Error avoidance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To prevent a fault of the information processor from causing a change of data by executing a program which inspects the processor at constant intervals of time under the control of an operating system and stopping a system immediately if an error is detected. CONSTITUTION:A main storage device 30 is stored with the OS31, a test control task 32, and test execution tasks 33 and 34 for CPUs 41 and 42. The test execution tasks 34 and 34 are started successively and an end flag is turned off. The number of a CPU to be tested and information on an instruction to be tested are transferred to the message areas of the test execution tasks. A decimal addition instruction to be tested is executed and the result is compared with an expected value; when they coincide with each other, the next test is taken and when coincidence is obtained after the final test, the end flag is turned on. A timer is set and inspection is performed again a specific time later. When the coincidence is not obtained, an error message is outputted and the OS31 performs system stop processing to prevent data from changing.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、主記憶装置に接続された処理装置な試験する
、情報処理装置の検査方式、特にオペレーティングシス
テムのもとで試験するヘルスチェック方式(=関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an information processing device testing method for testing a processing device connected to a main storage device, particularly a health check method for testing under an operating system. .

〔従来技術〕[Prior art]

従来、この種の情報処理装置の故障は、該装置内のチェ
ック回路による検出と、チェック回路(二よってチェッ
ク不可能な故障が発生するとオペレーティングシステム
などのソフトウェアの論理矛盾という形での検出に委ね
られていた。このため、ソフトウェアの論理矛盾という
形の検出に期待している故障は、ソフトウェアがハード
ウェアの故障を検出する目的で作成されていないために
、ソフ、トウエアでも検出されない場合があった。この
場合はデータ化けとなり、故障の検出が故障発生後長時
間経過して行なわれていたので、データ復旧が困難にな
るという致命的な問題があった。
Conventionally, failures in this type of information processing equipment have been detected by check circuits within the equipment, and detection by check circuits (2) where uncheckable failures occur in the form of logical contradictions in software such as the operating system. Therefore, failures that are expected to be detected in the form of logical contradictions in software may not be detected by software or software because the software was not created for the purpose of detecting hardware failures. In this case, the data would be garbled, and since the failure was detected a long time after the failure occurred, there was a fatal problem in that it would be difficult to recover the data.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、情報処理装置の故障がソフトウェアに
よって検出されず、データ化けとなる現象の発生を防止
した、情報処理装置の検査方式を提供すること(二ある
SUMMARY OF THE INVENTION It is an object of the present invention to provide an inspection method for an information processing device that prevents failures of the information processing device from being detected by software and garbled data.

毎に処理装置を検査するプログラムを実行し、エラーが
検出されたならば直ちにシステムを停止させるようにし
たものである。
A program is executed to check the processing device every time the system is installed, and if an error is detected, the system is immediately stopped.

すなわち、本発明の情報処理装置の検査方式は主記憶装
置に接続される処理装置を試験するための、かつ該処理
装置数だけの試験実行タスクと1個以上の該試験実行タ
スクを制御する試験制御タスクと該試験制御タスクを制
御するオペレーティングシステムとを該主記憶装置(二
格納し、オペレーティングシステムは常時該試験制御タ
スクを実行し、該試験制御タスクは一定時間毎)二1個
以上の該試験実行タスクの全部を起動し、試験実行タス
クがエラー検出した時(二はオペレーティングシステム
へ直ち(二実行停止要求を行ない、オペレーティングシ
ステムはこれにより直ちにオペレーティングシステム自
身の実行を停止することを特徴とする。
That is, the information processing device testing method of the present invention is for testing processing devices connected to a main storage device, and for controlling test execution tasks as many as the number of processing devices and one or more of the test execution tasks. A control task and an operating system that controls the test control task are stored in the main memory (2, the operating system always executes the test control task, and the test control task is executed at regular intervals). When all of the test execution tasks are started and the test execution task detects an error (2), it immediately issues a (2) execution stop request to the operating system, and the operating system immediately stops its own execution. shall be.

〔実施例〕〔Example〕

以下、図面を参照しながら本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図は本発明の検査方式を適用した情報処理装置の一
実施例のブロック図である。本実施例の情報処理装置は
、上記憶装置3oと、これに接続された処理装置(以下
、CPUという)41.42からなり、主記憶装置60
には、オペレーティングシステム(以下、O8という)
61、試験制御タスク32、CPU41の検査プログラ
ムである試験実行タスク66、CPU42の検査プログ
ラムである試験実行タスク64が格納されている。
FIG. 1 is a block diagram of an embodiment of an information processing apparatus to which the inspection method of the present invention is applied. The information processing device of this embodiment includes an upper storage device 3o and processing devices (hereinafter referred to as CPUs) 41 and 42 connected thereto, and a main storage device 60.
The operating system (hereinafter referred to as O8)
61, a test control task 32, a test execution task 66 which is a test program for the CPU 41, and a test execution task 64 which is a test program for the CPU 42 are stored.

第2図は0861が試験制御タスク62を起動した後の
試験制御タスク62の動作を示す概略フローチャート、
第3図は試験実行タスク33.34内の10進加算命令
試験の概略フローチャートである。以下、第2図、!s
6図を参照しながら、本実施例の情報処理装置の動作を
説明する。
FIG. 2 is a schematic flowchart showing the operation of the test control task 62 after 0861 starts the test control task 62;
FIG. 3 is a schematic flowchart of the decimal add instruction test within test execution task 33.34. Below is Figure 2! s
The operation of the information processing apparatus of this embodiment will be explained with reference to FIG.

先ず、ステップ11において試験実行タスク63を起動
し、試験制御タスク62内の試験実行タスク66用の終
了フラグ(図示せず)をオフにする。
First, in step 11, the test execution task 63 is started, and the end flag (not shown) for the test execution task 66 in the test control task 62 is turned off.

ステップ12で、試験実行タスク64を起動し、試験制
御タスク62内の試験実行タスク64用の終了フラグ(
図示せず)をオフにする。試験実行タスク66と64の
論理は同一であり、その一部を第6図に示す。先ず、ス
テップ21で当該試験実行タスクのメツセージエリアに
試験対象のCPU番号、試験対象命令の情報を移送する
。ステップ22で、試験対象である10進加算命令を実
行する。ステップ23で、この10進加算命令の実行結
果を期待値と比較し、ステップ24で、一致しているか
どうか判断する。一致しておれば、次の試験を実行する
(ステップ28)。もし、最後の試験でも結果が一致し
ておれば、前記終了フラグをオンにして当該試験実行タ
スクの実行を終了する。このようにして試験実行タスク
66.64が正常(二終了すれば、試験実行タスク36
.34用終了フラグはとも(ニオン(二なり、この後ス
テップ13からステップ14に移り、1時間のタイマが
セットされる。1時間経過後、ステップ15からステッ
プ11へ処理が移行し、再度、検査が実行されること(
二なる。ステップ24の判断において一致しなかった場
合は、プログラムの制御はステップ25へと移行し、ス
テップ22での実行結果とステップ23で用いた期待値
をメツセージ出カニリアへ移送する。この後、ステップ
26(二て、エラーメツセージを編集し、メツセージ出
力装置(図示せず)へ出力する。ステップ27ヘプログ
ラムの制御が移ると、0861へ停止要求を出し、08
61は直ち(=システム停止処理(図示せず)を行ない
、データ化は発生後も処理が進むのを抑止することがで
きる。
In step 12, the test execution task 64 is started and the end flag for the test execution task 64 in the test control task 62 (
(not shown). The logic of test execution tasks 66 and 64 is identical, a portion of which is shown in FIG. First, in step 21, information about the CPU number to be tested and the instruction to be tested is transferred to the message area of the test execution task. In step 22, the decimal addition instruction to be tested is executed. In step 23, the execution result of this decimal addition instruction is compared with the expected value, and in step 24 it is determined whether they match. If they match, the next test is performed (step 28). If the results match in the last test, the end flag is turned on to end the execution of the test execution task. In this way, if the test execution tasks 66 and 64 are completed successfully, the test execution task 36
.. The end flag for 34 is set to 2, after which the process moves from step 13 to step 14, and a 1 hour timer is set. After 1 hour, the process moves from step 15 to step 11, and the inspection is performed again. is executed (
Two. If they do not match in the determination at step 24, control of the program moves to step 25, where the execution result at step 22 and the expected value used at step 23 are transferred to the message sending canister. After that, in step 26, the error message is edited and output to a message output device (not shown). When control of the program is transferred to step 27, a stop request is sent to 0861, and a stop request is sent to 08
61 immediately performs (=system stop processing (not shown)), and it is possible to prevent the processing from proceeding even after data conversion occurs.

以上の実施例では検査対象の処理装置は2台であったが
、1台以上ならば何台の処理装置へも本発明は適用可能
である。
Although the number of processing devices to be inspected was two in the above embodiment, the present invention can be applied to any number of processing devices as long as it is one or more.

〔発、明の効果〕〔Effect of the invention〕

本発明は以上説明したよう(二、処理装置の正常性を検
査するプログラムを処理装置の数だけ、一定時間毎(二
実行することにより、何れの処理装置の誤動作:二より
データ化けになるこ゛とを防止することができる。
As explained above, the present invention prevents the malfunction of any processing device and the risk of data corruption by executing a program for checking the normality of the processing device for the number of processing devices at a fixed time interval (2). can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の検査方式を適用した情報処理装置の一
実施例を示すブロック図、第2図は本発明の検査プログ
ラムの制御の中心となる試験制御タスク62の動作を示
す概略フローチャート、第6図は検査を実行するプログ
ラムのうちで、10進加算命令試験の概略フローチャー
トである。 60・・・主記憶装置、 31・・・オペレーティングシステム、62・・・試験
制御タスク、 33.34・・・試験実行タスク、 41.42・・・中央処理装置。 第1図 第2図 一 第3図
FIG. 1 is a block diagram showing an embodiment of an information processing apparatus to which the inspection method of the present invention is applied, and FIG. 2 is a schematic flowchart showing the operation of the test control task 62 which is the center of control of the inspection program of the present invention. FIG. 6 is a schematic flowchart of the decimal addition instruction test among the programs that execute the test. 60... Main storage device, 31... Operating system, 62... Test control task, 33.34... Test execution task, 41.42... Central processing unit. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 主記憶装置に接続される処理装置を試験するための、か
つ該処理装置数だけの試験実行タスクと1個以上の該試
験実行タスクを制御する試験制御タスクと該試験制御タ
スクを制御するオペレーティングシステムとを該主記憶
装置に格納し、オペレーティングシステムは常時該試験
制御タスクを実行し、該試験制御タスクは一定時間毎に
1個以上の該試験実行タスクの全部を起動し、試験実行
タスクがエラー検出した時にはオペレーティングシステ
ムへ直ちに実行停止要求を斤ない、オペレーティングシ
ステムはこれにより直ちにオペレーティングシステム自
身の実行を停止することを特徴とする情報処理装置の検
査方式。
A test execution task for testing processing devices connected to the main storage device and as many as the number of processing devices, a test control task for controlling one or more of the test execution tasks, and an operating system for controlling the test control task. are stored in the main memory, the operating system constantly executes the test control task, the test control task starts all of the one or more test execution tasks at regular intervals, and the test execution task An inspection method for an information processing device, characterized in that when detection is detected, an execution stop request is not immediately made to the operating system, and the operating system immediately stops its own execution.
JP16047884A 1984-07-31 1984-07-31 Inspection system of information processor Pending JPS6139136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16047884A JPS6139136A (en) 1984-07-31 1984-07-31 Inspection system of information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16047884A JPS6139136A (en) 1984-07-31 1984-07-31 Inspection system of information processor

Publications (1)

Publication Number Publication Date
JPS6139136A true JPS6139136A (en) 1986-02-25

Family

ID=15715819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16047884A Pending JPS6139136A (en) 1984-07-31 1984-07-31 Inspection system of information processor

Country Status (1)

Country Link
JP (1) JPS6139136A (en)

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