JPS6147450B2 - - Google Patents
Info
- Publication number
- JPS6147450B2 JPS6147450B2 JP1868480A JP1868480A JPS6147450B2 JP S6147450 B2 JPS6147450 B2 JP S6147450B2 JP 1868480 A JP1868480 A JP 1868480A JP 1868480 A JP1868480 A JP 1868480A JP S6147450 B2 JPS6147450 B2 JP S6147450B2
- Authority
- JP
- Japan
- Prior art keywords
- unbalanced
- wire line
- differential amplifier
- resistors
- impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/54—Circuits using the same frequency for two directions of communication
- H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/03—Hybrid circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
本発明は、不平衡2線式回線と不平衡4線式回
線とを接続する為の電子式ハイブリツト回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic hybrid circuit for connecting an unbalanced two-wire line and an unbalanced four-wire line.
2線式回線と4線式回線とを接続する為のハイ
ブリツト回路は、従来は、ハイブリツドコイルに
より構成されるのが一般的であつた。このハイブ
リツドコイルは、磁心にコイルを巻回して構成す
るものであるから、小型化が困難であると共に、
巻線工程を含むので、製造コストの低減が容易で
ない欠点があつた。 Conventionally, a hybrid circuit for connecting a two-wire line and a four-wire line has generally been constructed of a hybrid coil. Since this hybrid coil is constructed by winding a coil around a magnetic core, it is difficult to miniaturize it, and
Since it involves a winding process, it has the disadvantage that manufacturing costs cannot be easily reduced.
このような欠点を改善する為に、電子式ハイブ
リツド回路が提案されているが、高性能の差動増
幅器を多数必要とし、又バランスネツトワークの
インピーダンスが小さく、それにより、バランス
ネツトワークを構成するコンデンサの容量値が大
きくなるので、高価であると共に、実装上の問題
があつた。又このような電子式ハイブリツド回路
は、平衡2線式回線と不平衡4線式回線とを接続
する為のものであるから、不平衡2線式回線と不
平衡4線式回線とを接続するには不利であつた。 Electronic hybrid circuits have been proposed to improve these drawbacks, but they require a large number of high-performance differential amplifiers, and the impedance of the balance network is small, making it difficult to configure the balance network. Since the capacitance value of the capacitor becomes large, it is expensive and there are problems in mounting. Also, since such electronic hybrid circuits are for connecting balanced 2-wire lines and unbalanced 4-wire lines, it is difficult to connect unbalanced 2-wire lines and unbalanced 4-wire lines. was at a disadvantage.
本発明は、不平衡2線式回線と不平衡4線式回
線とを接続する為の電子式ハイブリツド回路に関
するもので、小型且つ経済的な構成とすることを
目的とするものである。 The present invention relates to an electronic hybrid circuit for connecting an unbalanced two-wire line and an unbalanced four-wire line, and aims to have a compact and economical configuration.
以下図面を参照して本発明の実施例について説
明する。 Embodiments of the present invention will be described below with reference to the drawings.
図は本発明の実施例のブロツク図であり、1及
び2は不平衡4線式回線の入力端子及び出力端
子、3は不平衡2線式回線の入出力端子、4は第
1の差動増幅器、5はバランスネツトワーク、6
は第2の差動増幅器、R1〜R4、Ra,Rbは抵
抗、Zpは擬似負荷、Zは不平衡2線式回線のイ
ンピーダンスであつて、基本構成を示す。又右側
の5′は、抵抗値の変換を行つたバランスネツト
ワークであり、Ra′,Rb′はa,b間に直列に接
続した第1及び第2の抵抗、Zp′はc点と接地と
の間に接続した擬似負荷を示す。 The figure is a block diagram of an embodiment of the present invention, where 1 and 2 are input and output terminals of an unbalanced 4-wire line, 3 is an input/output terminal of an unbalanced 2-wire line, and 4 is a first differential line. Amplifier, 5, balance network, 6
is the second differential amplifier, R1 to R4, Ra, and Rb are resistors, Zp is the pseudo load, and Z is the impedance of the unbalanced two-wire line, showing the basic configuration. Also, 5' on the right side is a balance network that converts the resistance value, Ra' and Rb' are the first and second resistors connected in series between a and b, and Zp' is the connection between point c and ground. This shows the pseudo load connected between the
抵抗R4は、不平衡2線式回線との整合をとる
為の整合用抵抗であり、公称インピーダンスR0
(例えば、600Ω)に選定されている。この場合、
差動増幅器4の出力インピーダンスが小さいの
で、不平衡2線式回線は、公称インピーダンス
R0の抵抗R4により終端されることになる。又
抵抗R1〜R3は同一の抵抗値Rに設定されてい
る。又バランスネツトワーク5は、a,b間に直
列接続された第1及び第2の抵抗Ra,Rbと、そ
の接続点cと接地との間に接続された擬似負荷
Zpとにより構成されている。 Resistor R4 is a matching resistor for matching with the unbalanced 2-wire line, and has a nominal impedance R 0
(for example, 600Ω). in this case,
Since the output impedance of the differential amplifier 4 is small, the unbalanced two-wire line has a nominal impedance
It will be terminated by a resistor R4 of R0 . Further, the resistors R1 to R3 are set to the same resistance value R. The balance network 5 also includes first and second resistors Ra and Rb connected in series between a and b, and a pseudo load connected between their connection point c and ground.
It is composed of Zp.
不平衡2線式回線の入出力端子3に入力された
信号は、第2の差動増幅器6の反転入力端子
(−)に抵抗R3を介して入力され、且つ非反転
入力端子(+)に抵抗R4,Rb,Raを介して入
力される。その場合、第1の差動増幅器4の出力
インピーダンスは小さいので、入出力端子3は抵
抗R4によつて終端されていることになり、入出
力端子3から差動増幅器6の非反転入力端子
(+)に加えられる信号レベルは、反転入力端子
(−)に加えられる信号レベルに比較して無視で
きる程度に小さいものとなる。従つて、不平衡2
線式回線の入出力端子3に入力された信号は、差
動増幅器6から不平衡4線式回線の出力端子2に
出力される。 The signal input to the input/output terminal 3 of the unbalanced two-wire line is input to the inverting input terminal (-) of the second differential amplifier 6 via the resistor R3, and is input to the non-inverting input terminal (+) of the second differential amplifier 6. It is input via resistors R4, Rb, and Ra. In that case, since the output impedance of the first differential amplifier 4 is small, the input/output terminal 3 is terminated by the resistor R4, and the input/output terminal 3 is connected to the non-inverting input terminal of the differential amplifier 6 ( The signal level applied to the inverting input terminal (-) is negligibly small compared to the signal level applied to the inverting input terminal (-). Therefore, imbalance 2
A signal input to the input/output terminal 3 of the wire line is outputted from the differential amplifier 6 to the output terminal 2 of the unbalanced four-wire line.
又不平衡4線式回線の入力端子1に入力された
信号は、第1の差動増幅器4の非反転入力端子
(+)に加えられ、非反転出力信号が抵抗R4を
介して不平衡2線回線の入出力端子3に出力さ
れ、又その非反転出力信号は、抵抗R4,R3を
介して差動増幅器6の反転入力端子(−)に加え
られると共に、抵抗Rb,Raを介して差動増幅器
6の非反転入力端子(+)に加えられる。この差
動増幅器6の非反転入力端子(+)と反転入力端
子(−)とに加えられる信号レベル及び位相が同
じ場合に、差動増幅器6の出力信号は零となるの
で、不平衡4線式回線の入力端子1に入力された
信号が出力端子2に出力されることを防止するこ
とができる。即ち、入力端子1から出力端子2へ
の回り込みを防止することができる。 The signal input to the input terminal 1 of the unbalanced 4-wire line is applied to the non-inverting input terminal (+) of the first differential amplifier 4, and the non-inverting output signal is passed through the resistor R4 to the unbalanced 2-wire line. The non-inverted output signal is output to the input/output terminal 3 of the line line, and is applied to the inverting input terminal (-) of the differential amplifier 6 via resistors R4, R3, and is applied to the differential input terminal (-) via resistors Rb, Ra. It is applied to the non-inverting input terminal (+) of the dynamic amplifier 6. When the signal level and phase applied to the non-inverting input terminal (+) and the inverting input terminal (-) of the differential amplifier 6 are the same, the output signal of the differential amplifier 6 becomes zero, so the unbalanced 4-wire It is possible to prevent the signal input to the input terminal 1 of the system line from being output to the output terminal 2. That is, it is possible to prevent leakage from the input terminal 1 to the output terminal 2.
このような回り込み防止の条件は、不平衡2線
式回線の入出力端子3に於ける負荷条件を、バラ
ンスネツトワーク5のc点で実現させれば良く、
それにより、差動増幅器6の反転入力端子(−)
と非反転入力端子(+)とに入力される差動増幅
器4の出力信号のレベル及び位相を一致させるこ
とができる。即ち、Ra+Rb=R3+R4の関係であ
ると共に、Ra=R3、Rb=R4、Zp=Zの関係と
することにより、回り込み防止の条件を満足する
ことができる。このような条件を、差動増幅器6
による回り込み防止の基本条件とするものであ
る。 Such a bypass prevention condition can be achieved by realizing the load condition at the input/output terminal 3 of the unbalanced two-wire line at point c of the balanced network 5.
Thereby, the inverting input terminal (-) of the differential amplifier 6
It is possible to match the level and phase of the output signal of the differential amplifier 4 inputted to the non-inverting input terminal (+). That is, by setting the relationship Ra+Rb=R3+R4, Ra=R3, Rb=R4, and Zp=Z, the conditions for preventing wraparound can be satisfied. Under these conditions, the differential amplifier 6
This is the basic condition for preventing wraparound.
前述の基本条件の一例について示すと、不平衡
2線式回線の公称インピーダンスR0は、一般に
は600Ωであるから、整合用抵抗R4は600Ωに選
定される。又抵抗R1,R2,R3は、同一抵抗
値の30KΩに選定され、バランスネツトワーク5
の抵抗Ra,Rbは、Ra=R3、Rb=R4の関係か
ら、30KΩ及び600Ωに選定され、又擬似負荷Zp
は不平衡2線式回線のインピーダンスZと等しい
インピーダンスに選定される。 As an example of the above-mentioned basic condition, the nominal impedance R 0 of an unbalanced two-wire line is generally 600Ω, so the matching resistor R4 is selected to be 600Ω. In addition, resistors R1, R2, and R3 are selected to have the same resistance value of 30KΩ, and the balance network 5
The resistances Ra and Rb are selected to be 30KΩ and 600Ω from the relationship Ra=R3 and Rb=R4, and the pseudo load Zp
is chosen to have an impedance equal to the impedance Z of the unbalanced two-wire line.
本発明は、前述の基本条件のRa+Rb=R3+R4
の関係を維持しながら抵抗値を変換して、擬似負
荷のインピーダンスを不平衡2線式回線のインピ
ーダンスに比較して大きくできるようにしたもの
である。即ち、右側のバランスネツトワーク5′
に示すようにa,b間に直列に接続した第1及び
第2の抵抗Ra′,Rb′と、その接続点cと接地と
の間に接続した擬似負荷Zp′とからなる構成に於
いて、Ra′+Rb′=R3+R4の関係を維持し、且
つ、Ra′=Rb′の関係に選定して、差動増幅器6
の反転入力端子(−)と非反転入力端子(+)と
に入力される差動増幅器4の出力信号レベルが等
しくなるように、即ち、回り込み防止ができるよ
うに、Zp′>Zの関係に選定するものである。 The present invention is based on the above-mentioned basic condition Ra+Rb=R3+R4
By converting the resistance value while maintaining the relationship, the impedance of the dummy load can be increased compared to the impedance of the unbalanced two-wire line. That is, the right balance network 5'
As shown in the figure, in the configuration consisting of first and second resistors Ra' and Rb' connected in series between a and b, and a pseudo load Zp' connected between their connection point c and ground. , Ra′+Rb′=R3+R4, and selecting the relationship Ra′=Rb′, the differential amplifier 6
In order to make the output signal level of the differential amplifier 4 input to the inverting input terminal (-) and the non-inverting input terminal (+) of the differential amplifier 4 equal, that is, to prevent loop-circuiting, the relationship Zp'>Z is established. It is to be selected.
前述のように、抵抗R3を30KΩ、抵抗R4を
600Ωとした場合、基本条件のR3+R4=Ra′+
Rb′=30.6〔KΩ〕の関係を維持して、Ra′=
Rb′=15.3KΩに選定するものである。このよう
に抵抗Ra′,Rb′を選定することにより、擬似負
荷Zp′を不平衡2線式回線のインピーダンスZの
約19倍のインピーダンスとすることができた。従
つて、擬似負荷Zp′を構成するコンデンサの容量
を小さくすることが可能となる。 As mentioned above, resistor R3 is 30KΩ and resistor R4 is
When 600Ω, basic condition R3+R4=Ra′+
Maintaining the relationship Rb′=30.6 [KΩ], Ra′=
Rb' is selected to be 15.3KΩ. By selecting the resistors Ra' and Rb' in this way, the impedance of the pseudo load Zp' can be made approximately 19 times the impedance Z of the unbalanced two-wire line. Therefore, it is possible to reduce the capacitance of the capacitor constituting the pseudo load Zp'.
以上説明したように、本発明に、不平衡4線式
回線と不平衡2線式回線とを接続する為の電子式
ハイブリツド回路に於いて、バランスネツトワー
ク5′を構成する第1及び第2の抵抗Ra′及び
Rb′を、Ra′+Rb′=R3+R4の関係を維持し、且
つRa′=Rb′として、第2の差動増幅器6による
回り込み防止ができるように、擬似負荷Zp′を、
不平衡2線式回線のインピーダンスZより大きく
したものであり、能動回路としては、第1及び第
2の差動増幅器4,6のみとなるので、廉価の構
成となる。又擬似負荷Zp′のインピーダンスを大
きくできるから、その擬似負荷Zp′を構成するコ
ンデンサの容量を小さくすることができ、小型化
が可能となる。又差動増幅器4,6や抵抗等を含
めて集積回路化することが容易であるから、不平
衡2線式回線と不平衡4線式回線とを接続する為
の電子式ハイブリツド回路を、小型且つ経済的な
構成とすることができる利点がある。 As explained above, in the present invention, in an electronic hybrid circuit for connecting an unbalanced 4-wire line and an unbalanced 2-wire line, the first and second The resistance Ra′ and
In order to maintain the relationship of Ra'+Rb'=R3+R4 and set Ra'=Rb', the pseudo load Zp' is
The impedance Z is larger than that of an unbalanced two-wire line, and since the only active circuits are the first and second differential amplifiers 4 and 6, the configuration is inexpensive. Furthermore, since the impedance of the pseudo load Zp' can be increased, the capacitance of the capacitor constituting the pseudo load Zp' can be reduced, allowing miniaturization. Also, since it is easy to integrate the differential amplifiers 4, 6, resistors, etc. into an integrated circuit, it is possible to create an electronic hybrid circuit for connecting an unbalanced 2-wire line and an unbalanced 4-wire line in a small size. In addition, there is an advantage that it can be an economical structure.
図は本発明の実施例のブロツク図である。
1,2は不平衡4線式回線の入力端子及び出力
端子、3は不平衡2線式回線の入出力端子、4は
第1の差動増幅器、5,5′はバランスネツトワ
ーク、6は第2の差動増幅器、R1〜R3は抵
抗、R4は整合用抵抗、Ra,Ra′は第1の抵抗、
Rb,Rb′は第2の抵抗、Zp,Zp′は擬似負荷、Z
は不平衡2線式回線のインピーダンスである。
The figure is a block diagram of an embodiment of the invention. 1 and 2 are the input and output terminals of the unbalanced 4-wire line, 3 is the input and output terminal of the unbalanced 2-wire line, 4 is the first differential amplifier, 5 and 5' are the balanced network, and 6 is the input/output terminal of the unbalanced 2-wire line. A second differential amplifier, R1 to R3 are resistors, R4 is a matching resistor, Ra and Ra' are first resistors,
Rb and Rb' are the second resistances, Zp and Zp' are the pseudo loads, and Z
is the impedance of the unbalanced two-wire line.
Claims (1)
衡2線式回線に整合用抵抗R4を介して信号を送
出する第1の差動増幅器4と、前記不平衡2線式
回線の入力信号を抵抗R3を介して一方の入力と
し、前記第1の差動増幅器4の出力をバランスネ
ツトワーク5を介して他方の入力として、不平衡
4線式回線に信号を送出する第2の差動増幅器6
とを備え、 前記バランスネツトワーク5は、直列接続の第
1及び第2の抵抗Ra,Rbと、該第1及び第2の
抵抗Ra,Rbの接続点と接地との間に接続した擬
似負荷Zpとを有し、 前記2線式回線のインピーダンスをZとして、 Ra+Rb=R3+R4、 Ra=R3、 Rb=R4、 Zp=Z の関係を前記第2の差動増幅器6による回り込み
防止の基本条件とした電子式ハイブリツド回路に
於いて、 前記バランスネツトワーク5の第1及び第2の
抵抗Ra,RbをRa′,Rb′、擬似負荷ZpをZp′とし
て、 Ra′+Rb′=R3+R4 の関係を維持し、且つ Ra′=Rb′ Zp′>Z の関係として、前記第2の差動増幅器6による回
り込み防止を行うように、前記バランスネツトワ
ーク5の第1及び第2の抵抗と擬似負荷のインピ
ーダンスとを選定したことを特徴とする電子式ハ
イブリツド回路。[Claims] 1. A first differential amplifier 4 that sends a signal to the unbalanced 2-wire line via a matching resistor R4 in response to an input signal of the unbalanced 4-wire line; The input signal of the two-wire line is used as one input via the resistor R3, and the output of the first differential amplifier 4 is used as the other input via the balanced network 5, so that the signal is sent to the unbalanced four-wire line. Second differential amplifier 6
The balance network 5 includes first and second resistors Ra and Rb connected in series, and a pseudo load connected between the connection point of the first and second resistors Ra and Rb and ground. Zp, and the impedance of the two-wire line is Z, and the relationship Ra+Rb=R3+R4, Ra=R3, Rb=R4, Zp=Z is the basic condition for preventing wraparound by the second differential amplifier 6. In the electronic hybrid circuit, where the first and second resistors Ra and Rb of the balance network 5 are Ra' and Rb', and the pseudo load Zp is Zp', the relationship Ra' + Rb' = R3 + R4 is maintained. In addition, the impedance of the first and second resistances of the balance network 5 and the pseudo load is set such that the second differential amplifier 6 prevents the loop-circuit from occurring as the relationship Ra'=Rb'Zp'>Z. An electronic hybrid circuit characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1868480A JPS56115041A (en) | 1980-02-18 | 1980-02-18 | Electronic hybrid circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1868480A JPS56115041A (en) | 1980-02-18 | 1980-02-18 | Electronic hybrid circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56115041A JPS56115041A (en) | 1981-09-10 |
JPS6147450B2 true JPS6147450B2 (en) | 1986-10-20 |
Family
ID=11978429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1868480A Granted JPS56115041A (en) | 1980-02-18 | 1980-02-18 | Electronic hybrid circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56115041A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6361559U (en) * | 1986-10-14 | 1988-04-23 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5869132A (en) * | 1981-10-20 | 1983-04-25 | Nippon Telegr & Teleph Corp <Ntt> | Electronic hybrid circuit |
JPS61216531A (en) * | 1985-02-21 | 1986-09-26 | Fujitsu Ltd | Two-wire and four-wire converting circuit |
-
1980
- 1980-02-18 JP JP1868480A patent/JPS56115041A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6361559U (en) * | 1986-10-14 | 1988-04-23 |
Also Published As
Publication number | Publication date |
---|---|
JPS56115041A (en) | 1981-09-10 |
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