JPS5869132A - Electronic hybrid circuit - Google Patents

Abstract

PURPOSE:To reduce the size of a passive element, by using a passive circuit providing a two-wire termination impedance in a feedback loop and keeping the value of capacitance or inductance of the passive circuit and the dielectric strength low, when the capacitance of inductance is included in the passive circuit. CONSTITUTION:A signal inutted to two-wire input lines 20, 21 is detected at a differential amplifier 12 and a differential signal is outputted to a terminal 22. The output is outputted to a four-wire output terminal 23 via a differential amplifier 14. Further, a signal applied to a four-wire input terminal 24 is inputted to a differential amplifier 13 and a current subjected to voltage-current conversion of an impedance Z1 of a passive circuit 17 connected to an emitter 26 is outputted. This output is amplified with respect to current 16 and a complementary output current is outputted to the two-wire input terminals 20 and 21.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic hybrid circuit suitable for converting a bimodal input impedance into a complex impedance.

Conventionally, in an electronic hybrid circuit, a configuration as shown in FIG. 1 is used when shown as an AC equivalent circuit, and an amplifier 1. Output resistance 2. Each has an equal resistance value R1/2. Differential amplifiers 3, 4. It consists of passive circuits 5 and 6 and a voltage amplifier 7. To explain the circuit operation, the 4# input power value VR applied to the terminal 8 is input to the amplifier 1, and its complementary output is sent to the two-wire terminals 9 and 10 via the output resistor 2.
is output to.

On the other hand, the two-wire signal input to the terminals 9 and 10 is outputted to the terminal 11 as the fourth output value r8 via the differential amplifier 6.4. At this time, the 4-wire input value number VR is the 4-wire force value number r.
In order to suppress the input value to 8, the 4-wire input value signal F'R
are passive circuits 5 with impedance 2° and Z3, respectively.
,6. Subtraction is performed by the differential amplifier 4 via the amplifier 7. Because of this configuration, the two-wire termination impedance FEW is given by twice the resistance 2, and there is no problem if the termination impedance 11N is a pure resistance, but for example, if the termination impedance j'sw is a capacitor of 1 μF and a resistor of 600N, there is no problem. If you try to design it to be equivalent to a series impedance, you will need to replace the resistor 2 with a series circuit consisting of a capacitance of 2 μF and a resistor of 600 Ω.In this case, the 2 μF capacitor will have a large size due to its large capacitance value and withstand voltage. This has the disadvantage that it requires a large volume of elements, resulting in a decrease in packaging density and an increase in price.

In order to eliminate these drawbacks, the present invention uses a passive circuit in the feedback loop that provides a two-wire termination impedance, and if the passive circuit includes capacitance or inductance, the capacitance or inductance value is The purpose is to suppress the withstand voltage to a low level, reduce the size of the capacitance or inductance, and lower the price. The drawings will be explained in detail below.

FIG. 2 shows a first embodiment of the present invention and only shows an AC equivalent circuit. The circuit is a differential amplifier 12°16.14
．． ) 7 register 15. Current amplifier 16. Unlike the passive circuits 17, 18, and 19, the current amplifier 16 is an amplifier that outputs an input current as a complementary current. To explain the operation of this circuit, the signals input to the two-wire input terminals 20 and 21 are detected by the differential amplifier 12, and the differential signal is output to the terminal 22.
The output is outputted to the four-wire output terminal 26 via the differential amplifier 14. On the other hand, the signal applied to the 4-wire input terminal 24 is input to the differential amplifier 16, and its output is input to the base 62 of the transistor 5 and is connected to the emitter 26 of the passive circuit 17.
The voltage/current is converted, and the converted current is output to the collector 27. The output passes through a current amplifier 16, and complementary output currents are output to two-wire input terminals 20 and 21.

That is, the differential amplifier 16. The current converted by the conversion circuit including the transistor 5 and the passive circuit 17 is outputted to the two-wire input terminals 20 and 21 as complementary output currents via the current amplifier 16. Also, 4-wire input terminal 2
The signal applied to 4 is divided by the passive circuits 18 and 19 and input to the differential amplifier 14, thereby suppressing the signal from passing from the 4-wire input to the 4-wire output.

At this time, the characteristics of the circuit are GIW→*w-fa・fa (2)
Also, the balance condition is Zzuden-Zs/z, (4). However, ZIN is the impedance seen from the 2-wire input terminals 20 and 21 to the hybrid circuit, '1+'1sfl*
t4 are respectively current amplifiers 16. Differential amplifier 12,1
The amplification factor of 6°14, ZX, is the 2-wire input terminal 20, 21
The impedance seen from the phone side, a鵞V → 4w is 2
The voltage gain where the voltage between the line input terminals 20 and 21 is output to the 4-wire output terminal 26, G4W->mW is the 4-wire input terminal 24
The voltage is the voltage gain output between the two-wire input terminals 20 and 21.

As can be seen from equation (1), the two-wire impedance zxy
is proportional to the impedance Z1 of the passive circuit 17, and its proportionality constant is '/f112fB. For example, ZXN is a series circuit with a series impedance capacitance of 1 μF and a resistor of 60 oΩ, and a resistor of 600 Initial objectives are achieved.

FIG. 6 shows a second embodiment of the present invention, in which 21 is designed so that ZxytZLIIC is equal in FIG.
In addition, the passive circuits 18 and 19 are replaced with an amplifier 28 having an amplification factor of f, and the amplifier 28 can be realized by simply resistive voltage division.

At this time, the characteristics of the circuit are (1) + (2) * (3) +
<4) To put the formula f ZTJ-Zxy, G 鵞 w-+ 4W -fs af4
(6), and the balance condition is as follows. In general, zl is a complex impedance, 2
Since it is approximated by about 6 to 6 elements, Zl must also be a complex impedance in order to obtain Z IN -ZL, but 2=12. is just an amplifier 28
Since it can be substituted by (6), only one complex impedance Z1 is required in the circuit of Fig. 6, and (6)? As can be seen from equation (7), since the transfer function between the two and four wires is a real number, the frequency characteristics are flat and the transmission characteristics are excellent.

FIG. 4 shows still another circuit configuration example of the partial circuit consisting of the transistor 15 and the passive circuit 17 in FIGS.
In this circuit example, ZIM consists of 1. ．． 1γ
are the conversion coefficients of the voltage-current conversion circuit 29°60, and z4 is the conversion coefficient of the passive circuit 61 if the impedance of the passive circuit 61 is used.
Impedance ZXM proportional to the reciprocal of 1 can be realized. This shows that if a capacitor is used for Z4, ZIN can be designed as an inductance, and conversely, if an inductance is used for 24, ZXM can be designed as a capacitor.

It is clear that in the above embodiments, the voltage signal is replaced by a current signal, the current signal is replaced by a voltage signal, and the amplifier also operates by replacing the current type with the voltage type. It is also clear that a PNP type or FET can be used as the transistor 15.

FIG. 5 shows a more specific circuit configuration of this embodiment. The circuit components in FIGS. 2 and 6 correspond to the circuit components in FIG. 5, respectively, as follows. That is, the 2-wire input terminals 20 and 21 are connected to 2W, and the differential amplifier 12
(f*) is the current amplifier 4+A! +J! , output terminal 22
is at point Q, the differential amplifier 16 (rs) is for current addition at point Q, the conversion circuit including transistor 15 and passive circuit 17 (Zl) is at circuit B1, and passive circuit 17 (Zl) is at point Q.
) is the impedance 2. of the circuit B1. , current amplifier 1
6 (pt) is connected to circuit B3 and current amplifiers cl and cl, and voltage amplifier 2B (f@) is connected to current amplifier E3.
At the output of 1/2, the differential amplifier 14 (f4) is connected to the circuit E1.
corresponds to Note that 1 in Figure 5. is the communication current, VL is the voltage across the two-wire χ power terminal 2W, VBB is the power supply voltage, Vrd
is each transistor QttQ! in the circuit Bs. -Appropriate voltage to be applied within a range that does not saturate Q4, e.g. -5V, C
Do is the capacity for supplying current to the telephone. In addition, the current amplifiers AI, A鵞*BIs '1 * '11 EM are equipped with a current mirror circuit (e.g. @Analysis).
and Dasi-gn of Avsalog In
tegrated C4rcs4t”PmL R,Gr
ay, Robert G., Mayor: John
Filmy & 5ons, 1977 F, 197
~261 especially p, 266.266 Fig, ) can be used.

Next, the operation of this circuit will be explained. First, we will discuss the operation of DC characteristics.

The pace of the transistors in the current amplifier AI, A,
Since the emitter voltage drop is small compared to the power supply voltage VBB, it can be ignored: ground, current amplifier AI, resistor R1,
'lW, resistor R1, current amplifier 4s The current flowing through resistor R1 on the path to the FBI power supply is I VBys l
-FL 2R.

This becomes the input current of current amplifiers AI and AI, and the output of current amplifier A1 is input to current amplifier B2,
Its output is current amplifier A! output and point P.

are added at Q. Also, n of current amplifier c1: 1:2
The flow point of n/2 of the line current IL is input to the base of the transistor Ch (h) in the circuit B3.The current amplified by the transistor Q1. The current flowing into B3 is added and input to current amplifier C!, and n=1:1 of current amplifier C2.
The output of n is connected to the 2WA terminal, the output of 1 is input to the current amplifier c1, and the external output of fL:1:2 is connected to the 2WB terminal.

This DC circuit operates only for DC signals due to the capacitance CDO in circuit B3, and does not operate for AC signals.

Next, the operation of AC characteristics related to the present invention will be described.

The voltage at the 2W end is converted into voltage/current by current amplifiers AI, AI and resistor R1, and the output of current amplifier A is input to current amplifier B, and its output is added to the output of current amplifier A3 at point Q. , whereby the differential signal at the 92F end is detected. This current is input to the circuit B1, and the operational amplifier operates so that a potential drop equal to the potential drop occurring across the resistor R, occurs in the impedance Zx, and the collector current of the transistor Q3 changes to the circuit B! The current input to is multiplied by R1/Zx. This current is inputted into the current amplifier C3 through the common base transistor Q4 in the circuit B3, and the external output of 11:1 is outputted to the 2-wire input 2FA, and the output of 1 is outputted to the current amplifier C1 and outputted to the current amplifier C3. It is output to the line input WB.

Also, the signal from the 4-wire input 41F'R is connected to the capacitor and resistor R4.
is converted into a positive current by current amplifier E2, and its output is added to point Q. (This corresponds to the function of the differential amplifier 13 (fs).) In addition, for signal transmission from 2 wires to 4 wires, the 2 wire signal is converted into voltage and current by current amplifier A1 * 4 and resistor R1, and the output of current amplifier A1 is is the current amplifier E
, and its output is added to the output of current amplifier A at point S and output to four-wire output WE via differential amplifier E1. Echo suppression is achieved by converting the 4-wire input 4WR signal into a current amplifier, 1 E! It is output to the 7 output of 1.7:1 of the differential amplifier E.
1 to suppress echo.

Expressing the above circuit characteristics as a formula, we get Therefore, the cancellation conditions are It is.

As explained above, in order to provide the impedance ZXM on the two-wire side of the electronic hybrid circuit, the impedance Z! Alternatively, by inserting a passive circuit of Z4, the impedance ZXX on the two-wire side is proportional or inversely proportional to the impedance Z1 or Z4, and by appropriately selecting the proportionality constant or inverse proportionality constant, the impedance Z1゜Z4 The element value of the capacitance or inductance used for the
Since the circuit can be designed so that the voltage applied to the 2-wire input terminal is smaller than the DC voltage applied to the 2-wire input terminal, a low-voltage element can be used, which makes it possible to downsize and economize the elements of a passive circuit with impedance Z1 or Z4. It is valid.

[Brief explanation of drawings]

FIG. 1 shows a conventional electronic hybrid circuit, FIG. 2 shows a first embodiment of the present invention, FIG. 6 shows a second embodiment of the present invention, and FIG. 4 shows the first and second embodiments. Another circuit configuration example of the partial circuit, FIG. 5, is a specific circuit configuration of the embodiment. 1...Amplifier, 2...Output resistance, 3.4,12,1
3.14... Differential amplifier, 5, 6.17, 18.19
...passive circuit, 7,28...voltage amplifier, 8.24
...4-wire input terminal, 9,10,20.21...2-wire input terminal, 11.23...4-wire output terminal, 15...
Transistor, 16...Current amplifier, 22.25...
・Output terminal, 26...Emitter, 27...Collector, 62...Pace, 29.60...Voltage-current converter, 61...Passive circuit, Al* A2 + Bx *
C1 @ Cz t E @...Current amplifier patent applicant Nippon Telegraph and Telephone Corporation Patent attorney Kugo Tamamushi Department (6 others) Figure 1 Figure 3/16 Figure 4

Claims (1)

[Scope of Claims] A circuit for providing input impedance of a 12-wire balanced signal line input impedance of a complex impedance includes a detection circuit for detecting a 2-wire input value signal, and a detection circuit for detecting a signal by the detection circuit. a passive circuit of impedance Z that inputs the output of the passive circuit; a conversion circuit that converts the output from the passive circuit into a signal proportional to the impedance Z or 1/z of the passive circuit and outputs the signal; 1. An electronic hybrid circuit comprising an output amplification circuit which inputs an output and outputs the output to the two-wire balanced signal line. 2. A patent characterized in that a 4-trimmed balanced input value signal is applied between the detection circuit and the conversion circuit, and the input signal is output to the 2@balanced signal edge side via the conversion circuit and the output amplification circuit. An electronic hybrid circuit according to claim 1. 5. Set the impedance of the 2-layer capacitor to the above z, 11. 2. The electronic hybrid circuit according to claim 1, wherein: is set equal to the balanced signal-side impedance, and the passive circuit that defines the balance condition is configured by a resistive voltage divider or a voltage amplifier.