JPS6146990A - Level display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a level display device for a device for recording or reproducing a PCM digital signal, for example.

2. Description of the Related Art Conventional Structures and Problems There has been remarkable progress in recent years in so-called PCM devices that convert analog signals into digital signals and perform signal processing. CD players are already on the market as playback devices, and PCM tape recorders for consumer use are also expected to be commercialized in the near future. In such audio equipment, particularly tape recorders, a level display device for monitoring the recording signal level is essential. The level display device of the conventional analog tape recorder
In recent years, bar graph level display devices using light emitting diodes, fluorescent display tubes, etc. have become mainstream instead of conventional needle-hole meters. PC that handles digital signals
In M devices as well, the absolute value of a digital signal is often displayed using a bar graph type level display device.

A level display device in a conventional PCM device will be explained below. FIG. 1 shows the most basic level display device used in a conventional PCM device. Normally, the digital signal handled by a PCM device consists of a word representing one amplitude level in units of 14 bits to 16 pinots, but here, for simplicity, 8-bit digital data is input, and it is transmitted to 6 light emitting units. Consider the case where level display is performed in the form of a bar graph using diodes.

In Figure 1, 1A to 1H are input terminals into which digital signals are input, and 1A is the most significant bit (hereinafter referred to as MS).
) is input, and in the following order, 1B is the second pit,
It is assumed that the third bit is input to 1C, and the least significant bit (hereinafter referred to as LSB) is input to 1H. 2 is A
ND gates, 3A to 3D are OR gates, 4A to 4F are open collector inverters, 58 to 5F are light emitting diodes, and 6A to 6F are current limiting resistors.

FIG. 2 is a truth table showing the states of the light emitting diodes in response to the input digital signal in the configuration shown in FIG. 1, and the light emitting diodes 5A to 5F are turned off at "Q".

It is assumed that "1" represents the lighting state. In addition, generally PC
The digital signals contained and handled inside the M device are 2S COMPLEMENTARY codes, but 2S COMPLEMENTARY
If the complementary code is used as it is, each bit pattern of the digital signal expressing the value is completely different depending on whether the amplitude is positive or negative. In many cases, the input 8-bit digital signal is converted into a double code and then handled once, but in this example, for simplicity, the input 8-bit digital signal has already been converted into a double code.
1", that is, state 1 in FIG. 2, the output of the AND gate 2 becomes "1", and therefore the output of the open collector inverter 4A becomes 0", and the output from the power source 1B passes through the current limiting resistor 6A to the light emitting diode 5A. current flows,
Light. In addition, since the digital signal input to input terminal 1B and below is also 1", open collector inverter 4
The inputs of B to 4F are all "1", and the light emitting diodes 6B to 6F are also lit. In addition, in the case of state 2 in FIG. 2, that is, when the digital signal to the input terminal 1A is at least 1'', the input of the open collector inverter 4B becomes 1'', and the OR gates 3A to 3D Open collector inverter 40~4F input also -
1", and accordingly, the light emitting diodes 5B to 6F light up. Similarly, in state 3 in FIG. 2, the light emitting diodes 50 to 5F light up because the digital signal input to the terminal 1B is at least "1".

In state 4, the light emitting diodes 5D to 5F light up when the digital signal input to terminal 1C is "1", and in state 5, the light emitting diodes 5D to 5F light up when the digital signal input to terminal 1D is "1". sE,s
F is lit, and in state 6, the light emitting diode 5F is lit because the digital signal input to at least terminal 1E is 1'', and in state 7, the digital signal input to at least terminals 1A to 1E is all 0°''. As a result, all of the light emitting diodes 5A to 5F are turned off.

FIG. 3 is a diagram of a level display section in which the light emitting diodes 58 to 5F correspond to levels. If all the bits of the input digital signal are 1", it is impossible to express a value higher than that with the digital code 1", so the light emitting diode 5A is used in the sense of over level.
For example, the digital signal power input to input terminals 1A to 1H is displayed as "Q1oVER".
If we display the case of ``ooooo'' as the reference level = o dB, which is the reference level for recording, playback, etc., the input digital signal is 1oOoO○Oo''
When , +adB, -oolo.

000'' can be expressed as -6 dB.In other words, in the case of a digital signal, when the bit increases by one digit, the value expressed by that digital signal doubles, so if expressed in decibels, it becomes 201 oqlo 2''-6 (dB). Therefore, the level display based on FIG. 2 used in this example becomes a level display in adB steps as shown in FIG. 3. For example, in the case of state 3 in Fig. 2, the input digital signal power is from ``01000000'' to ``01111111'', that is, Od for the range of 0 ≦input value 6 in terms of dB dB bell.
B will be displayed. The level display device described above can be realized with a relatively simple circuit configuration, but in reality, the number of bits of the digital signal handled by the PCM device is 14 to 16.
The number of segments such as light emitting diodes used for bit and level display is 15 to 40 points, the display level is ±o,
A minimum interval of approximately sdB to 1 dB is required, making the circuit extremely complex.

FIG. 4 shows an example of a conventional circuit for inputting a 12-bit folded 2-command digital signal and displaying a level using 24 segment light emitting diodes. FIG. 6 is a truth value diagram showing the light emitting diodes that light up in response to the input digital signal in FIG. 4, and FIG. 6 is a diagram showing the correspondence between the light emitting diodes and the level display section.

The basic operation in FIG. 4 is the same as in FIG. 1. In Fig. 4, 68 to 6L are input terminals into which digital signals are input (MSB on facing 6A, LS on 6L)
B is input) 7A~7■ is N■ gate, 8A~a
Z, 8a to aa are OR gates, 9A to 9x are open collector inverters, 10A to 10x are light emitting diodes, and 11A to 11X are current limiting resistors.

In FIG. 5, for states 1 to 24 indicating the lighting/extinguishing states of the light emitting diodes, the input terminals 6A to 6 for suddenly turning on/off the respective light emitting diodes are
Among the digital signals input to L, the smallest value digital signal is written. Further, the state of the light emitting diode is the same as in FIG. 2, where "1" indicates lighting and "0" indicates off. In this example, the reference level is set to a level 20 dB lower than the highest value of the digital signal expressed using a 16-bit two's complement code that is generally handled by a PCM device. The terminals 68 to 6L are connected to the digital signal expressed using the 16-bit two's complement code, which is then converted to 1 representing the absolute value.
It is assumed that only the upper 12 bits of the 5 bits converted into 2 brigadier generals are input. In addition, the light emitting diode used as the bar graph-like level display section at the first festival is +20 dB to - as shown in Figure 6.
42 dB The 12-bit digital signals inputted to the input terminals 6A to 6L and represented by the 2 brigadier general numbers are 8M, 8T, and 8V.

sX, aZ, sC, sdK! , 9 States 1-2 in Fig. 5
Classified as 5. OR gate 8M, 8T, 8V.

The OR gates other than sX and sZ are for the purpose of always turning on the light emitting diodes displaying a lower level when a light emitting diode displaying a certain level is turned on.

Now, let us consider the operation of FIG. 4 in the case of state 1 in FIG. 5 as an example. Input terminal 6 which is at least the upper 4 bits of the digital signals input to input terminals 6A to 6L.
AN that the digital signal to 8~6D is 1''
D game) 7A, 7B.

7S, the open collector inverter 9A drives the light emitting diode 10A, and the O
All light emitting diodes of 10B or less are also turned on by the R gate. Originally, in state 1, which indicates the highest level state, all 24 light emitting diodes below 10A should be lit when all bits of the digital signal input to input terminals 6A to 6L are 1". However, it takes 12 people to detect this
Since an ND gate is required and the circuit scale increases, in this example, at least the top four of the input digital signals are
If the pit is 1", the light emitting diode 10A lights up. Therefore, the light emitting diode 10A
Although on the display the level represented by the input digital signal is +20 dB above the reference level, it actually lights up when the level is +19.442 dB or higher.

If a digital signal is input to the input terminals 68 to 6L, the lights will turn on, resulting in an error of 5 dB or more. In FIG. 6, the display level and the minimum level value that actually turns on are shown together.

Further, taking state 20 in FIG. 5 as an example, the minimum input digital signal showing a display level of -18 dB is "oOo000110ooo" in order from the upper pit, and the input digital signal (state 19 "000001100000") until transition to state 19 is "oOo000110ooo". ), the digital signal included in state 20 is divided into two types as shown below, and state 2O-A-000001 is detected.
0000008 or above State 20-A is the digital signal state to input terminal 6F 9.2 o -B is input terminal eG, eH
The state 20-A and the state 20-B are logically summed by the OR gate 82, thereby detecting the state 820.

As explained above, in the conventional level display device composed of AND and OR gates, (1) the number of circuit components increases significantly as the number of elements used for level display (light emitting diodes in this example) increases; .

(2) If an attempt is made to reduce the number of circuit elements, an error will occur between the displayed level (scale) and the actual lighting level.

(3) The number of circuit elements increases depending on the display level and level interval.

(It is necessary to design independent circuits depending on the level to be displayed at 71 levels and the number of segments used to display one level interval.

There were drawbacks such as. One of the Ike's methods that has been proposed to overcome this drawback is read-only memory (
There is a method of using a ``memory device'' (hereinafter referred to as a ``memory device''). This uses input digital signals as address signals for the memory device, and displays level display outputs corresponding to each input digital signal in advance on a one-to-one basis.
It is written into the memory device in advance, and the read output of the memory device is directly used as a level display output. However, when this method is used, there is a one-to-one correspondence between the input digital signal and the level display output, so in the case of FIG. 6, for example, the required memory device capacity is Since the bit and level display output is 24 pits, 2 x 24 = 9830
Since it is 4 bits and requires a huge amount of capacity,
The drawback was that it was not practical in terms of cost.

OBJECTS OF THE INVENTION In view of the above drawbacks, the present invention provides a level display device with a simple circuit configuration and high accuracy.

Structure of the Invention In order to achieve this object, the level display device of the present invention has the following features:
A first digital signal input from the outside and to be displayed as a level and a second digital signal read from a predetermined address of a read-only memory device (hereinafter simply referred to as a memory device) are input, and the first digital signal is read from a predetermined address of a read-only memory device (hereinafter simply referred to as a memory device). a digital comparator that compares the magnitude relationship of second digital signal values to obtain a predetermined output signal; an address counter that supplies an address signal to the memory device; It is composed of a latch that takes in the address signal output, and a level display drive circuit that uses the output signal of the latch as input information and drives the level display section according to the input information. Continuously reading out a second digital signal previously written in the memory device in response to the first digital signal value, that is, a digital signal corresponding to a threshold value at which the display state of the level display section should change; The magnitude relationship is compared by a Fiff digital comparator, and based on the output of the comparison result, the level of the address signal supplied to the memory device is displayed by a latch. By taking in the information as input information to the 1iI circuit, a highly accurate level display device can be realized with a simple circuit configuration.

DESCRIPTION OF THE EMBODIMENT FIG. 7 is a circuit diagram for realizing the level display shown in FIG. 5 in an embodiment of the present invention.

Figure 8 is a timing chart corresponding to each part of Figure 7,
FIG. 9 summarizes the digital signals and display levels output to each address of the memory device used in FIG. 7, and the minimum input digital signal value to achieve each display state.

In FIG. 7, 6A to 6L are input terminals into which a 12-bit digital signal represented by a folded 2 brigadier general symbol to be displayed is input, 12 is a digital comparator, and 13
14 is a memory device, 14 is an address counter for supplying address signals to the memory device 13, 15 and 16 are input terminals for inputting clock pulses, 17A and 17B are launches, 18 is a level display drive circuit, and 19 is a level This is the display section. The operation will be explained below using FIGS. 7 to 9. Incidentally, the timing chart of FIG. 8 represents the signal waveforms at the input/output terminals of each section in FIG. 7 by the names of the terminals of each section.

First, a 12-bit digital signal whose level is to be displayed is input to the input terminals 68-6L, and then applied to one input terminal 68-8 of the digital comparator 12. On the other hand, in synchronization with the digital signals input to the input terminals 6A to 6L, the clock pulses of CK1 and R/CK3 shown in FIG. It is reset during the "L" section of the clock pulse applied to the clock terminal CK1, and thereafter, the counting operation is performed at the rising edge of the clock pulse applied to the clock terminal CK1. 26 steps of address signals ad□-ad2s are applied to the address signal input terminals ADo to AD4 of the memory device 13 for one cycle of the digital signal to be displayed and input to the input terminals 6A to 6L. In the device 13, 12-bit digital signals written in advance at the corresponding address in accordance with each address signal are output to output terminals 00 to 00 in order from the largest value according to FIG.
011, the other input terminal B of the digital comparator 12. -B11 is input.

In FIG. 9, the output terminals 00 to 00 correspond to each address of the memory device 13 that realizes the level display shown in FIG.
011 is shown. The ROM capacity required here is at most 25 steps x 12 pits:
It is 300 bits.

In the digital comparator 12, the input terminal Ao-A11
and B. - The magnitude relationship between the two digital signals input to B11 is compared in sequence, and the input terminal B is output.

~The digital signal value input to B11 is input to input terminal A.
. - If it is larger than the digital signal value input to A11, "L" reliability is obtained at the output terminal A (B). Therefore, in this example, the digital signal to be level displayed is sequentially read out from the memory device 13. The digital comparator 12 performs a magnitude comparison with 25 types of digital signals, and the respective comparison results are obtained at the output terminal A (B).

The obtained comparison output is sent to the clock terminal CK2 of the latch 17A.
In the latch 17A, the input terminal is turned on at the rising edge of the clock pulse supplied to the clock terminal CK2. - Takes in the address signal given to D4 and outputs it to output terminal Q. -04. In the example shown in FIG. 8, when the address signal a d 11 is output, the digital signal corresponding to the address signal a d 11 is also read out from the memory device 13, and its value becomes the digital signal value (the input of the Since the value of the digital signal input to terminal A.-A11 is smaller than that of the digital signal input to terminal A.
Therefore, the latch 17A receives the address signal a.
d11 is taken in and output terminal Q. - Output to Q4. The address signal taken into the latch 17A is contained again by the latch 17B at the falling edge of the clock pulse to the clock terminal CK3 in order to keep the level display time constant, and is supplied to the repeat display drive circuit 18. .

The level display drive circuit 18 converts the supplied address signal into a signal for driving the level display section 19 as level display information for level display and outputs the signal.

A configuration example of the level display drive circuit will be described later.

Therefore, the digital signal input in interval T1 and whose level should be displayed is displayed in level in interval T2.

As described above, according to this embodiment, the address signal supplied to the memory device 13 is used to code all 12-pit input digital signal patterns into 25 types of level display states. ing. In other words, in order to express 26 types of level display states, 2
×25 It is sufficient to use a 5-bit address signal.

Each display level and its actual display state according to this embodiment
The input digital signal values for the input are compared as "display level" and "actual level" in FIG. 9, but as described above, according to this embodiment, the most Since a 12-pit bit pattern close to the display level can be written in the memory device 13, the error between the "display level" and the "actual level" is 20 points above and below the odB, which is particularly important for level display.
It is within ±o, i dB in the dB range,
Level display can be performed at extremely accurate levels. In addition, since it is possible to handle different display devices such as display levels and display steps using the same circuit by simply changing the contents written in the ROM, there is no need to design a separate dedicated level display device, and the circuit can be shared. is possible. .

Furthermore, in this embodiment, the A (B terminal) is used as the magnitude comparison output of the digital comparator, but the lighting conditions for the light emitting diode that displays the level of +e dB, for example, are based on the input digital signal value to be displayed as a level. D
dB, then 6dB≦o, <, dB. If you want to change this to, for example, the lighting condition of 6dB<p≦8dB, use a digital comparator.
Input terminal A of router 12. -A11. When the input digital signals to Bo-B11 match (are equal), a matching output signal is obtained. Output terminal A=B and A (by using the logical sum of B and B as the magnitude comparison output of the digital comparator 12, it is easy to do this. can be realized.

In this embodiment, the digital signals read out from the memory device 13 are read out sequentially starting from the largest value, but it goes without saying that the same effect can be obtained even if the digital signals are read out sequentially starting from the smallest value.

A configuration example of the level display drive circuit used in this example is shown in the 10th example.
As shown in the figure. The portion surrounded by a broken line in FIG. 10 corresponds to the level display drive circuit 18 in FIG. 20
A to 20E are input terminals for the output signal of the latch 17 in FIG. 7, that is, a 6-bit digital signal representing the level display state, and 21 is an output terminal M in response to the digital signal input to the control terminals 80 to S4. - Demultiplexer, 22A~, which outputs "H" level to any one of M23, or all of them are "L";
22W is an OR gate, 2sA to 23X are open collector inverters, 24A to 24X are light emitting diodes that constitute the level display section shown in Fig. 6, and 25A to 25X.
is a current limiting resistor. In the demultiplexer 21,
For example, all of the 6-bit digital signals input to the control terminals 80 to S4 representing the level display state are °'L.
”, the open collector inverter 23A can be configured so that an “H” output can be obtained only from the output terminal M.
The input becomes "H" and the output becomes "L'", so that current flows to the light emitting diode 24A through the current limiting resistor 25A, and the light emitting diode 24A becomes lit. Further, the OR gates 22A to 22W also turn on the light emitting diodes 24B to 24X, and the level display section becomes a level display state of +20 dB.

Similarly, depending on the condition of the 25 types of digital signals input to the input terminals 208-20H, any one of the 24 outputs M0-M23 of the demultiplexer 21 becomes "H", or all of them become "H". By selecting the state of "L", 25 types of level display states are realized.

In addition to the above-mentioned demultiplexer OR gate, the level display drive circuit loads a 6-bit digital signal representing the input level display state into a binary counter, counts clock pulses from the loaded value, Callan l when carry comes out
-If the configuration is configured to stop the ut operation, a level display output corresponding to the loaded digital signal value can be obtained as a serial signal, so if this is converted from serial to parallel and latched, OR gates can be used frequently. It is also possible to realize a similar level display drive circuit.

Further, although the level display section used in this embodiment was constructed from a light emitting diode, it may be realized using a fluorescent display tube or the like instead.

Effects of the Invention According to the present invention, a first digital signal to be level-displayed which is inputted from the outside and a second digital signal read from a predetermined address of a memory device are inputted, and the first digital signal is inputted from the outside and the second digital signal is read from a predetermined address of a memory device.
A digital counter that compares the magnitude relationship of second digital signal values to obtain a predetermined output signal, and a level display drive circuit that drives a level display section according to the input information as output power information of the digital comparator, A highly accurate and highly versatile level display device can be realized with a simple configuration, and its effects are significant.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional basic level display device;
The figure shows the operating conditions of the circuit shown in FIG. 1 (a circuit diagram of an embodiment of the cow footrest, FIG. 8 is a timing chart of each part of the block diagram shown in FIG. 7, FIG. 9 is an output signal state diagram corresponding to each address of the memory device used in the block diagram shown in FIG. 7, and FIG. It is a circuit diagram showing an example of the level display drive circuit used in the block diagram shown in the figure. 12...Digital comparator, 13...
... Memory device, 14 ... Address counter, 18 ... Level display drive circuit, 19 ...
...Level display section. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Level: 0'/E scale ÷ 6cLB 6dB -/2dB -/8cLfJ). 0D Figure 6 - 7th Figure 7 LH5B Figure 9 Figure 1O

Claims (1)

[Claims] A first digital signal input from the outside and to be displayed as a level and a second digital signal read from a predetermined address of a read-only memory device are input, and the magnitude of the first and second digital signal values is determined. a digital comparator that compares the relationship to obtain a predetermined output signal; an address counter that supplies an address signal to the read-only memory device; and an address counter that is controlled by the output signal of the digital comparator and takes in the address signal output of the address counter. 1. A level display device comprising a latch and a level display drive circuit that uses an output signal of the latch as input information and drives a level display section according to the input information.