KR910000148B1 - 8-10 bit modulating circuit of digital audio tape recorder - Google Patents

Abstract

The circuit has a digital sum generating circuit (1) including a ROM(ROM1) for generating 10-bit code word signal by a clock signal (CLK2), a parity generator (PG1) for generating parity code, a PTS converter (PTSC1) for converting output data of the ROM to series data by a control signal (CS2)and a clock signal (CLK3), a NRZI converter (NRZIC1) for NRIT converting of output signal of the PTSC1 by clock signal passed through an EXOR gate, a binary up down counter (BVDC1) for counting the output signal of the NRZI converter utilizing clock signal passed through an EXOR gate (EXOR1), and a comparator (COMP2) for comparing output signal of the counter with reference signal.

Description

8-10 bit modulation circuit of digital audio tape recorder

1 is a schematic diagram showing an 8-10 bit modulation encoding algorithm.

2 is an 8-10 bit modulation table to which the present invention is applied.

3 is an 8-10 bit modulation circuit diagram of the present invention.

4 and 5a-m are output waveform diagrams of respective parts of FIG.

6 is the truth table of the multiplexer of FIG.

* Explanation of symbols for main parts of the drawings

LA ₁ : Datalatch ROM ₁ : ROM

PG ₁ : Parity Generator MUX ₁ : Multiplexer

FF ₁ : Flip-Flop PTSC ₁ : Parallel / Serial Converter

NRZIC ₁ : NRZT Converter BUDC ₁ : Binary Up / Down Counter

COMP ₁ : Comparator EXOR ₁ : Exclusive Oagate

The present invention relates to an 8-10 bit modulation circuit of a digital audio tape recorder, and more particularly, to an 8-10 bit modulation of a digital audio tape recorder adapted to convert 8 bit input data into 10 bits according to an 8-10 bit modulation table. It is about a circuit.

The 8-10-bit modulation encoding algorithm of FIG. 1 and the modulation table of FIG. 2 are determined at the meeting of the digital audio tape recorder, and the 8-bit data signal and the digital thumb value (DC) information signal (Q ') of the previous code. The 10-bit codeword (premodulation data) and the digital thumb value (DC) information signal (Q) of the code are obtained according to the modulation table of FIG. 2. The digital thumb value (DC) information signal (Q ') of the previous code is obtained. Is a low potential signal (logical "-1"), the digital thumb value (DC) information signal (Q) of the code calculates the digital thumb value (DC) of the 10-bit codeword, and the digital thumb value (DC) is a low potential signal. (Logic " 0 ") and the high potential signal (Logical " 2 "), that is, as shown in the modulation table of FIG. 2, the digital thumb value (DC) information signal Q 'of the previous code is a low potential signal (logic). "-1" and the digital thumb of the code when the 10-bit codeword is odd parity when the digital thumb value (DC) is a low potential signal (logical "0"). (DC) The information signal Q is the information signal Q being a high potential signal (logical "1"). If the 10-bit codeword is even parity under the above conditions, the digital thumb value (DC) information signal of the code ( Q) becomes a low potential signal (logical "-1"), and the digital thumb value (DC) information signal Q of the code is used as an information signal for modulation of the next data word.

Also, when the digital thumb value DC information signal Q 'of the previous code is a high potential signal (logical "1") and the digital thumb value DC is a low potential signal (logical "0"), a 10-bit codeword In the case of odd parity, the digital thumb value (DC) information signal (Q) of the code is a low potential signal (logical "-1"). In the case of even parity, the digital thumb value (DC) information signal (Q) of the code is a high frequency. If the digital thumb value DC is not a low potential signal, the values of even and odd parity are reversed.

The present invention was designed to convert 8-bit input data into 10-bit by the configuration of the 8-10-bit modulation circuit of the digital audio tape recorder according to the 8-10-bit modulation table. Same as

FIG. 3 is an 8-10 bit modulation circuit diagram of a digital audio tape recorder according to the present invention. As shown in FIG. ₃ , a clock signal applied to data inputted to the input terminals DI ₇ -DI ₀ to the clock terminal LCK _{1 is} shown in FIG. The data latch LA ₁ temporarily stores and outputs the data according to the CLK ₁ and the output signal of the latch LA ₁ and the output signal of the flip-flop FF ₁ are applied to the clock terminal RCK ₁ . A ROM (ROM ₁ ) for outputting a 10-bit codeword signal by the clock signal CLK ₂ , a parity generator (PG ₁ ) for parity checking according to the output signal of the ROM (ROM ₁ ), and the ROM ( After loading the output signal of the ROM ₁ ) according to the load control signal CS ₁ applied to the load terminal PL, the control signal CS ₂ and the clock applied to the control terminal CIN and the clock terminal PCK ₁ . the output of the parallel / serial converter (PTSC _1), the P / S converter (PTSC ₁₎ for converting the serial data by a signal (CLK ₃₎ A clock terminal (NCK ₁₎ exclusive Iowa gate (EXOR ₁₎ NRZI accordance with the clock signal through to be applied to the arc (Non Return to Zero Inverted: NRZT ) converting NRZI converter (NRZIC _1), the NRZI converter (NRZIC that ₁ ) a binary up / down counter (BUDC ₁ ) for up / down counting the output signal of the output signal according to the clock signal through the exclusive ore gate EXOR ₁ applied to the clock terminal CCK ₁ , and the binary up / down counter. A digital thumb generating circuit (1) comprising a comparator (COMP ₁ ) for comparing the output signal of the counter (BUDC ₁ ) with a reference signal applied to the reference terminals (V ₁₄ -V ₁₀ ), and the digital thumb generating circuit (1). The multiplexer MUX ₁ selectively selects and outputs the output signal of the parity generator PG ₁ according to the output signals of the comparator COMP ₁ and the flip-flop FF ₁ .

Referring to the effects of the present invention configured as described above in detail.

When a data signal is input to the input terminals DI ₀ -DI ₇ , the input data signal is input to the input terminals D ₇ -D ₀ of the data latch LA ₁ and clocked to its clock terminal LCK ₁ . As the signal CLK ₁ is applied, that is, at the time when the clock signal CLK ₁ rises, the input data signal is latched to the data latch LA ₁ and its output terminals L ₇ -L ₀ at the time of the fall. And the output signal is applied to the address terminals A ₇ -A ₀ of the ROM (ROM ₁ ) and at the output terminal Q ₁ of the flip-flop (FF ₁ ) to the address terminal A _{8 thereof} . The output signal is applied as the digital thumb value DC information signal Q 'of the previous code.

By the way, a 10-bit codeword is stored in the ROM ₁ according to each corresponding address.

Accordingly, in response to the signal applied to the address terminals A ₈ -A ₀ , the ROM ROM ₁ has its output terminal R ₉ at the time when the clock signal CLK ₂ applied to its clock terminal RCK ₁ rises. A 10-bit codeword signal is output to -R ₀ ), and the output 10-bit codeword signal is output to the output terminals OUT ₉ -OUT ₀ and the input terminal I ₉ -I of the parity generator PG ₁ . ₀ ) is input to the parity detection, that is, the high potential signal is output to the even and odd output terminal (EVEN) (odd) according to the even and odd parity, and the input terminals MI ₁ , MI ₄ of the multiplexer (MUX ₁ ) ( MI ₂ , MI ₃ ) are commonly input to each other, while the 10-bit codeword signal output from the output terminals R _9- R ₀ of the ROM (ROM ₁ ) is input to the parallel / serial converter (PTSC ₁ ). is input to the (P ₉ -P ₀₎ is loaded in parallel in the falling time of the load control signal (CS ₁₎ which is applied to its load terminal (PL), a parallel / serial converter (PTSC ₁₎ The output terminal of Luck terminal (PCK ₁₎ and the control terminal a clock signal (CLK ₃₎ rising time point and a control signal (CS ₂₎ is converted at the falling time of the serial parallel / serial converter (PTSC ₁₎ of which is applied to the (CIN) is output to the (So), that the output signal is the clock signal (CLK ₃₎ and a control signal (CS ₂₎ is applied to the input to the input terminal (NI) of the NRZI converter (NRZIC ₁₎ its clock terminal (NCK ₁₎ Is converted to NRZI at the time of falling of the signal output through the exclusive oar gate (EXOR ₁ ), and the converted signal is output to the output terminal (No) of the NRZI converter (NRZIC ₁ ) and the binary up / down counter (BUDC) ₁ ) is applied to the up / down input terminal (U / D), and at this time, its input in the high potential signal section of the control signal (CS ₃ ) applied to the load terminal (LD) of the binary up / down counter (BUDC ₁ ). one after loading into the terminal (V ₄ -V _0), the reference signal a signal (000 ₂₎ to be input to the counting at the falling time of the clock signal applied to the clock terminal (CCK ₁₎ .

That is, the NRZI converter (NRZIC ₁₎ up counting from the output terminal in a low potential signal portion of the signal output from the (No) the reference signal (000 _2), the down counting from, the high-potential portion of the signal based on the signal (000 ₂₎ When the to 2 jineop / down counter (BUDC ₁₎ clock terminal (CCK ₁₎ 10 of the clock signal is completed, to be applied to the second jineop / down counter (BUDC ₁₎ will stop the count, and the second jineop / down counter ( The result of counting during the high potential signal of the control signal CS ₄ applied to the control terminal OE of the BUDC ₁ ) is output to the output terminals B ₄ -B ₀ , and the output counted signal is the comparator COMP. after comparison with the ₁₎ comparison terminal (C ₄ -C is input to the ₀₎ reference terminal (V ₁₄ -V ₁₀₎ a reference signal (000 ₂₎ is applied to the case of the same is low in its output terminal (CV ₀₎ If the output voltage signal, that is not the same, larger or smaller, the case outputs a high potential signal of the flip-flop (FF ₁₎ Applied to the output selection terminal (S ₁₎ (S ₂₎ of each of the multiplexers (MUX ₁₎ with the output signal outputted from the (Q ₁₎ that is, a multiplexer (MUX ₁₎ is in accordance with the truth table shown in Figure 6 its input terminal (MI ₁ -MI ₄₎ of the selective selected by the flip-flop (FF ₁₎ to the signal input to the input terminal (D) is applied to the clock signal applied to its clock terminal (DCK ₁₎ (CLK ₁ ) Is output to the output terminal Q _{1 in a} repetitive operation as described above as a word value of the next data.

Here, an example of data signal input according to the modulation table of FIG. 2 will be described in detail with reference to FIGS. 3 to 6 as follows.

First, the low potential signal is initially outputted from the output terminal Q ₁ of the flip-flop FF _{1 to} the information signal Q 'of the pre-modulation code, and then the input terminal DI ₇ -DI _{0 of} FIG. As shown in (a), when the data signal (00000000 ₂ ) is input, the input data signal is input to the input terminals (D ₇ -D ₀ ) of the latch (LA ₁ ) to its clock terminal (LCK ₁ ). As the clock signal CLK ₁ as shown in FIG. 4 (b) is applied, that is, at the rising point of the clock terminal LCK ₁ , the input data signal is latched to the latch LA ₁ to the falling point. Is outputted to its output terminal (L ₇ -L ₀ ), and the output signal is applied to the address terminal (A ₇ -A ₀ ) of ROM (ROM ₁ ) and its address terminal (A ₈ ) The low potential signal output from the output terminal Q of the flip-flop FF ₁ initially set as the digital thumb value DC signal is applied.

Accordingly, the clock signal CLK ₂ is output to the output terminals R _9- R ₀ of the ROM ROM ₁ according to the signal applied to the address terminals A ₈ -A ₀ as shown in FIG. At the rising point of R < 1 >, a 10-bit conversion data codeword signal (0101010101) is output to the output terminals (R _9- R ₀ ) of the ROM (ROM ₁ ) as shown in FIG. 10 bit data code word signal of the output terminal is outputted to the (OUT ₀ -OUT ₉₎ in addition, the parity generator (PG ₁₎ input terminal is inputted to the (I ₀ -I ₉₎ that is detected parity, the parity generator (PG ₁₎ of Since the 10-bit codeword signal (0101010101) inputted to the input terminal (I ₉ -I ₀ ) is odd parity, a high potential signal is outputted to the odd output terminal (odd) thereof, thereby inputting the input terminal (MI ₁ ) of the multiplexer (MUX ₁ ). In addition to common input to (MI ₄ ), a low potential signal is input to the input terminals (MI ₂ ), (MI ₃ ).

In this case, the 10-bit codeword signal (0101010101) output from the output terminals (R ₉ -R ₀ ) of the ROM (ROM ₁ ) is connected to the input terminals (P ₉ -P ₀ ) of the parallel / serial converter (PTSC ₁ ). It is input in parallel at the time of falling of the load control signal CS ₁ as shown in Fig. 4 (e) which is input and applied to its load terminal PL, and the parallel loaded signal is loaded in parallel / serial converter ( Ascending time of the clock signal CLK ₃ and the control signal CS ₂ as shown in FIGS. 4F and 4G applied to the clock terminal PCK ₁ and the control terminal CIN of the PTSC ₁ ). As shown in (m) of FIG. 4 at the time of the fall of, it is converted in series and output to the output terminal So of the parallel / serial converter PTSC ₁ , and the output signal (0101010101) is converted into the NRZI converter (NRZIC _1). ) input terminal (NI) is input to a clock signal (CLK ₃₎ and a control signal (CS ₂₎ as shown in the fourth degree (i) is applied to its clock terminal (NCK ₁₎ exclusive of Ahkeyiteu is NRZI conversion as shown in the fourth degree (j) at the falling point of the signal output through the (EXOR ₁₎ is output to the output terminal (No) of the NRZI converter (NRZIC _1), that the output signal is 2 The high voltage of the control signal CS ₃ as shown in FIG. 4 (k) applied to the up / down input terminal U / D of the up / down counter BUDC ₁ and applied to its load terminal LD. As shown in (i) of FIG. 4, the reference signal 10000 ₂ input to its reference signal input terminals V ₄ -V ₀ is loaded in the above signal section and then applied to its clock terminal CCK ₁ . The low potential signal portion of the signal as shown in FIG. 4 (j) applied to the up / down input terminal U / D of the binary up / down counter BUDC ₁ at the time of the falling of the same ten clock signals. Down counts from the loaded reference signal 10000 ₂ , and up counts from the high potential signal part, so that the up / down counter (BUDC ₁ ) When ten clock signals as shown in FIG. 4 (i) applied to the clock terminal CCK ₁ are completed, the counter BUDC ₁ stops counting, that is, from the reference signal 10000 ₂ , down and The values of repeated up counts cancel each other, resulting in a reference signal 10000 ₂ , and the reference signal 10000 ₂ is applied to the control terminal OE of the binary up / down counter BUDC ₁ . As shown in Fig. 1, a signal 10000 ₂ counted during the high potential signal of the control signal CS ₄ is output to the output terminals B ₄ -B ₀ as shown in Fig. 4m _. Since the output counted signal 10000 ₂ is applied to the comparison terminals C ₄ -C ₀ of the comparator COMP ₁ , the output signal 10000 ₂ is compared with the reference signal 10000 ₂ applied to the reference terminals V ₁₄ -V ₁₀ . because the comparison is equal to a comparator (COMP ₁₎ has its output terminal and the low potential signal to the output (CV ₀₎ digital sseomgap (DC) on, the digital sseomgap (DC) of the low-potential output signal Therefore it applied to the selection terminal (S ₁₎ (S ₂₎ of a multiplexer (MUX ₁₎ with the low potential signal outputted from the output terminal (Q ₁₎ of said flip-flop (FF _1), as shown in the sixth degree truth table The multiplexer MUX ₁ selects a high potential signal input to its input terminal MI ₁ and is input to the input terminal D of the flip-flop FF ₁ , and the input signal is a flip-flop FF ₁ . the address terminals of the clock terminal of claim is a high potential signal to the fourth degree (b) an output terminal (Q ₁₎ by a clock signal (CLK ₁₎ as shown in the output ROM (ROM ₁₎ applied to the (DCK ₁₎ (A ₈ ) is applied as the digital thumb value (DC) information signal Q 'of the previous code, and thus the ROM (ROM ₁ ) is applied to its clock terminal (RCK ₁ ) as shown in FIG. As shown in (d) of FIG. 4, the output terminal R ₉ -R ₀ of the ROM ROM ₁ at the time when the clock signal CLK ₂ rises as shown in FIG. 4 is a 10-bit conversion data codeword signal (0101010101). ) Is output, the digital thumb value DC of the low potential signal is output to the output terminal CV ₀ of the comparator COMP _{1 in the} same manner as described above, and the digital thumb value DC of the output low potential signal is Since it is applied to the selection terminal S ₁ (S ₂ ) of the multiplexer MUX ₁ together with the high potential signal output from the output terminal Q ₁ of the flip-flop FF ₁ , as shown in the truth table of FIG. 6. The multiplexer MUX ₁ selects a low potential signal input to its input terminal MI ₃ and inputs it to the input terminal D of the flip-flop FF ₁ , and the input signal is its clock terminal DCK _1. ), The low potential signal is output to the output terminal Q ₁ by the clock signal CLK ₁ as shown in FIG. 4 (b), and transferred to the address terminal A ₈ of the ROM ₁ . The digital thumb value (DC) information signal Q 'of the code is applied.

In this state, when the data signal 00000000 ₂ is input to the input terminals DI ₇ -DI ₀ as shown in FIG. 5A, the input data signal is input terminal D ₇ − of the latch LA ₁ . D ₀ ) is outputted to the output terminal L ₇ -L ₀ as the clock signal CLK ₁ as shown in FIG. 5B is applied to its clock terminal LCK ₁ , and the output signal is The digital thumb value (DC) of the previous code which is applied to the address terminals A _7- A ₀ of the ROM ₁ and simultaneously output from the output terminal Q of the flip-flop FF _{1 to the} address terminals A _{8 thereof} . Since the low potential signal of the information signal Q 'is applied, the ROM ROM ₁ is applied at the time when the clock signal CLK ₂ as shown in FIG. 5C is applied to its clock terminal RCK ₁ . ROM _1), the output terminal (R ₉ -R ₀₎ is converted to a code word signal (0101010111) of 10 bits is output as illustrated in FIG 5d, that the output signal of the 10-bit code word The output terminal is outputted to the (OUT ₀ -OUT ₉₎ In addition, the parity generator (PG ₁₎ at the input terminal is inputted to the (I ₀ -I ₉₎ parity detection that is, the input terminal of the parity generator (PG ₁₎ (I ₉ -I _Since the 10-bit data codeword signal (0101010111) input to ₀ ) is even parity, a high potential signal is outputted to its even output terminal (EVEN) to the input terminals (MI ₂ ) and (MI ₃ ) of the multiplexer (MUX ₁ ). In addition to the common input, a low potential signal is input to the input terminals MI ₁ and MI ₄ .

In this case, the 10-bit data codeword signal (01010101111) output from the output terminals R ₉ -R ₀ of the ROM (ROM ₁ ) is an input terminal P ₉ -P ₀ of the parallel / serial converter PTSC ₁ . Is loaded in parallel at the time of the falling of the load control signal CS ₁ as shown in FIG. 5E and applied to its load terminal PL, and the parallel loaded signal is loaded in parallel to the serial converter PTSC _1. 5f applied to the clock terminal PCK ₁ and the control terminal CIN of FIG. ₃ ) and the rising time of the clock signal CLK ₃ as shown in (g) and the falling time of the control signal CS ₂ . As shown in FIG. 5h, the signal is converted in series and output to the output terminal So of the parallel / serial converter PTSC ₁ , and the output signal 0101010111 is input to the input terminal NI of the NRZI converter NRZIC ₁ . type, so that its clock terminal (NCK ₁₎ the clock signal (CLK ₃₎ and a control signal (CS ₂₎ as shown in Fig. 5i claim applied to the exclusive Iowa K (EXOR ₁₎ as shown in claim 5j also on the falling time of the signal outputted through the NRZT is converted is output to the output terminal (No) of the NRZI converter (NRZIC _1), that the output signal is 2 jineop / down counter The reference signal in the high potential signal section of the control signal CS ₃ as shown in FIG. 5k applied to the up / down input terminal U / D of BUDC ₁ and applied to the load terminal LD thereof. After the reference signal 10000 ₂ inputted to the input terminals V ₄ -V ₀ is loaded, the clock signal CCK ₁ is applied to the clock terminal CCK ₁ at the falling time of the ten clock signals as shown in FIG. In the low potential signal portion of the signal as shown in FIG. 5j applied to the up / down input terminal U / D of the binary up / down counter BUDC ₁ , it is down counted from the loaded reference signal 10000 ₂ . a, in the high-potential portion of the signal by the up-count two jineop / down counter being applied to the clock terminal (CCK ₁₎ of (BUDC ₁₎ When the 10 clock signal as shown in the first 5i also complete two jineop / down counter (BUDC ₁₎ stops the count that is, to the one repeating the down and the up-count from the reference signal (000 ₂₎ values cancel each other out Eventually, the reference signal 10000 ₂ becomes a value, and the reference signal 10000 ₂ is applied to the control terminal OE of the binary up / down counter BUDC ₁ as shown in FIG. The signal 10000 ₂ counted during the high potential signal of CS ₄ ) is output to the output terminals B ₄ -B ₀ as shown in FIG. 5m, and the output counted signal 10000 ₂ is output to the comparator ( COMP ₁₎ comparison terminal (C ₀ -C ₄₎ applied, so the reference terminal (V ₁₄ -V _10), so the same is compared with the applied reference signal (000 ₂₎ when the comparator (COMP ₁₎ has its output terminal to the ( CV ₀ ) outputs a low potential signal as a digital thumb value DC, and the digital thumb value DC of the output low potential signal is output of the flip-flop FF ₁ . Since it is applied to the selection terminal S ₁ (S ₂ ) of the multiplexer MUX ₁ together with the low potential signal output from the output terminal Q ₁ , the multiplexer MUX ₁ has its input as shown in the truth table of FIG. 6. The low potential signal input to the terminal MI ₁ is selected and input to the input terminal D of the flip-flop FF ₁ , and the input signal is input to the clock terminal DCK ₁ of the flip-flop FF ₁ . The low potential signal is output to the output terminal Q ₁ by the clock signal CLK ₁ as shown in FIG. 5B, and the digital thumb value of the previous code is transmitted to the address terminal A ₈ of the ROM ROM ₁ . DC) is applied to the information signal Q '.

Accordingly, as described above, the modulation table of FIG. 2 can be obtained by repeating the same according to the data signal input to the input terminals DI _7- DI ₀ .

Then, the reference terminal of the comparator _{(COMP 1) (V 14 -V} 10) and the comparison output terminals (CV ₀ when the signal is not the same that is, a comparator (COMP ₁₎ applied to the (C ₀ -C ₄₎ In the case where the signal outputted from the output signal is not the low potential signal, the output terminal R ₉ of the ROM ₁ when the information signal Q 'of the digital thumb value DC of the previous code is the low potential signal as described above. If the 10-bit codeword signal output from -R ₀ ) is odd parity, the digital thumb value (DC) information signal (Q) low potential signal of the code output from the output terminal (Q ₁ ) of the flip-flop (FF ₁ ) is even. If it is parity, a high potential signal is output, and in contrast to the above, when the digital thumb value (DC) information signal Q 'of the previous code is a high potential signal, it is output from the output terminals R ₉ -R ₀ of the ROM ₁ . a 10-bit code word signal is odd parity, the flip-flop (FF ₁₎ an output terminal (Q ₁₎ digital code sseomgap (DC) of the information outputted from the No. (Q) is the even parity of the high potential signal, and outputs a low potential signal.

As described above, the present invention has the effect of converting 8-bit input data into 10-bit according to the 8-10-bit modulation table of the digital audio tape recorder with the configuration of the 8-10-bit modulation circuit of the digital audio tape recorder. .

Claims (2)

The output signal of the input terminal is to be connected to a data latch (LA ₁₎ are temporarily stored and output by the data signal input to the clock signal (CLK ₁₎ to ₍₇ DI -DI _0), and the data latch (LA ₁₎ And the output signal of the flip-flop (FF ₁ ) are applied to the ROM (ROM ₁ ) which outputs the 10-bit codeword signal as an address signal, and the 10-bit codeword output signal of the ROM (ROM ₁ ) is output terminal ( OUT ₉ -OUT ₀ ), and connected to the parity generator (PG ₁ ) to be applied as a parity check signal, and the output signal of the ROM (ROM ₁ ) is connected to the parallel / serial converter (PTSC ₁ ), EX Parallel / which is the input side of the digital thumb generating circuit (1) consisting of an NRZT converter (NRZIC), a binary up / down counter (BUDC ₁ ), and a comparator (COMP ₁ ) under the control of the output signal of the exclusive oracle (EXOR ₁ ). the output of the serial converter (PTSC ₁₎ and connected to be applied in parallel a code word signal, the parity generator (PG ₁₎ Shin It is the input signal to selectively selected by the flip-flop (FF ₁₎ via a multiplexer (MUX ₁₎ according to the output signal on the output side of the comparator (COMP ₁₎ and the flip-flop (FF ₁₎ of the digital thumb generating circuit (1) An 8-10 bit modulation circuit of a digital audio tape recorder, characterized in that it is connected and applied. The digital thumb generating circuit 1 loads the 10-bit codeword signal of the ROM ₁ according to the load control signal CS ₁ , and then the control signal CS ₂ and the clock signal CLK. ₃ ) the output signal of the parallel / serial converter (PTSC ₁ ) for converting to serial data is applied to the NRZI converter (NRZIC ₁ ) for converting the NRZI according to the clock signal through the exclusive oracle (EXOR ₁ ). The output signal of the NRZI converter NRZIC ₁ is loaded with a reference signal by a control signal CS ₃ , and then up / down counted according to a clock signal through an exclusive oracle EXOR ₁ to control the signal. CS ₄ ) is connected to the binary up / down counter BUDC ₁ for outputting the counted result, and the output signal of the binary up / down counter BUDC ₁ is compared with the reference signal COMP _1. Digital audio, characterized in that the connection to be applied as a comparison signal) 8-10 bit modulation circuit of tape recorder.

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