JPS60128721A - Variable length encoding and decoding system - Google Patents

Abstract

PURPOSE:To reduce the number of shift registers for code word of an encoding circuit and the number of shift registers for data word of a decoding circuit by premising an inversion processing at the time when a code word string is changed from ''0'' to ''1'' and constituting a counter of a variable frequency divider, which divides this string to data words, with one flip-flop. CONSTITUTION:An inputted binary data string is inputted from a terminal 51 to a two-stage shift register 52 successively, and the Q output of the second stage of the shift register 52 is inputted to a two-stage shift register 54 through an NAND circuit 53. A code bit C0 operated in accordance with the state of a counter 65 and data set to shift registers 52 and 54 is stored in a D flip-flop 64 and is inputted to the clock terminal of a D flip-flop 68, where the D terminal and the Q terminal are connected, thereafter and is subjected to the inversion processing at the time, when it is changed from ''0'' to ''1'', to obtain a recording signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sequential encoding circuit and a sequential decoding circuit using an encoding/decoding method for converting a binary digital data string into a signal sequence suitable for magnetic recording.

[Technical background of the invention and its problems] When attempting to record information represented by a binary digital data string on a magnetic recording medium such as a magnetic tape or a magnetic disk, the binary digital data string is not suitable for magnetic recording. The signal sequence is then converted into a signal sequence. For conversion and inverse conversion into such a signal sequence, that is, an encoding/decoding method, the present applicant first divides a data sequence into data words of 2 bits and 3 bits, and then converts each data word to 4 bits long. We also proposed a variable word length encoding/decoding method that converts codewords into 6-bit length codewords.

This variable length encoding/decoding method converts a binary data string into three types of 2-bit length data words selected from four types of 2-bit length data words and the 2-bit length data excluded from the above selection as the upper bits. Divide into two types of 3-bit length data words, and divide the above three types of 2-bit length data words into (1, 0, 0, 0L (0, 1, 0, 0), (0, 0, 1
, 0), and the two types of 3-bit length data words as (1, 0, 0).
0, 1, 0, 0>, (0, 0° 0.1, 0.0), respectively, and each data word separated into the binary data string is replaced with a code word. (1, 0, 1) in the converted codeword string is further converted to (0, 0, 1) to encode the data string, and the encoded data string is inversely transformed according to the above correspondence relationship and decoded. This is an encoding/decoding method. When recording on a magnetic recording medium, the recording signal is inverted at the sign (1) of the codeword string. Therefore, in the above variable length coding and decoding system, adjacent (
Since there are a minimum of 2 (0) and a maximum of 7 (0) between 1), when the period of the bit cell of the original binary data is T, the minimum inversion interval T77L in is 1.5T. 9. Maximum reversal interval T77! αX becomes 4T.

Table 1 is a conversion table showing an example of the correspondence between data words and code words in the variable length encoding/decoding method, FIG. 1 is an encoding circuit thereof, and FIG. 2 is a conventional example of a decoding circuit.

In the conversion table in Table 1, the code (η is a code that represents (1) only when the first bit of the next code word is (0). , O, 1).

Now, such encoding processing is performed as follows in FIG. The input binary data string is sequentially input from a terminal 11 to a three-stage shift register 12. This shift register 12 has a frequency fo given from the terminal 3.
It operates in response to the clock signal CKI. A
ND circuits 14, 15, 16 and NAND circuit 17
, 18, 19, the logic circuit includes data AI, A2 . Upon receiving the data word consisting of A3, the following calculations are performed in parallel: Pi = A1A2 + A2A3 P2 = A1A2 P3 = A1A2 P4:A1A2. In addition, in this logic [1 path, the above-mentioned (Y) is always calculated to be (1)0. On the other hand, in the parallel input shift register, the clock signal CK2 with the frequency 2fo input from the terminal 21 is used. Shift operation is performed in response to this. This shift register I receives the load signal at the 8/L terminal and outputs the data PI from the logic circuit.
, P2. P3. P4 is input in parallel, and (0) corresponding to serial input terminals 8IKPs and PeK is input. This load signal is generated by a counter n which inputs the clock signal CKI through an inverter n, and a separate NAND circuit which logically processes its output.The counter inputs the data P4 through an inverter 5. Thus, binary/ternary operation can be switched. In other words, the counter is configured to operate as a binary counter when P4 becomes (0) and as a ternary counter when it becomes (1). As a result, shift register 1
The upper 2 bits of the data set to 2 are (0, 1).

(1,,0), (1,1), the counter n operates in binary and outputs the output signal on the NAND circuits, and the code words PI, P2 . P3. P4 is loaded into register 20. Also, the data of the upper bits above is (
0, 0), the counter is 3 and over-operates, and the code words at that time are PI, P2 . P3. P4 is loaded into the register and Ps and Ps are connected to the serial input terminal (
0) is input. As a result, the C input binary data string is divided into 2-bit length data words or 3-bit length data words, and the divided data words are converted by the logic circuit into code words shown in the above correspondence relationship and shifted. Stored in a register. The code word input to this shift register is shifted to a period excluding the application period of the load signal according to the clock signal CK2. That is, if it is divided into 2-bit long data words, it will be shifted by 4 bits, and if it is divided into 2-bit long data words,
If divided into bit length data words, it is shifted by 6 bits. The output data Q from the shift register 1 and 2 is delayed through a 2-bit shift register % which operates in response to the clock signal (X2), and is ANDed.
In circuit n, AND is performed with the Q output of the shift register. As a result, the Q output data string from (1,0)20 becomes (1,0
, 1), it is converted to a data string (0, 0, 1). In other words, the value (1) above was tentatively determined (
The code is changed to (0) according to the code of the first bit of the next code word, that is, when the first bit of the next code word is (1), it is changed to (0) and output. As a result, the code word string S shown in the above-mentioned correspondence relationship is generated, set in the flip-flop Z, and outputted. still,
If the output of this flip-flop device is inputted to the clock input terminal of the fourth flip-flop whose D input terminal and Q output terminal are connected, the recording signal will be inverted each time the data of (1) is obtained. become.

Further, the decoding circuit shown in FIG. 2 performs decoding as follows. The restored codeword string is input from the input terminal 31, and the reproduced frequency zf is input from the terminal 32.
Parallel data Pt, P2 . P3. P4
These parallel data PI, P2. P3. P
4 by AND circuit style, logic consisting of 35.36] by 11 paths.

The data word is input to the shift register 37 as A1 ni P2·P4 A2=Px-P4 Aa=P1-P4. This shift register 37 has a counter blade and a NA
The load and shift operations are controlled by the ND circuit 39. That is, the counter blade inputs the reproduced clock signal via the inverter 40, divides the frequency by two in the first stage to reproduce a clock with a frequency of 10, and provides the clock as a shift clock to the shift register 37. In addition, the counter output is controlled to perform quaternary or hexadecimal operation by inputting the inverted data P4 of the data P4 to the second stage, and the NAND circuit 3
9 is used as a load signal to the shift register 37. That is, it is determined whether the data reproduced from the restored codeword string corresponds to a 2-bit length or a 3-bit length according to the value of P4, and the A1. Data A2 and A3 are stored in the shift register. When the data is 2 bits long, only the upper 2 bits are output, and when the data is 3 bits long, all 3 bits are output to reproduce the data word string.

However, conventional encoding circuits and decoding circuits that implement the variable length encoding/decoding method have the following problems. In conventional encoding circuits and decoding circuits, multiple-bit data words and code words are processed in parallel to convert and inversely transform them. must be stored in shift registers with multiple parallel inputs and then read out sequentially. This requires a shift register consisting of many D flip-flops, which increases the circuit scale when integrated. That is, there is a problem in that the number of gates increases when an integrated circuit is constructed.

[Object of the Invention] The present invention has been made in consideration of the above circumstances, and its purpose is to provide a circuit that can perform sequential encoding or decoding in the above-mentioned variable length encoding/decoding method. An object of the present invention is to provide a variable length encoding/decoding method that can realize a sequential encoding circuit and a sequential decoding circuit with a highly practical configuration that can be made small in scale.

[Summary of the Invention] The present invention provides a binary data string with three types of 2-bit length data words selected from four types of 2-bit length data, and the 2-bit length data excluded from the above selection as the upper bits. 2
Divided into 3-bit length data words of the above three types.
For bit-length data words, a code that becomes (1) only when the first bit of the next code word is (0) is (
Y), (1,0°0.0), (0,1,0,0)
, (0, 0, Y, O), respectively, and (1, 0, 0F 1 ) for the two types of 3-bit long data words.

0.0), (0,0,0,1,0,0,), respectively converting each data word into a code word to encode the binary data string; In addition, in the variable-length encoding/decoding method in which the encoded data string is inversely transformed and decoded according to the above-mentioned correspondence relationship, (0) of the code word string is encoded.
It is assumed that inversion processing is performed at the point when the value changes from Logic that stops the operation of the flip-flop 70 for a specific 3-bit length data word, and converts the sign of the 3rd bit of the data word according to the state of the flip-flop of the counter. By changing the circuit calculation algorithm, the binary data string can be sequentially converted into a codeword string.Furthermore, in the decoding of the variable length coding/decoding method, the codeword is converted into another code. After converting into words, the counter of the variable frequency divider for dividing into data words is set to one, and when a specific bit l' of the code word is +1 (1), that is, when it corresponds to a 3-bit length data word, the data word is By stopping the operation of the flip-flop 70 for one bit of the counter and changing the operation of the logic circuit for code conversion according to the state of the flip-flop of the counter, a binary data string is sequentially converted from the converted code word. This is a compressed version that can be decrypted.

[Effects of the Invention] Thus, the present invention provides a codeword shift register of an encoding circuit in the variable-length encoding/decoding system that divides a binary data string into 2-bit length data words and 3-bit length data words and performs code conversion. There are advantages such as the number of shift registers for data words in the decoding circuit can be reduced, the circuit scale is reduced, and the number of gates when integrated is small, making it highly practical.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings and a conversion table.

Table 2 (α) is a conversion table showing the correspondence between data words and code words used for code conversion in the encoding circuit of the present invention, and Table 2 (h) is a correspondence diagram showing the state of the counter with respect to the data words. , Table 2 (C) is a conversion table showing the correspondence between the converted data word and the code word at the time when one bit of data word has elapsed from the data word boundary, and Table 2 (d) is A diagram showing the correspondence of code pits sequentially output with respect to the state of the counter, FIG. 3 is an encoding circuit constructed by applying the present invention, and Table 3 (a) is a decoding circuit according to the present invention. Table 3 (Cb) is a conversion table showing the correspondence between data words used in "code conversion" in the circuit and the converted code words. FIG. 4, which is a diagram showing the correspondence of data sequentially output with respect to the states, is a decoding circuit constructed by applying the present invention.

Table 2 (α) Table 3 Cα) Code conversion into a codeword string in the encoding circuit of the present invention does not perform inversion processing where (1) of the encoded codeword string exists; Word string (
It is assumed that the inversion process is performed at the time of change from 0) to (1). That is, in the conversion table showing the correspondence between data words and code words in Table 2 (α),
(Y') represents a code that becomes (1) only when the first bit of the next code word is (0), as in Table 1,
(xl), (x2), and (x3) may have any sign of (0) or (1), and CX1 ) − (X2 ) + (
X3) does not change the recording signal that has been inverted.

Table 2 <h> is a diagram showing the state of the counter of the variable branch divider that determines the data word length for the data word. When the data word is 2 bits long, it is a 2-bit counter, and when the data word is 3 bits long, for example, if the correspondence is as shown in Table 2 (α), only in the case of A1 and A2-1, the period of 1 data bit is used. The counter operates as a 3-bit counter starting from 1E. Additionally, the third bit of a particular 3-bit long data word, in this embodiment a (0,0,0) data word, is delayed by a period of one bit from the time of the data word boundary, i.e. After the code bits of PI and P2 are outputted by sequential conversion to AI, they are converted from (0) to (1). Table 2 (C)
is a conversion table that shows the correspondence between data words and code words after such conversion.
-A'3 is expressed as A'3-A3+AlA2QB (1). In order to output code pits sequentially, PI,
If the code pit of P2 is outputted as P3 and P4 for A2 and P5 and P6 for A3, it will be converted into code bits sequentially. That is, code pit PI
, P3. Pls note number chord pit C1, chord pit P2. P4. When the even numbered code pit of P6 is represented by C2, a 2-bit long data word is input,
If the state of the counter is (0), the current data D1 to be converted is A1, the next data D2 is A2, the next data bit 5A3, and the next data D4 is A4, but the counter state is ( 1), the current data D1 is A2
, D2 is A3. D3 becomes A4 and D4 becomes A5. Also, if a 3-bit long data word is input and the counter state is initially (0), the current data Dl is AI%D2.
is A2, D3 is A3, D4 is A4, and if the counter state is the second (0), the current data Dl is A2, D
2 is N13, D3 is A4, and D4 is A5. If the state of the counter is (1), the current data D1 is A's,
D2 is A4, D3 becomes A5, and D4 becomes A6. Therefore, for the state of the counter, the output code (P) C
If I and C2 are considered from the conversion table of Table 2 (α) and (C), then (Xi), cx2), taking into account the existence of an arbitrary sign of (K3), as shown in Table 2 (Li') Become. At this time, the symbols (Xl) and (K2).

(K3) are both equal to 0')K. CKl is the clock signal of the data in which the first half T/2 of the period T of the bit cell of the input data is (1) and the second half T/2 is (0).
Then, the code pit Co to be output sequentially is Co
= CK1. (QA D1D2 +QAD2D3 +
QAD1D3 +DI, D2. D4)+CK1・QA
-D1D2...(2).

Such encoding processing is performed in the encoding circuit shown in FIG. 3 as follows. The input binary data string is input from the terminal 51 to the two-stage shift register 52 in order,
SHITON 2F 5520 2nd stage Q output is NAND circuit 5
The signal is further inputted to a two-stage shift register '54 via 3. These registers 52 and 54 operate in response to a clock signal CK1 of frequency f0 applied from terminal 55. NAND circuit 56, 57, 58, 59,
A logic circuit consisting of 60, 61 and an inverter 62 inputs the data DI set in the shift registers 52 and 54.
In response to D4 to D4, the operation 'n of equation (2) is performed, and the code pit C0 is stored in the D flip-flop 64 which operates in response to the clock signal CK2 of frequency 2fo input from the terminal 63.

- A counter 65 consisting of a D flip-prop operates in response to the clock signal CKI.
-1, the NAND circuit 66 and AND circuit 67 stop the operation of the counter 65 and shift
(1) is added to the output A3 of the second stage of the F5520 by the NAND circuit 53, the calculation of the above-mentioned equation (1) is performed, and the output A3 is shifted to the first stage of the shift register 54 as K3 at the next clock. In the shifted state, QA=1 but D2
= 0, the operation of the counter 65 stops only for one bit of data, resulting in a ternary operation. In this way, the state of the counter 65 and the shift register 52.
54 The code pit C0 calculated based on the K set data is input to the clock terminal of the D flip-flop 68 to which the Q terminal is connected to the trailing terminal stored in the D flip-flop 64, and is changed from (0) to (1). Inversion processing is performed at the point where K changes, and a recording signal is obtained.

Conversion into a data string in the decoding of the present invention involves converting the restored codeword into another codeword, successively converting the data bits from the converted codeword, and converting the data bit that is the fourth bit of the codeword. Using a marker bit indicating the length, one D-flip 70 block constitutes a ternary-operated counter, similar to the encoding circuit. In other words, from the conversion table of Table 1 showing the correspondence between original data words and code words, the code words are converted into the third
It is converted into the code words 1 to v6 shown in Table (α).

P'l to P's can be determined from Pt to P6 as follows.

Table 3 (h) is a diagram showing the state of the counter of the dipping frequency divider that determines the data word length similarly to the encoding circuit, and is the same as Table 2 (h) in the encoding circuit, so a description thereof will be omitted. However, the detection of a 3-bit long data word that stops the operation of the counter is controlled by the fourth code pit in the code word. In order to output data bits sequentially, K becomes A1 from P1' and P2' depending on the state of the counter.
, Ps', A2 from P4', Ps', Pa
It would be good if you could output A3 from '. PI with code word '
', Pa', P5' odd numbered code pits are CI, P2', P4', P6' even numbered code pits are 02. When the code pit 3 bits after C1 is expressed as C4, the output data pit (Do) for the state of the counter is considered from the conversion table in Table 3 (α).
Traps are required as shown in table (C). Therefore, the data bits Do that are sequentially output are D0=QB-C2.C4+QBC1 (4).

Such decoding processing is performed in the decoding circuit shown in FIG. 4 as follows. The restored codeword string is inputted from the input terminal 71, and is inputted from the two D flip-flops 75 and 76 via the inverter 73 and the NAND circuit 74 by the reproduced clock signal of frequency 1fo inputted from the terminal 72. The data is stored in a two-stage shift register, and the
The output is stored in a two-stage shift register composed of two D flip-flops 78 and 79 via a NAND circuit 77 to obtain parallel data P1 to P4.

NAND circuits 80, 81.8 from these Pl to P4
2, calculates P3' and Ps' in equation (3) above, inputs it to the D flip-flop 78 and the D flip-flop 75, and then inputs it to the D flip-flop 78 and the D flip-flop 75 at the next clock.
The contents of 9, 78, 76.75 are converted into P1 to P5. On the other hand, a counter 83 consisting of 70 flip-flops divides the frequency of the reproduced clock signal by two to generate a clock signal with a frequency of IO, and a counter 84 consisting of a D flip-flop operates upon receiving the clock signal with a frequency of 10.
4"" At 10 o'clock NAI'tl) Circuit 85 and AND
A circuit 86 stops the operation of the counter 84. When the next clock signal is input to the counter 84, the content of the D flip-flop 76 becomes P6 and P6' = Q, so the counter 84 only operates for one bit of data, and the counter 84 is in ternary form. It will take action. Sequential output data D0 is converted to the (4th ), the clock signal of frequency 2fo from the terminal 72 and the frequency f of the counter 83 are
A D flip-flop 91 has a clock signal inputted to its clock terminal via a N A N J) circuit 90.
is stored and output.

As explained above, according to the variable length encoding/decoding method using 2-bit length data words and 3-bit length data words according to the present invention, compared to conventional encoding circuits and decoding circuits, the variable length The counter of the frequency divider becomes simple, and the encoding circuit requires fewer shift registers for code words and the decoding circuit requires fewer shift registers for data words, resulting in a smaller circuit scale. For example, if the number of gates of a D flip-flop is 6 and we compare the number of gates with a conventional circuit, the encoding circuit in Figure 1 has approximately 100 gates, while the decoding circuit in Figure 2 has approximately 75 gates. According to the present invention, the encoding circuit of FIG. 3 has 52 gates, and the decoding circuit of FIG. 4 has 54 gates. Therefore, the encoding circuit and decoding circuit according to the present invention can perform sequential encoding and decoding, and the circuit size is reduced, which is a great practical advantage when integrated circuits are used.

Note that the present invention is not limited to the above-mentioned embodiments. For example, the selection of a 2-bit data word is performed by (0, 0), (
9,1) and (1,0), and the %3 bit length data word may be (1,1,0), (1,1,1), and other combinations are of course possible.

In addition, the method of setting the code word corresponding to each data word can be arbitrarily determined, and the key is to establish a one-to-one correspondence relationship.
It is sufficient to set it to . Then, the logical operation algorithm may be rearranged according to the correspondence relationship. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 shows a conventional encoding circuit, FIG. 2 shows a conventional decoding circuit, FIG. 3 shows an encoding circuit to which the present invention is applied, and FIG. 4 shows a decoding circuit to which the present invention is applied. 12.20.2+3.33.37.52, 54...shift register, 2:3. Hu, 65, 83, 84・
・Counter, 14, J5. l(i, 27.34.
35, 36.67, 86-=AND circuit, 17.
18, 19, 24, 39, 53, 56, 57, 58, 5
9,60,61゜66,74,77,80,8
1, 82, &5, 87, 88, 89, 9
0.=NAND circuit, 22, 25, 40.62, 7
3...(Mbaata, public, 29.64, 6B, 75
, 76.78, 79.91...D flip-flop. Agent: Patent attorney Kensuke Chika (and 1 other person) Figure 2 Figure 8

Claims (2)

[Claims] (1) The binary data string is composed of three types of 2-bit length data words selected from four types of 2-bit length data, and two types of 3-bit length data words whose upper bits are the 2-bit length data excluded from the above selection. For the three types of 2-bit length data words mentioned above, the code is (1) only when the first bit of the next code word is (0).
1) as (1, 0, (), 0). (0, 1, 0, 0), (0, 0, Y, 0), and the above two types of 3
For bit length data words (1,0,0,1°0
．． 0), (0, 0, 0, 1, 0, 0), convert each of the data words into code words to encode the binary data string, and encode the binary data string. In a variable-length encoding/decoding method in which a codeword string is inversely transformed according to the above-mentioned correspondence relationship, inversion processing is performed at the time when the codeword string changes from (0) to (1). On the premise of creating a recording signal, the three types of code words are (1, O, 0, O), (0, 1, Y, 0), (
0゜0, Y, 0) with the above two types of code words (1,
0,0゜1,Y,O), (0,0,0,1,Y,O), and the counter of the variable divider for dividing the word length is set to 3 bits when the data word length is 3 bits. The operation is stopped by one bit, and JillK of a specific 3-bit length data word is changed to the sign of the 3rd bit of the data word, thereby causing the counter to operate in ternary form. A variable length encoding/decoding system characterized in that the binary data 11 is sequentially converted into a code word string by changing the operation of a logic circuit for code conversion according to the state of the counter. (2) Among the three types of code words (0, 1, 0,
0) to (0, 1, 1, 0) (0, 0, Y, 0) to (0
, 0, 1, 0), and the above two types of code words are (1, 0, 0° 1.0, 0) converted into (1, 0, 1, 1, 1,
0) to (0,0,0,1,0,0) (0,0,1,1
. By changing the operation of the logic circuit that performs code conversion according to the state of