JPS6384209A - Sequential decoding circuit - Google Patents

Abstract

PURPOSE:To decrease gate number in integrating a small sized circuit by converting a 3-bit code bit into a 2-bit data bit, inputting it to output a code word string into a binary data string. CONSTITUTION:A decoding circuit is a sequential decoding circuit outputting two-bit data at each 3-bit of a code word string 3. The code word string is inputted to a DFF 10 synchronously with a clock B and a Q output is fed to a serial/parallel shift register 11 via an OR circuit 12. The output of the DFF 10 and the register 11 is loaded to a shift register 17 via OR circuits 13, 14 and an AND circuit 15 and a decode data output is obtained. In the code conversion, a 3-bit length and the 1st half 3-bit of a 6-bit code word are converted into a 2-bit data bit. The latter half 3-bit is converted into a 2-bit data bit by correcting the 5th bit in the sequential decoding circuit.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to a sequential encoding/decoding method for converting a binary digital data sequence into a signal sequence suitable for magnetic recording or optical recording. Regarding Decoding Circuit (Prior Art) When attempting to record information represented by a binary digital data string on a magnetic recording medium such as a magnetic tape or a magnetic disk, the binary digital data string is The conditions required for conversion into such a signal sequence are that as the magnetization reversal interval (recording wavelength) of the magnetic recording medium becomes shorter, interference from previous and subsequent magnetization reversals is reduced. As a result, the detection error increases.

(2) The minimum magnetization reversal interval is large, and (2) The detection window width for detecting recording viratora is large, and the magnetization reversal interval is larger than the period of the demodulation clock signal. However, since it is more difficult to generate a demodulating clock signal than a reproduction signal, the maximum magnetization reversal interval must be made smaller. These conditions are contradictory to ■■, and must be optimized to maximize the data recording density on the magnetic recording medium.・T
, Horiguchi and Morita's paper “An Optimiya-ti On of Mod
nlation Codes in Digit
lLl Recording's Engineering EEL
! : Transactions on Mag
netics, Vol. MAG-12°No.6.
Nov. 1976, P. 740, by converting a 2-bit unconstrained data word into a 3-bit constrained codeword, the minimum A code rate 2/3 encoding/decoding method is disclosed in which the number d is one and the maximum number k of .O's between adjacent "l"s is seven. However, the encoding/decoding method disclosed in the above paper is a variable length encoding/decoding method in which data words are 2-bit or 4-bit,69 and has the disadvantage that the apparatus for performing the conversion is complicated.

Japanese Unexamined Patent Publication No. 58-212248 discloses an encoding and decoding device that can sequentially perform conversion in the variable length encoding/decoding method. Table 1 shows a conversion table of the encoding/decoding method with a code rate of 2/3 adopted in the encoding device and the decoding device in the above patent.

Table 1 In Table 1, the left column labeled Data Word indicates the set of data bits separated from the data string, and the right column labeled Code Word indicates the corresponding set of converted code bits. There is. The converted codeword string is recorded on the magnetic recording medium as a magnetization reversal by inverting the recording signal at the code bit position of °11. The last bit of the word indicates the 11m or 10° bit and represents the complement of the previous bit.A decoding device for such an encoding system is shown in FIG. 0 second that can be realized with a circuit like
The decoding circuit shown in the figure is a sequential decoding circuit that outputs 2 bits of data for every 3 bits of the code word string. The single word string is synchronized with clock B,
It is input to a shift register 20 with serial input and parallel output, and is shifted by clock B.

The four stages of parallel outputs of the shift register 20 are code-converted by a logic circuit 21 consisting of AND circuits 211 to 213 and OR circuits 214 and 215, and are loaded in parallel to a parallel input shift register 23 operated by clock A and a load signal. The load operation of the 0 shift register 23 is performed by clock A when the load signal is at high level.
At the rising edge of the signal, output cams 1, B1, Ol of the logic circuit 21
, Di in parallel. When the load signal is at a low level, the shift register 23 performs a shift operation. The logic circuit 21 performs the code conversion shown in Table 1 and performs logical operations for decoding data words from code words, and sequentially converts every 3 code bits into 2 data bits, and A code C1 representing the word length for decoding, 6 bits,
In the case of a long code word, output 1 code D for storing the second code. C1 only when converting 1 bit to 2 bit data
= 1, Table 1 is stored as shown in Table 2 using data bits 01-1 two bits earlier, so C1-1, data bits Dl-1 two bits earlier, and code bit X,
Using Y, Z, W, data bits A1 and B1
Then, the code C1 representing the word length and the code bit D1 to be stored are calculated as follows. □C knee 1 and Di-1 are data bits and indicate the code 2 bits earlier, and when the load signal is high level, , C1 at the rising edge of clock A
-1 is stored in the B stage of the shift register 23, and Di-1 is stored in the 0 stage of the shift register 23. Therefore, the logic circuit 21 is a circuit for realizing the logical operation formula (1), and the AND circuit 211 ~213 and OR circuit 214.215'
By connecting like the logic circuit 21 in Fig. 2 to (
However, in the conventional decoding circuit shown in FIG. 2 which implements the decoding device of the encoding/decoding method shown in Table 1, the operation 1) is executed.

It requires an extra register to calculate and store the code representing the word long metal, and the scale of one circuit is extremely large (a) It has the drawbacks of being complex. (Problems to be solved by the invention) As mentioned above, If we try to implement this system as a circuit using the encoding/decoding system shown in Table 1.

In other words, code conversion as shown in Table 1 above had the drawback of being large and complex.

It could not be said that it was suitable for realizing the device. Therefore, the present invention has been made in consideration of the above circumstances, and its purpose is to provide a small sequential decoding circuit with a single circuit size that can be used in a decoding device in the variable length coding/decoding system. The objective is to provide an integrated circuit.

[Structure of the invention]

(Means for Solving the Problems) This invention stores a binary data string in four types of 2-bit lengths in one word (0,0”) (0,1) (1,0) (1,
Three types of 2-bit length data words excluding the (0.0) or (1,1) data word selected from 1) and the 2-bit length data (0,0) or (1) excluded from the selection.
, 1) are divided into four types of 4-bit length data, and the three types of 2-bit length data words are divided into three types of 3 types.
into bit length codewords.

The first and second pits of the data word correspond to the second and 8g3 bits of the code word, respectively, or are their complements, and the four types of 1-bit length data words are matched to the four types of 6-bit length. Convert a binary data string to a code word string by associating the data word with the third and fourth bits of the data word being the same as or complementing the second and sixth bits of the n code word, respectively. A variable-length sequential decoding circuit comprising: an input means into which a codeword string is input; code correction means for replacing the second bit of the 6-bit long code word, and data word and code sequentially for each 3-bit code bit of the n code word string inputted from the input means. Conversion circuit means converts 3-bit code bits into 2-bit data bits according to the correspondence relationship with words, and 2-bit data bits from this conversion circuit means are input, and the code word string is converted into a binary data string. 0 (Operation) The present invention is a sequential decoding circuit characterized by comprising an output means for outputting a binary data string t - (0.0) or ( 3 types of 2-bit length data words excluding the data words of 1 and 1) and 4 types of 4 types in which the upper bits are the 2-bit length data excluded from selection
into bit-length data words, such that the first and second bits of the three types of 2-bit length data words are the same as the second and third bits of the 3-bit length code word, respectively, or appear as complements. Furthermore, the third and fourth bits of the four types of 4-bit length data words are 1. 6 each
Is it the same as the second and sixth pits of the bit length code word?
0 and 0, which is a decoding circuit that converts a code word string used in a variable length encoding/decoding method into a data string so as to correspond to a complement number.

If the input code word is detected to be a 6-bit code word, the word length is changed by replacing the 5th bit of the 6-bit code word with the 2nd bit of the 6-bit code word. An embodiment of the present invention will be described below with reference to the drawings. Table 3 FIG. An example of a decoding circuit,
Basically D flip-flop 10. shift register 1
1. Table 3 is composed of OR circuit 12, 13, 14 AND circuit 15, 16 and parallel input shift register 17.
This is a conversion table showing the correspondence between code words and data words decoded by a decoding circuit. When decoding a 6-bit code word, first the first three
Along with converting a bit of code bits into 2 bits of data bits.

Figure 1 shows that after creating a modified codeword by replacing the 5th and 5th bits of the codeword with the 2nd bit, the latter 3 code bits are converted into 2 data bits. The decoding circuit is a sequential type decoding circuit that outputs a total of 2 bits of data for every 3 bits of the code word string,
Similar to the conventional example shown in FIG. 2, it operates in accordance with the control signal and clock signal waveforms and timing relationships shown in FIG. The code word sequence is synchronized with clock B and D7 rip 70 lub1.
A common input with clock B is input to 0, and its Q output is a serial input operated by clock B via an OR circuit 12.
It is added to the parallel output shift register 11. D7
The output of the lip-flop 10 and the output of the shift register 11
The parallel outputs of the stages are logically operated on data bits by OR circuits 13 and 14 and AND circuits 15, and loaded into a parallel input shift register 17 operated by clock A and a load signal.

If the word length of the codeword is 6 bits.

When the quad signal is high level, D7 lip 70 degrees F10
A specific pattern is detected from the output of the shift register 11 and the parallel output of the shift register 11, and the AND circuit 16 and the OR circuit 12
Accordingly, the WX2 bits of the 6-bit code word stored in the X stage of the shift register 11 become the 5th bit of the 6-bit code word stored in the W stage of the shift register 11.

The signal is input to two stages of the shift register 11 instead of the gate.

The load operation of the shift register 17 is performed by loading all logically operated data bits in parallel at the rising edge of clock A when the load signal is at a high level. When the load signal is at a low level, the shift register 17 performs a shift operation. Therefore.

The code conversion according to this embodiment converts the 3 code bits of the code word before being corrected into 2 data bits for the first 3 bits of the 3-pit length code word and the 6-bit length code word. It is detected that the code bits stored in the H, D flip-flop 10 and shift register 11 have a specific pattern for the latter three bits of the 6-bit code word, and the code bits of the 6-bit code word are From Table 3, the data bit Aj is a sequential decoding circuit in which the fifth pit is completely modified to convert the last three code bits of this modified code word into two data bits.

Bj, the input Zji of the shift register 11 for modifying the code word, and the load signal set to L, the calculation is performed as follows.

Therefore, the logical operation to execute equation (2) is to combine the A output of the D flip-flop 10 with the Y stage of the shift register 11 and the 2nd stage of the shift register 11.
The possible output of the stage is input to the AND circuit 15, and the AND circuit 15
The output of and the Q and output of the X stage of the shift register 11 are input to the OR circuit 13, and the output of the OR circuit 13 is set as kAj,
The output of the AND circuit 15 and the Q of the Y stage of the shift register 11
By inputting the output to the OR circuit 14 and making it the output tBj of the OR circuit 14.

While loading the shift register 17 in parallel, the Q output of the X stage, the available output of the Y stage, the available output of the 2nd stage, and the load signal are input to the AND circuit 16, and This can be done by inputting the Q output of the lip 70 to the OR circuit 12 and adding the output of the OR circuit 12 to the input of the shift register 11 as Zj.

That is, the decoding circuit of FIG. 1 modifies and decodes a 6-bit long code word.

Compared to conventional decoding circuits, the number of shift register stages can be reduced.

As explained above, the decoding circuit according to the present embodiment sequentially decodes 2 bits of data for every 3 code bits from the code word string using the modified code words shown in Table 3. Since a register for storing a code representing the word length, etc. can be made unnecessary, the configuration of the decoding circuit can be simplified.Therefore, its practical advantage is enormous.

Note that the present invention is not limited to the above embodiments. For example, it is of course possible to convert each bit of the code word string to its complement (invert the code word string) and then perform code conversion. From shift register 11 to AND circuit 15.16. Q connected to the OR circuits 12 to 14, the output and the available output are exchanged, and the AND circuit 16'? It is sufficient to use a NAND circuit and the OR circuit 12 as a NOR circuit ◎Also, to perform the logical operation of equation (2), a combination of an AND circuit and an OR circuit was used, but it is better to use a combination of a NAND circuit or a NOR circuit. But, of course, this is a good thing, as long as the correspondence between code words and data words in Table 3 corresponds to data bits converted to their complements.

It is sufficient to invert the output of the decoding circuit shown in Figure 8g1.

In short, the present invention can be implemented with various modifications without departing from the gist thereof◎ [Effects of the Invention] According to the present invention, it is possible to omit all the registers that store codes representing the word length of the decoding circuit. Since the scale of one circuit is reduced and the number of gates to be integrated can be reduced, it is extremely practical.

[Brief explanation of the drawing]

Figure K1 shows a decoding circuit that is an embodiment of the present invention, Figure 2 shows a conventional decoding circuit, and Figure 3 shows a conventional decoding circuit and a decoding circuit that is an embodiment of the present invention. Schematic diagram of waveforms and timing of clock and control signals 0 10...D flip-flop, 11.20... serial input parallel output shift register, 12.13.1
4.214.215...OR circuit, 15.16.21
1.212.213...AND circuit.

Claims (1)

[Claims] The binary data string is selected from four types of 2-bit length data words. Divided into three types of 2-bit length data words excluding the (0, 0) or (1, 1) data words, and four types of 4-bit length data with the upper bits of the 2-bit length data excluded from the selection. , 2 of the above three types
Corresponding bit-length data words to three types of 3-bit length code foods such that the first and second bits of the data words are the same as or the complements of the second and third bits of the code word, respectively, and Four types of 4-bit length data words correspond to four types of 6-bit length data words such that the third and fourth bits of the data words are the same as or the complements of the second and sixth bits of the code word, respectively. a variable-length sequential decoding circuit for converting the binary data string into a codeword string, the circuit comprising: an input means into which the codeword string is input; and a variable length sequential decoding circuit that converts the binary data string into a codeword string; sign correction means for replacing the fifth bit of the 6-bit code word with the second bit of the 6-bit code word when a bit-length code word is detected; and the code word string input from the input means. converting circuit means for successively converting the three code bits into two data bits in accordance with the correspondence between the data words and the code words for each of the three code bits; 1. A sequential decoding circuit comprising output means for inputting data bits, converting the code word string into the binary data string, and outputting the binary data string.