JPS6146975B2 - - Google Patents
Info
- Publication number
- JPS6146975B2 JPS6146975B2 JP54003250A JP325079A JPS6146975B2 JP S6146975 B2 JPS6146975 B2 JP S6146975B2 JP 54003250 A JP54003250 A JP 54003250A JP 325079 A JP325079 A JP 325079A JP S6146975 B2 JPS6146975 B2 JP S6146975B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor
- wall member
- integrated circuit
- external leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011810 insulating material Substances 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子を収納する半導体容器の構
造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor container that houses a semiconductor element.
各種の半導体素子を収納し、それら半導体素子
の電極と外部回路とを接続するための外部リード
を有する半導体容器には、各種の形状のものが開
発され、実用化されているが、マイクロ波帯、特
に数GHz以上の周波数帯域で使用されるものに
ついては、外部リードに特性インピーダンスをも
たせた所謂ストリツプライン形の半導体容器が圧
倒的に多い。 Semiconductor containers of various shapes have been developed and put into practical use as semiconductor containers that house various semiconductor devices and have external leads for connecting the electrodes of these semiconductor devices and external circuits. In particular, for those used in frequency bands of several GHz or higher, there are overwhelmingly many so-called stripline type semiconductor containers in which the external leads have characteristic impedance.
すなわち、セラミツク基板上の壁部材に外部リ
ードに特性インピーダンスを持たせるためにガラ
ス等の絶縁材を接着剤として外部リードを埋め込
み、この外部リードとセラミツク基板上にロウ着
された半導体素子の電極とを金属細線で電気的に
接続してその後金属の蓋部材で気密封止を行なつ
ていた。セラミツク基板の裏面には接地電位を印
加する金属層が形成されている。 That is, the external leads are embedded in a wall member on a ceramic substrate using an insulating material such as glass as an adhesive in order to give the external leads a characteristic impedance, and the external leads are connected to the electrodes of the semiconductor element brazed on the ceramic substrate. They were electrically connected using thin metal wires and then hermetically sealed with a metal lid member. A metal layer to which a ground potential is applied is formed on the back surface of the ceramic substrate.
しかしながら、このような半導体容器ではセラ
ミツク基板の裏面の金属層を接地面として使用す
るとしても、外部リード間には壁部材と絶縁材の
容量が接続された構造になるため数十GHz以上
の超高周波帯域での使用は困難なものであつた。 However, in such a semiconductor container, even if the metal layer on the back side of the ceramic substrate is used as a ground plane, the capacitance of the wall member and the insulating material are connected between the external leads, so It was difficult to use it in high frequency bands.
こうした問題点を解決するため第１図に示すよ
うな半導体容器が提案されている。すなわち、金
属基板１３上にこれと同じ金属ブロツク１１を取
りつけ、信号入出力部分のみ特性インピーダンス
となる大きさに絶縁体２０と外部リード１４，１
４′を備えている。金属ブロツク１１の上端には
蓋部材１８がロウ材９によつて接着されている。
このような半導体容器は一般に混成集積回路装置
用に使用されている。すなわち、金属基板１３上
には集積回路が形成されている集積回路基板１２
および半導体素子１７の放熱のための放熱板４０
が接着されている。半導体素子１７は放熱板４０
の上に固着され、集積回路基板１２上の集積回路
の所定の部分に金属細線１５と電気的に接続され
ている。外部リード４，４′もまた集積回路の所
定の部分と金属細線１５′と電気的に接続されて
いる。 In order to solve these problems, a semiconductor container as shown in FIG. 1 has been proposed. That is, the same metal block 11 is mounted on the metal substrate 13, and the insulator 20 and external leads 14, 1 are set to a size such that only the signal input/output portion has a characteristic impedance.
4'. A lid member 18 is bonded to the upper end of the metal block 11 with a brazing material 9.
Such semiconductor containers are commonly used for hybrid integrated circuit devices. That is, an integrated circuit board 12 on which an integrated circuit is formed is formed on a metal substrate 13.
and a heat sink 40 for heat radiation of the semiconductor element 17
is glued. The semiconductor element 17 is a heat sink 40
and is electrically connected to a predetermined portion of the integrated circuit on the integrated circuit board 12 with a thin metal wire 15 . The external leads 4, 4' are also electrically connected to predetermined portions of the integrated circuit and the thin metal wires 15'.
第１図の半導体容器では金属基板１３を接地し
て使用した場合、金属ブロツク１１も接地状態に
あるため外部リード１４，１４′間に存在する容
量は極めて小さくなり超高周波帯域でも使用でき
るようになる。しかし、特に特性インピーダンス
を構成する絶縁体２０と金属ブロツク１１の熱膨
腸係数の違いにより、絶縁体１０に亀裂が発生し
て気密性に劣るという新たな欠点が生じていた。 When the semiconductor container shown in FIG. 1 is used with the metal substrate 13 grounded, the metal block 11 is also grounded, so the capacitance existing between the external leads 14 and 14' is extremely small, making it possible to use it even in ultra-high frequency bands. Become. However, due to the difference in thermal expansion coefficient between the insulator 20 and the metal block 11, which constitute the characteristic impedance, a new drawback has arisen in that cracks occur in the insulator 10, resulting in poor airtightness.
本発明の目的は数十GHz以上の超高周波帯域
に於いてでも使用でき、また気密性に優れた半導
体容器を提供することにある。 An object of the present invention is to provide a semiconductor container that can be used even in an ultra-high frequency band of several tens of GHz or more and has excellent airtightness.
本発明によれば金属基板上に絶縁物で形成され
た壁部材を有しかつその壁部材を貫通して設けら
れた外部リードを有する半導体容器で、外部リー
ド部分の領域を除く半導体容器の内部表面が金属
で覆われていることを特徴とする半導体容器を提
供する。 According to the present invention, there is provided a semiconductor container having a wall member formed of an insulator on a metal substrate and an external lead provided through the wall member, the interior of the semiconductor container excluding the area of the external lead portion. To provide a semiconductor container whose surface is covered with metal.
次に本発明の実施例を図面を用いてより詳細に
説明する。 Next, embodiments of the present invention will be described in more detail with reference to the drawings.
第２図は本発明の一実施例を示す半導体容器の
断面図である。即ち、金属基板２３上にロー付等
の方法でセラミツクの壁部材２６を固定する。外
部リード２４，２４′に特性インピーダンスを持
たせるためガラス等の絶縁材５０を壁部材２６の
中に形成し、その時外部リード２４，２４′を同
時にうめ込んで固定する。このようにして形成さ
れた壁部材２６の内部の外部リード２４，２４′
を除く部分全面に金等の金属を付着して金属層３
０を形成する。壁部材２６の上端にも金等の金属
を付着させて金属層３５を形成する。次に、上に
集積回路が形成されているセラミツク等の集積回
路基板２２と半導体素子２７の放熱のために銅の
ような熱伝導性のよい放熱板４１を接着する。半
導体素子２７は放熱板４１に固着され、半導体素
子２７の各々の電極は金属細線２５によつて集積
回路基板２２上の集積回路の所定の部分と電気的
に接続される。外部リード２４，２４′も集積回
路の所定の部分と金属細線２５によつて電気的に
接続されている。 FIG. 2 is a sectional view of a semiconductor container showing one embodiment of the present invention. That is, the ceramic wall member 26 is fixed onto the metal substrate 23 by brazing or the like. In order to give the external leads 24, 24' a characteristic impedance, an insulating material 50 such as glass is formed in the wall member 26, and at that time, the external leads 24, 24' are simultaneously embedded and fixed. External leads 24, 24' inside the wall member 26 thus formed
Metal layer 3 is formed by attaching metal such as gold to the entire surface except for
form 0. A metal layer 35 is formed by depositing metal such as gold on the upper end of the wall member 26 as well. Next, a heat dissipation plate 41 made of copper or the like having good thermal conductivity is bonded to the integrated circuit substrate 22 made of ceramic or the like on which an integrated circuit is formed and for heat dissipation of the semiconductor element 27 . The semiconductor element 27 is fixed to a heat sink 41, and each electrode of the semiconductor element 27 is electrically connected to a predetermined portion of the integrated circuit on the integrated circuit board 22 by a thin metal wire 25. The external leads 24, 24' are also electrically connected to predetermined portions of the integrated circuit by thin metal wires 25.
かかる本発明の一実施例の半導体容器では、壁
部材２６と絶縁材５０の熱膨脹率をほぼ等しくで
きるため第２図の従来の半導体容器で生じていた
金属ブロツク１１と絶縁材１０との熱膨脹率の差
異による亀裂がなくなり、気密性に優れた半導体
容器を得ることができる。また金属基板２３を接
地面として使用すれば、金属基板２３と金属層３
０とは電気的に連続しているため壁部も接地状態
にあり、従つて外部リード２４，２４′間の容量
を極めて小さくすることができ数十GHz以上の
超高周波帯域での使用も可能となる。 In the semiconductor container according to the embodiment of the present invention, the thermal expansion coefficients of the wall member 26 and the insulating material 50 can be made almost equal, so that the thermal expansion coefficients of the metal block 11 and the insulating material 10, which occur in the conventional semiconductor container shown in FIG. Cracks caused by differences in the temperature are eliminated, and a semiconductor container with excellent airtightness can be obtained. Moreover, if the metal substrate 23 is used as a ground plane, the metal substrate 23 and the metal layer 3
Since it is electrically continuous with 0, the wall is also in a grounded state, so the capacitance between the external leads 24 and 24' can be extremely small, and it can be used in ultra-high frequency bands of tens of GHz or higher. becomes.
以上のように本発明によれば超高周波帯域でも
使用可能であり、さらに気密性に優れた半導体容
器を提供しうる。 As described above, according to the present invention, it is possible to provide a semiconductor container that can be used even in an ultra-high frequency band and has excellent airtightness.
尚、壁部材２６や絶縁材５０等の材質は実施例
で示したものに限られる必要はなく、ただ壁部材
２６と絶縁材５０の熱膨脹等がなるべくなら同じ
材質のものが好ましい。また、金属層３０，３５
は別工程で形成したが、金属層３０を形成すると
きと同時に金属層３５を形成してもよい。 Note that the materials of the wall member 26, the insulating material 50, etc. are not limited to those shown in the embodiments, but it is preferable that the wall member 26 and the insulating material 50 are made of the same material if possible in terms of thermal expansion, etc. In addition, metal layers 30, 35
Although formed in a separate process, the metal layer 35 may be formed at the same time as the metal layer 30 is formed.
第１図は従来構造の半導体容器を示す断面図、
第２図は本発明の一実施例を示す半導体容器の断
面図である。
１３，２３……金属基板、１１……金属ブロツ
ク、１０，５０……絶縁材、１４，１４′，２
４，２４′……外部リード、１５，１５′，２５，
２５′……金属細線、１７，２７……半導体素
子、１９，２９……ロウ材、１８，２８……蓋部
材、１２，２２……集積回路基板、４０，４１…
……放熱板、３０，３５……金属層。
Figure 1 is a sectional view showing a semiconductor container with a conventional structure.
FIG. 2 is a sectional view of a semiconductor container showing one embodiment of the present invention. 13, 23... Metal substrate, 11... Metal block, 10, 50... Insulating material, 14, 14', 2
4, 24'...external lead, 15, 15', 25,
25'... Metal thin wire, 17, 27... Semiconductor element, 19, 29... Brazing material, 18, 28... Lid member, 12, 22... Integrated circuit board, 40, 41...
... Heat sink, 30, 35 ... Metal layer.
Claims (1)
し、且つ該壁部材を貫通して外部リードが設けら
れた半導体容器に於いて、前記外部リードの突出
部分を除く前記壁部材の内側全面が前記金属基板
に接続された金属層で被覆されていることを特徴
とする半導体容器。1. In a semiconductor container having a wall member made of an insulating material on a metal substrate and having an external lead penetrating the wall member, the inside of the wall member excluding the protruding portion of the external lead. A semiconductor container characterized in that the entire surface is covered with a metal layer connected to the metal substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP325079A JPS5595343A (en) | 1979-01-11 | 1979-01-11 | Container for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP325079A JPS5595343A (en) | 1979-01-11 | 1979-01-11 | Container for semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5595343A JPS5595343A (en) | 1980-07-19 |
| JPS6146975B2 true JPS6146975B2 (en) | 1986-10-16 |
Family
ID=11552207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP325079A Granted JPS5595343A (en) | 1979-01-11 | 1979-01-11 | Container for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5595343A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953001A (en) * | 1985-09-27 | 1990-08-28 | Raytheon Company | Semiconductor device package and packaging method |
| JPS62293624A (en) * | 1986-06-13 | 1987-12-21 | Nippon Telegr & Teleph Corp <Ntt> | Ic package |
| JPH0793392B2 (en) * | 1986-10-25 | 1995-10-09 | 新光電気工業株式会社 | Package for ultra high frequency devices |
| JPH0524399U (en) * | 1991-09-02 | 1993-03-30 | コクヨ株式会社 | Picture frame |
| JPH0846073A (en) * | 1994-07-28 | 1996-02-16 | Mitsubishi Electric Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5587461A (en) * | 1978-12-26 | 1980-07-02 | Fujitsu Ltd | Microwave integrated circuit package |
-
1979
- 1979-01-11 JP JP325079A patent/JPS5595343A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5587461A (en) * | 1978-12-26 | 1980-07-02 | Fujitsu Ltd | Microwave integrated circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5595343A (en) | 1980-07-19 |
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