JPS6146914B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a memory element.

The degree of integration of memory elements has increased with the advancement of technology, and in devices using memory elements, it is necessary to clear the information when the power is turned on.

Conventionally, since this type of memory element does not have an internal clearing function, clearing has been performed using an external control circuit (for example, firmware). As a result, there are disadvantages in that it is troublesome to control the updating of addresses for clearing, application of write enable pulses, etc., and that it takes time to perform control using firmware or the like to execute clearing.

In FIG. 1, which is a block diagram of a conventional memory element, 1 is a memory cell array, 2 is an address decoder and driver, 3, 5, 6, and 7 are AND gates, 4 is a driver, 8 is a NAND gate, and 101 is the address input signal, 1
08 is a data input signal, 115 is a data output signal, 117 is an enable signal, and 118 is a write enable signal.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology, and therefore, an object of the present invention is to provide a clear function inside the memory element, thereby eliminating the need for a clear control circuit that was conventionally required to be installed externally. lost,
Another object of the present invention is to provide a novel memory element that can shorten the clearing time.

The above-mentioned object of the present invention is to have a memory cell, a means for externally instructing an address for writing to or reading from the memory cell, a means for externally providing write data and write timing, and a means for externally providing write data and write timing. A writable and readable memory element having a means for externally instructing the start of clearing, a means for holding a state during clearing, a counter for giving an address of the memory cell during clearing, and a counter for providing an address of the memory cell during clearing. means for setting the output of the counter as the address of the memory cell in the clearing state and using an external address as the address of the memory cell when the clearing state is not in progress, and applying write pulses to the memory element at regular intervals in the clearing state. By means of a storage element with a clearing function, comprising: means for updating the counter; means for setting write data to a constant value in a clearing state; and means for outputting a clearing completion signal. achieved.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

An embodiment of the present invention is shown in FIG. In one embodiment of the present invention, as shown in FIG. 2, an external address input signal 101 and a counter 11 (described later) are input by a memory cell array 1, an address decoder and driver 2, and an output 104 of a flip-flop 12 (described later).
The address signal 102 in the clearing state where
a selector 10 that selects the address of the memory cell array 1 during clearing, a counter 1 that provides the address of the memory cell array
1. Flip-flop 1 that holds the state during clearing
2. An oscillator circuit that applies write pulses to the memory cell array 1 at regular intervals in the clearing state, a delay element 14 that takes the timing that participates in counting the addresses of the memory cell array 1, a driver 4, and gates 3, 15, 16, 17, 19,
20, NAND gate 8, OR gate 18, address input signal 101, data input signal 108, enable signal 117, write enable input signal 1
18, data output signal 115, clear instruction signal 1
Consists of 07.

Next, the functions and operations of the present invention will be explained in detail with reference to FIGS. 2 and 3. When clearing is to be performed, the clear instruction signal 107 is set to "1" to instruct the clearing operation of the memory element shown in FIG. 2. When the clear instruction signal 107 becomes "1", the flip-flop (hereinafter abbreviated as F/F) 1 which maintains the clearing state
2 is set and the counter 11 is reset. F/F12 is set and its output 1
When 04 becomes "1", the selector 10 selects the address signal 102 generated by the counter 11.
Figure 3 shows the clear instruction signal 107 and the signals 106,1.
As shown in the relationship shown in FIG. is input. The signal 120 input to the AND gate 17 is ANDed with the output of the AND gate 3, and the signal 110 becomes "1".
This becomes a write pulse and is input to the memory cell array 1, and the AND gate 16
is input. Output signal 10 of AND gate 16
9 is set to “0” by the back output signal 121 of F/F12
Therefore, data "0" by the output signal 109 is written to address 0 (FIG. 3) of the memory cell array 1 indicated by the counter 11. said address 0
When data "0" is written to the memory cell array 1, an Add1 instruction is issued to the counter 11 by the output signal 105 in which the signal 106 is delayed by the delay circuit 14, and "0" is written to the memory cell array 1 in sequence until the counter 11 overflows. 0'' is written. The counter 11 is configured to be able to specify all addresses of the memory cell array 1.
When overflows, "0" is written to all addresses of the memory cell array 1 (cleared). When the counter 11 overflows, the signal 103 becomes "1" and a clear completion signal 122 is output to the outside, and the AND gate 20 performs an AND with the signal 105, and then resets the F/F 12 to complete the clearing operation. .

As explained above, the present invention has the advantage that by configuring the memory element to have a clearing function, an external clearing control circuit can be eliminated and the clearing time can be shortened. Further according to the invention,
Since a means for outputting a clear completion signal to the outside is provided, there is no need to externally monitor whether or not clearing of the memory element is completed, and there is no need to provide a means for such monitoring. can get.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a conventional memory element, and FIG. 2 is a block configuration diagram showing an embodiment of the present invention.
FIG. 3 is an operation time chart. 1...Memory cell array, 2...Address decoder and driver, 3, 5, 6, 7, 15, 1
6, 17, 19, 20...and gate, 4...
Driver, 8...NAND gate, 10...Selector, 11...Counter, 12...Flip-flop, 13...Oscillation circuit, 14...Delay circuit, 18
...Orgate.

Claims (1)

[Claims] 1 having a memory cell, means for externally instructing an address for writing to or reading from the memory cell, means for externally providing write data and write timing, and means for outputting read data to the outside. A writable and readable memory element having a means for externally instructing the start of clearing, a means for holding a clearing state, a counter for giving an address of the memory cell during clearing, and an output of the counter in the clearing state. means to set the address of the memory cell as the address of the memory cell, and use an address from the outside as the address of the memory cell when not in the clearing state, means for applying write pulses to the memory element at regular intervals in the clearing state, 1. A memory element with a clearing function, comprising: means for updating; means for setting write data to a constant value in a clearing state; and means for outputting a clearing completion signal.