JPS6146547A - Data processor - Google Patents

Abstract

PURPOSE:To improve the flexibility of a single-chip microcomputer by allowing a user to changes freely addresses assigned to respective input/output ports. CONSTITUTION:An address register 1 in which an address is set so as to make input/output ports active selectively is provided corresponding to the input/output ports. A comparing circuit 2 compares an address supplied to a port with the address set in the register 1. When the both coincide with each other, a latch 4 or input buffer 5 is put in operation to output the signal on an internal bus BS2 to an input/output pin 3 and input data from the input/output pin 3. For the purpose, an optional address is set in the address register 1 and addresses assigned to the respective input/output ports are changed freely through a program.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing technique and a technique that is particularly effective when applied to a decoding method for an input/output port in a microcomputer. Concerning effective techniques for use in configuration.

[Background Art] FIG. 1 shows a block diagram of an 8-bit single-chip microcomputer (hereinafter referred to as a single-chip microcomputer). In other words, this single-chip microcontroller has a read-only memory ROM that stores the program that operates the system, a program counter PC that sequentially accesses the addresses of this memory ROM, and a program counter that decodes instructions read from the memory ROM. ALU(
An instruction decoder ID that forms signals that control the execution unit EXEC, etc., which consists of an arithmetic logic unit) and various registers, and a read/write function that stores the data necessary for program execution and the data obtained by program execution. The execution unit EXEC and memory RAM are connected to internal bus B.
They are connected to each other by s1 and BS2. The input/output ports PlyP2yP3, . . . are connected to the internal buses Bs1 and Bs2.

Regarding the configuration of the single-chip microcomputer mentioned above, for example, Hitachi, Ltd. published in September 1981 [Hitachi 4-bit 1-chip Microcomputer HM]
C840 Series User's Manual”, page 3, etc.

By the way, the conventional single chip with the above configuration
In the microcontroller, each input/output port P1yP2+P3
A unique address is assigned to each input/output port p, y, P2, P3, etc., and each input/output port p, y, P2, P3, etc. is operated by decoding the corresponding address output from the program memory ROM. It has become.

In other words, the input/output port addresses of conventional single-chip microcontrollers are determined by internal circuitry, and are determined by the user.

Therefore, in conventional single-chip microcontrollers, the addresses of the input/output ports are fixed, and the program and LSI (Large-Scale Integrated Circuit) are given to the user.
There was a disadvantage that the degree of freedom in the technology used was small.

[Object of the Invention] An object of the present invention is to provide a data processing technology that can increase the degree of freedom of a user's program and LSI usage technology in a single-chip microcomputer, and can improve its versatility.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, by comparing the address setting register (or RAM) that can arbitrarily set the address of the turnout port according to program instructions and the address set in this register with the address supplied to each input/output port, By providing a comparison circuit that outputs a selection drive signal when the two match, the user can freely change the address assigned to each input/output port, thereby improving the versatility of single-chip microcontrollers. This is to achieve the above purpose.

The present invention will be described in detail below along with examples.

[Embodiment] FIG. 2 shows an embodiment in which the present invention is applied to an input/output port of a single-chip microcomputer.

In this embodiment, an address register 1 for setting the address of the port corresponding to each input/output port;
An address comparison circuit 2 is provided which compares the address set in the address register 1 with the address supplied for selecting this port.

This address comparison circuit 2 includes, for example, exclusive NOR circuits G1 to Gn provided corresponding to the output of each bit of the address register 1, and the outputs of these exclusive NOR circuits G1 to Gn as input signals. N
AND circuit G, 0. It is composed of.

The above exclusive NOR circuit G1 to which the output of each bit of address register 1 is applied to one input terminal.
The other input terminal of Gn has a program memory ROM.
Each bit constituting the address written in the operand part of the instruction read from is input.

Therefore, the exclusive NOR circuit G1=Gn connects the output of address register I and the program memory ROM.
bit by bit, and if they match, the exclusive NOR circuit (G1 to Gn
) output becomes high level. When all bits of the supplied address and the set address in address register 1 completely match, all exclusive NOR circuits G,
~Gn output becomes high level. This allows the N.A.
The power of the ND circuit G circuit G1 changes from high level to low level, and is supplied to the three-power NOR circuit G20.

The other two input terminals of the three-man power NOR circuit G20 receive a control signal CP indicating the command output from the command decoder ID.
A system clock CLK output from a clock generator (not shown) is input. When all three input signals change to low level, the output of NOR circuit G2 changes from low level to high level, and this is applied as selection drive signal φS to internal bus Bs.
2 and the input/output pin 3.

As a result, one bit of the 4-bit data output from the execution unit EXEC or data memory RAM, etc. onto the internal bus Bsz is latched by the latch circuit 4 and output to the input/output pin 3. . Each input/output port has a number of latch circuits 4 corresponding to the number of internal data bits (for example, 4 bits in a 4-bit microcomputer).
are provided in parallel, and all of them are operated by the selection drive signal φS, and each bit of data placed on the internal path Bsz is taken in simultaneously in synchronization with the clock CLK.

Incidentally, when the latch circuit 4 is operated, the input buffer 5 connected to the same input/output pin 3 is set to a non-operating state by a control signal such as an inverted signal φS of the selection drive signal φS of the latch circuit 4. be made into

On the other hand, when the address supplied from the program memory ROM and the address set in address register 1 match, the control signal CP indicating the command supplied from the instruction decoder ID is set to a high level, for example, and the "input" is input. ″
When the command is issued, the output of the NOR circuit G20 is set to a low level, and the latch circuit 4 is operated to put the input/output pin 3 in a high impedance state. Also, at this time, the human buffer 5 outputs an inverted signal φS of the selection drive signal φS.
The input signal currently being supplied to the input/output pin 3 is taken in by a control signal such as
Output on top.

As explained above, according to this embodiment, there is an address register 1 for setting an address for selectively activating the input/output port corresponding to each input/output port.
The address supplied to this port is compared with the address set in the address register 1, and when the two match, the latch circuit 4 or the input buffer 5 is operated, and the address on the internal path Bsz is It outputs a signal to the input/output pin 3 and takes in data from the input/output pin 3 internally. Therefore, address register 1
By setting an arbitrary address to , you can freely change the address assigned to each input/output port using a program.

As a result, for example, by allocating the same address to a certain area in the data memory RAM and any one input/output port, data that enters a certain input/output port during system operation can be guaranteed. Putting it into a certain area in memory RAM, or conversely, when a certain area in memory RAM is accessed, it causes the data stored there to be output from a specific input/output pin. be able to. However, depending on the program, it is easy to arbitrarily change the correspondence between certain areas in the memory RAM and input/output ports during the execution of the program.

For example, when writing a program that reads data one after another from different input/output ports, in conventional systems it was necessary to create a program consisting of similar routines with different addresses for each input/output port. In contrast, according to the above embodiment, in such a case, the procedure for importing data from one outgoing port is made into a subroutine, and an instruction to change the address of the input/output port is inserted before or after execution of the subroutine. By doing so, you can use the same subroutine to read data from different input/output ports one after another. the result,
Another advantage is that the overall program can be made shorter.

In the above embodiment, a method of setting an address in address register 1 is, for example, by creating a new instruction that includes the address to be set in the operand part, and executing that instruction, for example, as shown by the broken line in FIG. Thus, the operand of the instruction can be placed on the internal path Bsz, and the address can be placed in the address register 1 in the desired input/output port via the internal bus Bs2.

Alternatively, use a register in the execution unit EXEC, put the address to be set in that register, output the address from that register onto the internal path Bsz, and transfer it to the address register in the desired input/output port. 1 may be incorporated.

In the above embodiment, a register is used as a means for setting the address of each input/output port, but the present invention is not limited to this. For example, a random access memory for storing the address may be provided. .

An address comparison circuit 2 that compares the address set in the address and the address supplied to each input/output port uses a plurality of exclusive NOR circuits G1 to Gn corresponding to each bit of the address and their outputs as input signals. NAND circuit G1. However, the type of logic gate circuit and the configuration of the comparison circuit are not limited thereto, and various modifications using arbitrary logic gate circuits can be easily considered.

[Effect] Address setting register (or RA
M) and a comparison circuit that compares the address set in this register with the address supplied to each input/output port and outputs a selection drive signal when the two match. The ability for users to freely change the addresses assigned to input/output ports increases the degree of freedom in user programs and LSI usage techniques in single-chip microcontrollers, thereby improving the versatility of single-chip microcontrollers. There is an effect.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, an address register or a dedicated random access memory is provided in order to set the address allocated to each input/output port, but these are omitted and the already provided data memory RAM is used. It is also possible to use

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a 4-bit single-chip microcomputer, which is the field of application that formed the background of the invention.
The invention is not limited to this, and can also be used for 8-bit single-chip microcontrollers.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an example of a conventional 4-bit single-chip microcomputer, and FIG. 2 is a circuit configuration diagram showing an example of the input/output port configuration of a single-chip microcomputer to which the present invention is applied. It is a diagram. ROM...read-only memory (program memory), PC...program counter, ID...
Instruction decoder, EXEC...execution unit, RAM
... Memory that can be read and written at any time (data memory), P, ~P3 ... Input/output port, Bsl, B
s2...internal bus, 1...address setting means (
address register), 2...address comparison circuit,
3...Input/output pin, 4...Latch circuit, 5...
...Input buffer Figure 1 Figure 2

Claims (1)

[Claims] 1. In a data processing device having a plurality of input/output ports, each input/output port being selectively operated according to an address, the addresses of the input/output ports can be arbitrarily set. In addition, an address comparison circuit is provided corresponding to each input/output port, and when the address supplied to the input/output port and a preset address are compared for selection, and they match, A data processing device characterized in that only a corresponding input/output port is selectively operated. 2. The address for selecting each input/output port above is
2. The data processing device according to claim 1, wherein the data processing device is configured to be set in an address setting register or memory provided corresponding to each input/output port.