JPS6146071B2 - - Google Patents

Info

Publication number
JPS6146071B2
JPS6146071B2 JP55056881A JP5688180A JPS6146071B2 JP S6146071 B2 JPS6146071 B2 JP S6146071B2 JP 55056881 A JP55056881 A JP 55056881A JP 5688180 A JP5688180 A JP 5688180A JP S6146071 B2 JPS6146071 B2 JP S6146071B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
semiconductor
region
conductivity type
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55056881A
Other languages
Japanese (ja)
Other versions
JPS56160079A (en
Inventor
Hisao Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP5688180A priority Critical patent/JPS56160079A/en
Publication of JPS56160079A publication Critical patent/JPS56160079A/en
Publication of JPS6146071B2 publication Critical patent/JPS6146071B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • H01L27/14654Blooming suppression

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Light Receiving Elements (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置、例えばフオトダイオード
のような半導体素子を共通の半導体基体上に近接
して配置することが望まれるような、例えばレー
ザービームスポツトの位置検出に用いられる検出
装置に係わる。
DETAILED DESCRIPTION OF THE INVENTION The present invention is useful for detecting the position of a laser beam spot in a semiconductor device, for example, where it is desired to arrange semiconductor elements such as photodiodes in close proximity on a common semiconductor substrate. Related to detection equipment.

例えばレーザービームスポツトの位置検出に用
いられる検出装置としての半導体装置は、第1図
に示すように共通の半導体基体1に例えば4個の
フオトダイオード2が分離領域7によつて分離さ
れて設けられ、レーザービームスポツトが正規の
位置にある状態では、第1図に鎖線bをもつて示
すように、4つのフオトダイオード2の例えば中
心にその中心があるように位置させ、互いに対角
位置にある2つのダイオード2の出力の夫々の和
をとり、これらの和の出力の互の差によつてビー
ムスポツトbのずれを検出するようになされる。
For example, a semiconductor device as a detection device used for detecting the position of a laser beam spot includes, for example, four photodiodes 2 separated by a separation region 7 on a common semiconductor substrate 1, as shown in FIG. , when the laser beam spot is in the normal position, the center of the four photodiodes 2 is positioned diagonally to each other, as shown by the chain line b in FIG. The outputs of the two diodes 2 are summed, and the deviation of the beam spot b is detected from the difference between the summed outputs.

このような半導体装置は第1図に示すように、
例えばN型の低比抵抗のシリコン半導体層4上
に、これと同導電型で、これに比し高比抵抗のシ
リコン半導体層5が設けられた半導体基体6が用
意され、この基体6の半導体層5の全厚さWに亘
る深さに、選択的拡散によつて基体6と同導電型
のN型の低比抵抗、すなわち高不純物濃度の分離
領域7が例えば十文字パターンに設けられ、この
分離領域7によつて分離された半導体層5の各部
分に、選択的拡散、イオン注入法等によつてP型
の高不純物濃度領域8が高濃度の分離領域7と離
間するように設けられて夫々ダイオード2が構成
される。9は各領域8にオーミツクに被着された
電極、10はレーザービームに対する反射防止膜
である。
As shown in FIG. 1, such a semiconductor device has
For example, a semiconductor substrate 6 is prepared in which a silicon semiconductor layer 5 of the same conductivity type and higher resistivity is provided on an N-type silicon semiconductor layer 4 of low resistivity. A low resistivity isolation region 7 of the N type of the same conductivity type as the substrate 6, that is, a high impurity concentration, is provided in the depth of the entire thickness W of the layer 5 by selective diffusion, for example, in a cross pattern. A P-type high impurity concentration region 8 is provided in each portion of the semiconductor layer 5 separated by the isolation region 7 by selective diffusion, ion implantation, etc. so as to be separated from the high concentration isolation region 7. diodes 2 are constructed respectively. Reference numeral 9 represents an electrode ohmicly applied to each region 8, and 10 represents an anti-reflection film for the laser beam.

このような構造による場合、半導体層5の厚さ
Wは、入射光の電気信号変換効率を高める上で、
或る厚さ、例えばこれがシリコンの場合、6000Å
の波長の光に対してはこの厚さWは10μm以上で
あることが必要となるので、この厚さWを横切る
深さをもつて分離領域7を拡散するためには、そ
の幅Dは一般にD2Wであることから大となつ
てしまう。その上、耐圧等の問題から領域8は、
高濃度の分離領域7に接することがないようにす
ることが要求されるものであるので、前述の幅D
に加えて更に領域7及び8間に必要な間隔lが存
在し、各素子2間の間隔は少くともD+2 lが
必要となる。そして、この間隔lは領域7及び8
を形成するための夫々の不純物の例えば選択的拡
散に際しての拡散マスクの窓あけのためのフオト
エツチングにおける各露光マスクの位置合せ相互
の誤差を勘案した距離を必要とする。したがつて
この構成によるダイオード2間の間隔は十分小さ
くすることができず、ビームスポツトに対して無
効部分が大となり、検出信号量が小さくなる。ま
た、上述の構成において仮りにその分離領域7の
幅Dを小とすれば、ダイオード2間のクロストー
クが問題となる。
In the case of such a structure, the thickness W of the semiconductor layer 5 is determined to improve the electrical signal conversion efficiency of incident light.
a certain thickness, for example 6000 Å if this is silicon
For light with a wavelength of It becomes big because it is D2W. Moreover, due to problems such as withstand voltage, region 8 is
Since it is required to avoid contact with the high concentration separation region 7, the above-mentioned width D
In addition to this, there is also a required spacing l between regions 7 and 8, and the spacing between each element 2 must be at least D+2 l. And this interval l is the area 7 and 8
For example, distances are required that take into account mutual errors in the alignment of each exposure mask during photoetching for opening a window in a diffusion mask during selective diffusion of each impurity to form a mask. Therefore, with this configuration, the distance between the diodes 2 cannot be made sufficiently small, and the ineffective portion with respect to the beam spot becomes large, resulting in a small amount of detected signal. Furthermore, in the above-described configuration, if the width D of the isolation region 7 is made small, crosstalk between the diodes 2 becomes a problem.

本発明においては、このような欠点を解消し、
半導体素子間の間隔、すなわちダイオード間の間
隔を十分小さくすることができ、しかもクロスト
ークを回避することのできる半導体装置を提供す
るものである。
In the present invention, these drawbacks are solved,
It is an object of the present invention to provide a semiconductor device that can sufficiently reduce the distance between semiconductor elements, that is, the distance between diodes, and can avoid crosstalk.

以下本発明を詳細に説明するに、第2図及び第
3図を参照して本発明を例えば上述したように共
通の半導体基体に複数のダイオードを形成してビ
ームスポツトの位置検出を行うような半導体装置
に適用する場合の一例をその理解を容易にするた
めにその製造方法の一例と共に説明しよう。
The present invention will be described in detail below with reference to FIGS. 2 and 3. For example, as described above, the present invention may be implemented by forming a plurality of diodes on a common semiconductor substrate to detect the position of a beam spot. An example of application to a semiconductor device will be explained together with an example of its manufacturing method to facilitate understanding.

本発明においては、第3図に示すように、1の
導電型の低比抵抗、すなわち高不純物濃度の半導
体層11、例えばN型のシリコンサブストレイト
上に、これと同導電型でこれに比し高比抵抗の第
1の半導体層12、例えばN型のシリコン層をエ
ピタキシヤル成長によつて形成する。そして、こ
の第1の半導体層12に例えば選択的拡散によつ
てこの半導体層12の全厚さに亘る深さをもつて
この半導体層12と同導電型を有し、これに比し
十分高い不純物濃度を有する分離領域13を例え
ば第1図で説明した分離領域7に対応して十文字
パターンに形成して、この領域13によつて半導
体層12を複数の部分12a例えば4個(図にお
いては2個のみが示されている)に分割する。更
に、この第1の半導体層12上にこれと同導電型
を有し、同様に低比抵抗の第2の半導体層14、
例えばN型のシリコン層をエピタキシヤル成長に
よつて形成する。そして、この第2の半導体層1
4の全表面に他の導電型の例えばP型の比較的高
濃度の領域15を例えば拡散法によつて形成す
る。このようにして形成された半導体基体16の
第1及び第2の各半導体層12及び16の各厚さ
W1及びW2はW1≫W2に選定される。
In the present invention, as shown in FIG. 3, a semiconductor layer 11 having a low resistivity of one conductivity type, that is, a high impurity concentration, is formed on a semiconductor layer 11 of the same conductivity type and having a high impurity concentration, for example, an N-type silicon substrate. A first semiconductor layer 12 having a high specific resistance, for example an N-type silicon layer, is formed by epitaxial growth. Then, by, for example, selective diffusion, the first semiconductor layer 12 is made to have a depth that spans the entire thickness of the semiconductor layer 12, has the same conductivity type as the semiconductor layer 12, and has a sufficiently high conductivity compared to the first semiconductor layer 12. An isolation region 13 having an impurity concentration is formed in a cross pattern corresponding to, for example, the isolation region 7 explained in FIG. (only two are shown). Further, on this first semiconductor layer 12, a second semiconductor layer 14 having the same conductivity type and also having a low specific resistance,
For example, an N-type silicon layer is formed by epitaxial growth. Then, this second semiconductor layer 1
A relatively high concentration region 15 of another conductivity type, eg, P type, is formed on the entire surface of 4 by, eg, a diffusion method. Each thickness of each of the first and second semiconductor layers 12 and 16 of the semiconductor substrate 16 formed in this way
W 1 and W 2 are selected such that W 1 >>W 2 .

そして、第4図に示すように、この基体16の
領域15とこれの下の第2の半導体層14との全
厚さを横切つて分離領域7上にこの分離領域7の
パターンに沿つて溝17を、例えばエツチングに
よつて形成し、この溝17によつて第2の半導体
層14と、領域15とを夫々複数の部分14a及
び15aに夫々分割する。ここに、第2の半導体
層16に対する分離手段としての分離溝17は、
分離領域13上にこの領域13の幅内に在るよう
に配置するが、ここに分離溝17の幅D2はでき
るだけ小に選定し、片や分離領域13の幅D1
これを十分大に選定するものであり、これがた
め、溝17の分離領域13に対する位置合せの裕
度は十分大にとり得る。
Then, as shown in FIG. 4, along the pattern of the isolation region 7, it is applied to the isolation region 7 across the entire thickness of the region 15 of the base body 16 and the second semiconductor layer 14 therebelow. A groove 17 is formed, for example, by etching, and the groove 17 divides the second semiconductor layer 14 and the region 15 into a plurality of portions 14a and 15a, respectively. Here, the separation trench 17 as a separation means for the second semiconductor layer 16 is
The width D 2 of the separation groove 17 is selected to be as small as possible, and the width D 1 of the separation area 13 is selected to be sufficiently large. Therefore, the tolerance for positioning the groove 17 with respect to the separation region 13 can be sufficiently large.

そして、基体16の領域15を有する表面に、
例えば分離溝17内を含んで光透過性と電気的絶
縁性を有する反射防止膜18を被着する。尚、1
9は領域15の夫々分割された部分15aにオー
ミツクに被着された各ダイオード素子の一方の電
極、図示の例ではアノード電極を示す。
Then, on the surface of the base body 16 having the region 15,
For example, an anti-reflection film 18 having optical transparency and electrical insulation is coated on the inside of the separation groove 17 . Furthermore, 1
Reference numeral 9 designates one electrode of each diode element ohmicly adhered to each divided portion 15a of the region 15, which is an anode electrode in the illustrated example.

上述したように本発明装置によれば共通の半導
体基体16に、夫々分離手段、すなわち分離領域
13と分離溝17によつて分割された領域15及
び半導体層14の各部分15a及び14a間に形
成されたPN接合jを有して成る複数の例えば4
個の半導体素子20、すなわちフオトダイオード
が分離形成される。
As described above, according to the device of the present invention, the regions 15 divided by the separating means, that is, the separating regions 13 and the separating grooves 17, and the regions 15a and 14a of the semiconductor layer 14 are formed on the common semiconductor substrate 16, respectively. For example, a plurality of 4
The semiconductor elements 20, ie, photodiodes, are formed separately.

そして、上述の本発明構成によれば、各半導体
素子、この例ではフオトダイオード20は、その
PN接合jを有する部分は幅ぜまの分離手段、例
えば溝17によつて分離されるので、互いに十分
近接して配置されるので、無効部分を小さくする
ことができ、例えば第1図に説明したレーザービ
ームのスポツト位置の検出においてその信号量を
十分大きくとることができる。そして、分離領域
13はPN接合jの分離、すなわち素子20の間
隔の設定に直接的に影響を及ぼすものではないの
でその幅D1を十分大に選定できるものであり、
これによつて素子20間のクロストークのおそれ
は回避でき、しかも、この幅D1を十分大に選定
できるのが故に、半導体層12の厚さW1も十分
大に選定できるので、素子20に入射するビーム
を効率良く吸収し、電気信号に変換させることが
できる。
According to the configuration of the present invention described above, each semiconductor element, in this example, the photodiode 20 is
Since the parts having the PN junctions j are separated by widthwise separating means, e.g. grooves 17, they are arranged sufficiently close to each other, so that the ineffective parts can be made small, for example as illustrated in FIG. In detecting the spot position of the laser beam, the signal amount can be made sufficiently large. Since the isolation region 13 does not directly affect the isolation of the PN junction j, that is, the setting of the spacing between the elements 20, its width D 1 can be selected to be sufficiently large.
This avoids the possibility of crosstalk between the elements 20, and since the width D 1 can be selected to be sufficiently large, the thickness W 1 of the semiconductor layer 12 can also be selected to be sufficiently large. It can efficiently absorb the incident beam and convert it into an electrical signal.

上述した例では、本発明を例えば4つのダイオ
ードが配列されたレーザービームの位置検出を行
う半導体装置に適用した場合であるが、共通の半
導体基体に複数の半導体素子を近接して配列する
ことが望まれる各種半導体装置に本発明を適用す
ることもできる。
In the example described above, the present invention is applied to a semiconductor device that detects the position of a laser beam in which four diodes are arranged, but it is possible to arrange a plurality of semiconductor elements close to each other on a common semiconductor substrate. The present invention can also be applied to various desired semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の略線的拡大平面
図、第2図はそのA−A線上の要部の拡大断面
図、第3図及び第4図は本発明による半導体装置
の一例の製造工程図である。 16は半導体基体、12及び14はその第1導
電型の第1及び第2の半導体層、13は分離領
域、17は分離溝、15は第2導電型の領域、2
0は半導体素子である。
FIG. 1 is a schematic enlarged plan view of a conventional semiconductor device, FIG. 2 is an enlarged cross-sectional view of the main part along line A-A, and FIGS. 3 and 4 are fabrication of an example of a semiconductor device according to the present invention. It is a process diagram. 16 is a semiconductor substrate; 12 and 14 are first and second semiconductor layers of the first conductivity type; 13 is an isolation region; 17 is an isolation trench; 15 is a region of a second conductivity type;
0 is a semiconductor element.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基体に第1導電型の第1の半導体層
と、これの上に形成されたこれと同導電型の第2
の半導体層とが設けられ、該第1及び第2の半導
体層を複数区域に分離する手段が設けられ、上記
第2の半導体層は上記第1の半導体層より小さい
間隔で分離され、上記第2の半導体層の表面に上
記第1の半導体層の分離手段から離隔した第2導
電型の領域が設けられて成る半導体装置。
1 A first semiconductor layer of a first conductivity type on a semiconductor substrate, and a second semiconductor layer of the same conductivity type formed thereon.
a semiconductor layer is provided, means is provided for separating the first and second semiconductor layers into a plurality of regions, the second semiconductor layer is separated by a smaller interval than the first semiconductor layer, and the second semiconductor layer is separated by a smaller interval than the first semiconductor layer; A semiconductor device comprising a second conductivity type region spaced apart from the separation means of the first semiconductor layer on the surface of the second semiconductor layer.
JP5688180A 1980-04-29 1980-04-29 Semiconductor device Granted JPS56160079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5688180A JPS56160079A (en) 1980-04-29 1980-04-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5688180A JPS56160079A (en) 1980-04-29 1980-04-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS56160079A JPS56160079A (en) 1981-12-09
JPS6146071B2 true JPS6146071B2 (en) 1986-10-11

Family

ID=13039751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5688180A Granted JPS56160079A (en) 1980-04-29 1980-04-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56160079A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106863A (en) * 1981-12-18 1983-06-25 Sanyo Electric Co Ltd Integration type semiconductor photo-receptor
JPH0644618B2 (en) * 1986-04-03 1994-06-08 日産自動車株式会社 Semiconductor light receiving device

Also Published As

Publication number Publication date
JPS56160079A (en) 1981-12-09

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