JP2001144278A - Light receiving element array - Google Patents
Light receiving element arrayInfo
- Publication number
- JP2001144278A JP2001144278A JP32200999A JP32200999A JP2001144278A JP 2001144278 A JP2001144278 A JP 2001144278A JP 32200999 A JP32200999 A JP 32200999A JP 32200999 A JP32200999 A JP 32200999A JP 2001144278 A JP2001144278 A JP 2001144278A
- Authority
- JP
- Japan
- Prior art keywords
- receiving element
- light receiving
- layer
- element array
- inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、受光素子アレイ、
特に、サイズおよびピッチを小さくすることができ、か
つ、受光素子間のクロストークを低減できる受光素子ア
レイに関する。The present invention relates to a light receiving element array,
In particular, the present invention relates to a light receiving element array capable of reducing the size and pitch and reducing crosstalk between light receiving elements.
【０００２】[0002]
【従来の技術】波長多重された光を分波して光のスペク
トルをモニタする光分波モジュールにおいて使用される
市販の受光素子アレイを図１に示す。受光素子アレイ
は、受光素子１０が直線状に配列されて構成されてお
り、各受光素子の電極は、交互に列両側のボンディング
パッド１２に接続されている。2. Description of the Related Art FIG. 1 shows a commercially available light receiving element array used in an optical demultiplexing module for demultiplexing wavelength-multiplexed light and monitoring the spectrum of the light. The light receiving element array includes light receiving elements 10 arranged in a straight line, and electrodes of each light receiving element are alternately connected to bonding pads 12 on both sides of the column.
【０００３】従来の受光素子アレイを構成する受光素子
は、拡散によりｐｎ接合を形成したｐｉｎ構造のフォト
ダイオードである。図２に、図１の受光素子アレイのＡ
−Ａ′線の部分拡大断面図を示す。ｎ−ＩｎＰ基板２０
上に、ｎ−ＩｎＰ層２２，ｉ−ＩｎＧａＡｓ層（光吸収
層）２４，ｎ−ＩｎＰ層（窓層）２６が積層され、ｎ−
ＩｎＰ層２６内にＺｎが拡散されてｐ型領域２８が形成
され、ｐｉｎフォトダイオードが作られる。この場合、
拡散は等方的であり横方向にもＺｎ拡散が進む。拡散長
は、ＩｎＰ内の拡散係数がＩｎＧａＡｓ内の拡散係数よ
りも大きいため、Ｚｎ拡散は、縦方向の拡散より横方向
の方が延びることとなる。したがって、このような従来
の拡散型受光素子アレイでは、素子間隔を小さくするこ
とには制限があり、５０μｍピッチ程度が限界となって
いる。図１には、５０μｍ寸法を図示している。A light receiving element constituting a conventional light receiving element array is a photodiode having a pin structure in which a pn junction is formed by diffusion. FIG. 2 shows A of the light receiving element array of FIG.
FIG. 4 shows a partially enlarged cross-sectional view taken along line -A ′. n-InP substrate 20
An n-InP layer 22, an i-InGaAs layer (light absorbing layer) 24, and an n-InP layer (window layer) 26 are stacked on top of each other.
Zn is diffused into the InP layer 26 to form a p-type region 28, thereby forming a pin photodiode. in this case,
Diffusion is isotropic, and Zn diffusion proceeds in the lateral direction. As for the diffusion length, the diffusion coefficient in InP is larger than the diffusion coefficient in InGaAs, so that the Zn diffusion extends in the horizontal direction more than in the vertical direction. Therefore, in such a conventional diffusion type light receiving element array, there is a limitation in reducing the element interval, and the pitch is about 50 μm. FIG. 1 illustrates a 50 μm dimension.
【０００４】[0004]
【発明が解決しようとする課題】従来の受光素子アレイ
の受光素子は、ｐｎ接合を形成するため拡散を用いてい
る。前述したように、拡散は等方的であるため、拡散深
さ（基板方向）以上に横方向（隣接素子方向）にも拡散
される。また、拡散フロント形状の問題から、窓層であ
る最上層の膜厚を薄くすることができない。さらに、窓
層と光吸収層では材料系が異なり、光吸収層に対し窓層
の拡散係数が大きいため、横方向の拡散長が縦方向の拡
散長より大きくなってしまう。The light receiving element of the conventional light receiving element array uses diffusion to form a pn junction. As described above, since the diffusion is isotropic, it is also diffused in the lateral direction (in the direction of the adjacent element) beyond the diffusion depth (in the direction of the substrate). Further, due to the problem of the diffusion front shape, the thickness of the uppermost layer, which is the window layer, cannot be reduced. Further, since the window layer and the light absorbing layer have different material systems, and the diffusion coefficient of the window layer is larger than that of the light absorbing layer, the diffusion length in the horizontal direction is larger than the diffusion length in the vertical direction.
【０００５】以上のことから、受光素子をアレイ状に並
べる際に、素子の間隔に制限がある。すなわち、素子間
をある一定以上狭くすることができない。したがって、
光分波モジュールでは、分波した後の光路長を長くする
必要があり、モジュールの小型化に制限が生ずる。[0005] As described above, when the light receiving elements are arranged in an array, there is a limit to the interval between the elements. That is, the distance between the elements cannot be made narrower than a certain value. Therefore,
In an optical demultiplexing module, it is necessary to increase the optical path length after demultiplexing, which limits the miniaturization of the module.
【０００６】以上のことから、従来の拡散型受光素子ア
レイは、高密度集積には不向きである。As described above, the conventional diffusion type light receiving element array is not suitable for high density integration.
【０００７】また、拡散型の受光素子の光吸収層は、素
子間で分離されていないため、光吸収により発生したキ
ャリアの横方向拡散により、キャリアは隣の受光素子へ
の移動が可能である。これが、隣の受光素子へのクロス
トークとなり、受光素子アレイの特性が劣化する。Further, since the light absorption layer of the diffusion type light receiving element is not separated between the elements, the carrier can move to the adjacent light receiving element due to the lateral diffusion of the carrier generated by the light absorption. . This causes crosstalk to an adjacent light receiving element, which degrades the characteristics of the light receiving element array.
【０００８】本発明の目的は、受光素子アレイのサイズ
およびピッチを小さくすることができ、かつ、隣接受光
素子へのクロストークを低減できる受光素子アレイを提
供することにある。An object of the present invention is to provide a light receiving element array which can reduce the size and pitch of the light receiving element array and reduce crosstalk to adjacent light receiving elements.
【０００９】[0009]
【課題を解決するための手段】前述したように、従来の
拡散型受光素子アレイの問題点は、受光素子の間隔に制
限があることであった。これは、ｐｎ接合をＺｎ拡散に
より形成しているためである。したがって、本発明では
ｐｎ接合を受光素子アレイ用エピタキシャルウェハの窓
層成膜時にｐ型となる材料をドーピングすることにより
作製し、かつ、受光素子間をエッチングにより分離する
ことによりメサ構造の受光素子アレイを形成する。これ
により受光素子アレイのサイズおよびピッチを小さくす
ることができる。As described above, the problem of the conventional diffusion type light receiving element array is that there is a limitation on the interval between the light receiving elements. This is because the pn junction is formed by Zn diffusion. Therefore, in the present invention, a pn junction is produced by doping a p-type material at the time of forming a window layer of an epitaxial wafer for a light-receiving element array, and the light-receiving elements are separated by etching to form a light-receiving element having a mesa structure. Form an array. Thereby, the size and pitch of the light receiving element array can be reduced.
【００１０】さらに受光素子間をエッチングにより除去
したメサ型構造を採用するので、素子間が分離独立し、
受光素子内での横方向へのキャリアの拡散がないので、
隣接受光素子へのクロストークを低減することができ
る。Further, since a mesa structure in which the light receiving elements are removed by etching is employed, the elements are separated and independent from each other.
Since there is no carrier diffusion in the lateral direction in the light receiving element,
Crosstalk to an adjacent light receiving element can be reduced.
【００１１】[0011]
【発明の実施の形態】図３は、本発明の受光素子アレイ
の第１の実施例の断面図である。受光素子を分離エッチ
ングしたメサ型構造の受光素子アレイであり、ｎ−Ｉｎ
Ｐ基板３０上に、ｎ−ＩｎＰ層３２，ｉ−ＩｎＧａＡｓ
層（光吸収層）３４，ｐ−ＩｎＰ層（窓層）３６が積層
され、ＩｎＧａＡｓ層３４とＩｎＰ層３６とをエッチン
グして素子間を分離して、絶縁膜３８を被覆し、各受光
素子のｐ−ＩｎＰ層３６上にはｐ型オーミック電極４０
を、ｎ−ＩｎＰ基板３０の裏面には共通のｎ型オーミッ
ク電極４２が形成されている。すなわち、受光素子はｐ
ｉｎ構造のフォトダイオードよりなる。FIG. 3 is a sectional view of a first embodiment of a light receiving element array according to the present invention. This is a light-receiving element array having a mesa structure in which the light-receiving elements are separately etched, and n-In
On a P substrate 30, an n-InP layer 32, i-InGaAs
A layer (light absorbing layer) 34 and a p-InP layer (window layer) 36 are laminated, the InGaAs layer 34 and the InP layer 36 are etched to separate the elements, and the insulating film 38 is covered. A p-type ohmic electrode 40 is formed on the p-InP layer 36 of FIG.
On the back surface of the n-InP substrate 30, a common n-type ohmic electrode 42 is formed. That is, the light receiving element is p
It consists of an in-structure photodiode.
【００１２】以上のような受光素子アレイは、次のよう
にして作製される。ｎ−ＩｎＰ基板３０上に、ＭＯＣＶ
Ｄ法等によりｎ−ＩｎＰ層３２，ｉ−ＩｎＧａＡｓ層３
４，ｐ−ＩｎＰ層３６を連続してエピタキシャル成長す
る。このとき２層目のｉ−ＩｎＧａＡｓはノンドープも
しくはわずかにドーピングされていてもよい。素子間の
エッチングにより、ｎ−ＩｎＰ層３２表面まで部分的に
露出させて分離溝を作りメサを形成する。メサ形成にお
いては、ＩｎＰおよびＩｎＧａＡｓとで選択性のあるエ
ッチング液を使用することにより、各層の境界でエッチ
ングを停止させることが容易となる。The light receiving element array as described above is manufactured as follows. MOCV on n-InP substrate 30
N-InP layer 32, i-InGaAs layer 3 by D method or the like
4. The p-InP layer 36 is continuously epitaxially grown. At this time, the second layer i-InGaAs may be non-doped or slightly doped. By etching between the elements, a separation groove is formed by partially exposing the surface of the n-InP layer 32 to form a mesa. In the formation of the mesa, by using an etchant having selectivity with InP and InGaAs, it becomes easy to stop the etching at the boundary of each layer.
【００１３】次に、最上層のｐ−ＩｎＰ層３６，および
エッチングにより表出させたｎ−ＩｎＰ層３２上に例え
ばＳｉＮよりなる絶縁膜３８成膜し、コンタクトホール
を設けてｐ−ＩｎＰ層３６上に例えばＡｕＺｎよりなる
ｐ型オーミック電極４０を形成する。また、ｎ−ＩｎＰ
基板３０の裏面に例えばＡｕＧｅＮｉよりなるｎ型オー
ミック電極４２を形成する。Next, an insulating film 38 made of, for example, SiN is formed on the uppermost p-InP layer 36 and the n-InP layer 32 exposed by etching, and a contact hole is provided to form the p-InP layer 36. A p-type ohmic electrode 40 made of, for example, AuZn is formed thereon. Also, n-InP
An n-type ohmic electrode 42 made of, for example, AuGeNi is formed on the back surface of the substrate 30.
【００１４】絶縁膜３８の成膜後、ボンディングパッド
を含めた配線が形成されるが、オーミック電極および配
線は、兼用が可能である。さらに、受光素子上部の絶縁
膜３８の膜厚を無反射条件にすることにより、デバイス
特性を向上させることができる。After the formation of the insulating film 38, a wiring including a bonding pad is formed. However, the ohmic electrode and the wiring can be shared. Furthermore, device characteristics can be improved by setting the thickness of the insulating film 38 above the light receiving element to a non-reflection condition.
【００１５】図４は、基板に半絶縁性（ＳＩ）基板であ
るＳＩ−ＩｎＰ基板を用いた受光素子アレイの第２の実
施例を示す。FIG. 4 shows a second embodiment of a light receiving element array using a semi-insulating (SI) substrate, an SI-InP substrate.
【００１６】ＳＩ−ＩｎＰ基板４４上に、第１の実施例
と同様に、ｎ−ＩｎＰ層３２，ｉ−ＩｎＧａＡｓ層３
４，ｐ−ＩｎＰ層３６をエピタキシャル成長させて積層
し、ＩｎＧａＡｓ層３４とＩｎＰ層３６とをエッチング
して溝を形成し素子間を分離して、絶縁膜３８を被覆
し、各受光素子のｐ−ＩｎＰ層３６上にはコンタクトホ
ールを開けてｐ型オーミック電極４０を形成している。
分離溝の底部の絶縁膜３８には、コンタクトホールを開
けて、各受光素子のｎ型電極４６を形成する。An n-InP layer 32 and an i-InGaAs layer 3 are formed on an SI-InP substrate 44 in the same manner as in the first embodiment.
4, the p-InP layer 36 is epitaxially grown and laminated, the InGaAs layer 34 and the InP layer 36 are etched to form a groove, the elements are separated, the insulating film 38 is covered, and the p- A p-type ohmic electrode 40 is formed on the InP layer 36 by opening a contact hole.
A contact hole is formed in the insulating film 38 at the bottom of the separation groove, and an n-type electrode 46 of each light receiving element is formed.
【００１７】以上の第１および第２の実施例によれば、
ｐｎ接合は結晶成長により形成するため、従来技術の拡
散に起因する問題がない。このため、受光素子アレイの
サイズおよびピッチを小さくすることができる。According to the first and second embodiments,
Since the pn junction is formed by crystal growth, there is no problem caused by diffusion in the related art. Therefore, the size and pitch of the light receiving element array can be reduced.
【００１８】また、隣の受光素子とはエッチングにより
分離するため、受光素子内での横方向へのキャリアの拡
散がない。したがって、隣接素子へのクロストークを低
減できる。Further, since the light receiving element is separated from the adjacent light receiving element by etching, there is no carrier diffusion in the lateral direction in the light receiving element. Therefore, crosstalk to an adjacent element can be reduced.
【００１９】図５は、エッチングにより除去された素子
間の部分を半導体材料を用いて埋め込むことにより、メ
サ界面に生ずるリーク電流を低減し受光素子アレイの低
暗電流化を実現した第３の実施例である受光素子アレイ
を示す。この受光素子アレイによれば、エッチング部分
は、半絶縁性ＩｎＰまたはアンドープＩｎＰが埋込まれ
る。FIG. 5 shows a third embodiment in which a portion between elements removed by etching is buried by using a semiconductor material to reduce a leak current generated at a mesa interface and to reduce a dark current of a light receiving element array. 1 shows an example of a light receiving element array. According to this light receiving element array, semi-insulating InP or undoped InP is embedded in the etched portion.
【００２０】このような受光素子アレイは、次のように
して作製される。ｎ−ＩｎＰ基板３０上にＭＯＣＶＤ法
等によりｎ−ＩｎＰ層３２，ｉ−ＩｎＧａＡｓ層３４，
ｐ−ＩｎＰ層３６を連続成長する。このとき２層目のｉ
−ＩｎＧａＡｓ層はノンドープもしくはわずかにドーピ
ングされていてもよい。エッチングにより、ｎ−ＩｎＰ
層表面まで部分的に表出させて分離溝を形成する。エッ
チングしていない部分を、例えばＳｉＮ膜，ＳｉＯ2 膜
などのマスク材（図示せず）で被覆し、再度ＭＯＣＶＤ
法等により半絶縁性ＩｎＰ（例えばＦｅドープ）もしく
はアンドープＩｎＰを分離溝部分にのみ選択的に再成長
させる。図には、成長したＩｎＰを５０で示す。その
後、マスク材を除去し、ｐ−ＩｎＰ層３６上にｐ型電極
（ＡｕＺｎ）４６を，ｎ−ＩｎＰ基板３０の裏面に共通
のｎ型電極（ＡｕＧｅＮｉ）４２を形成する。絶縁膜５
２の成膜後ボンディングパッドを含めた配線を形成す
る。Such a light receiving element array is manufactured as follows. On the n-InP substrate 30, an n-InP layer 32, an i-InGaAs layer 34,
The p-InP layer 36 is continuously grown. At this time, the second layer i
The -InGaAs layer may be non-doped or lightly doped. N-InP by etching
A separation groove is formed by partially exposing to the layer surface. An unetched portion is covered with a mask material (not shown) such as a SiN film or a SiO 2 film, and the MOCVD is performed again.
A semi-insulating InP (for example, Fe-doped) or undoped InP is selectively regrown only in the isolation trench portion by a method or the like. In the figure, the grown InP is indicated by 50. Thereafter, the mask material is removed, and a p-type electrode (AuZn) 46 is formed on the p-InP layer 36 and a common n-type electrode (AuGeNi) 42 is formed on the back surface of the n-InP substrate 30. Insulating film 5
After the film formation of 2, the wiring including the bonding pad is formed.
【００２１】以上の第３の実施例においては、第１の実
施例と同様に、オーミック電極および配線電極は、兼用
が可能である。また、受光素子上部の絶縁膜５２の膜厚
を無反射条件にすることにより、デバイス特性を向上さ
せることができる。In the third embodiment, as in the first embodiment, the ohmic electrode and the wiring electrode can be shared. In addition, by setting the thickness of the insulating film 52 above the light receiving element to a non-reflection condition, device characteristics can be improved.
【００２２】また、第３の実施例によれば、エッチング
部分すなわち分離溝を、半導体材料にて埋込を行うこと
により、メサのエッチング面が改善され、ダメージ等に
よる再結合準位が低減する。したがって、メサ界面での
リーク電流が低減する。According to the third embodiment, the etched portion, that is, the separation groove is buried with a semiconductor material, so that the etching surface of the mesa is improved and the recombination level due to damage or the like is reduced. . Therefore, the leakage current at the mesa interface is reduced.
【００２３】また、埋込再成長により分離溝が埋込まれ
平坦化されるため、エッチング段差を低減でき、配線電
極の引き回しが容易になる。Further, since the separation groove is buried and flattened by the burying regrowth, the etching step can be reduced and the wiring electrodes can be easily routed.
【００２４】さらに埋込み再成長により平坦化が可能で
あるため、エッチング段差すなわちエッチング深さが大
きくても問題がない。このため光吸収層３４の膜厚を大
きくすることができる。光吸収層の膜厚が大きくなる
と、受光感度，耐圧など、光吸収層膜厚に依存するデバ
イス特性が向上する。Furthermore, since flattening is possible by burying regrowth, there is no problem even if the etching step, that is, the etching depth is large. Therefore, the thickness of the light absorption layer 34 can be increased. As the thickness of the light absorbing layer increases, device characteristics such as light receiving sensitivity and breakdown voltage, which depend on the thickness of the light absorbing layer, are improved.
【００２５】本発明の受光素子アレイのメサ形成におい
ては、ＩｎＰおよびＩｎＧａＡｓとで選択性のあるエッ
チング液を使用することにより、各層の境界でエッチン
グを停止させることが容易となる。また、エッチングの
際にマスクをＳｉＮ膜やＳｉＯ2 膜にすることにより、
エッチング部分へのＩｎＰ再成長時にマスク材の成膜パ
ターニングを省略することができる。In the mesa formation of the light receiving element array of the present invention, the use of an etchant having a selectivity with InP and InGaAs makes it easy to stop the etching at the boundary between the layers. Also, by using a mask of SiN film or SiO 2 film at the time of etching,
It is possible to omit the film formation patterning of the mask material during the regrowth of InP on the etched portion.
【００２６】以上の第１〜第３の実施例では、ｎ−Ｉｎ
Ｐ層，ｉ−ＩｎＧａＡｓ層に次いで、ｐ−ＩｎＰ層を成
長することにより、ｐｉｎ構造を形成している。In the first to third embodiments, n-In
A p-type structure is formed by growing a p-InP layer after the P-layer and i-InGaAs layer.
【００２７】ｐｉｎ構造の形成は、これに限るものでは
なく、次のように形成することもできる。すなわち、ｎ
−ＩｎＰ，ｉ−ＩｎＧａＡｓ層に次いで、ｎ−ＩｎＰ層
を成長し、この層の全面にｐ型拡散を行うことによって
もｐｉｎ構造が形成できる。これにエッチング分離溝を
設ければ、同様にメサ型受光素子アレイを構成できる。The formation of the pin structure is not limited to this, and the pin structure can be formed as follows. That is, n
A pin structure can also be formed by growing an n-InP layer next to the -InP and i-InGaAs layers and performing p-type diffusion on the entire surface of this layer. If an etching separation groove is provided in this, a mesa light receiving element array can be similarly formed.
【００２８】[0028]
【発明の効果】本発明によれば、半導体層を積層してな
る受光素子にメサ構造を採用していることにより、受光
素子アレイのサイズおよびピッチを小さくすることがで
きる。したがって、光分波モジュールに用いる高精細型
の受光素子アレイ、例えば２５μｍ以下のピッチで１２
８個の受光素子からなるチップを実現することができ
る。According to the present invention, the size and pitch of the light receiving element array can be reduced by employing the mesa structure in the light receiving element formed by laminating the semiconductor layers. Therefore, a high-definition light-receiving element array used in the optical demultiplexing module, for example, 12 μm at a pitch of 25 μm or less.
A chip including eight light receiving elements can be realized.
【００２９】また、受光素子間が電気的に分離独立して
いるため、隣接素子へのクロストークの低減ができる。Further, since the light receiving elements are electrically separated and independent from each other, crosstalk to adjacent elements can be reduced.
【図面の簡単な説明】[Brief description of the drawings]
【図１】従来の拡散型受光素子アレイを示す図である。FIG. 1 is a diagram showing a conventional diffusion type light receiving element array.
【図２】図１の受光素子アレイ部分のＡ−Ａ′線の拡大
断面図である。FIG. 2 is an enlarged cross-sectional view taken along line AA ′ of the light receiving element array portion of FIG.
【図３】本発明のメサ型受光素子アレイの第１実施例の
断面図である。FIG. 3 is a sectional view of a first embodiment of the mesa-type light receiving element array of the present invention.
【図４】本発明のメサ型受光素子アレイの第２実施例の
断面図である。FIG. 4 is a cross-sectional view of a mesa-type light receiving element array according to a second embodiment of the present invention.
【図５】本発明のメサ型受光素子アレイの第３実施例の
断面図である。FIG. 5 is a sectional view of a mesa-type light receiving element array according to a third embodiment of the present invention.
３０ ｎ−ＩｎＰ基板 ３２ ｎ−ＩｎＰ層 ３４ ｉ−ＩｎＧａＡｓ層 ３６ ｐ−ＩｎＰ層 ３８，５２ 絶縁膜 ４０，４６ ｐ型オーミック電極 ４２ ｎ型オーミック電極 ４４ ＳＩ−ＩｎＰ基板 Reference Signs List 30 n-InP substrate 32 n-InP layer 34 i-InGaAs layer 36 p-InP layer 38,52 insulating film 40,46 p-type ohmic electrode 42 n-type ohmic electrode 44 SI-InP substrate
フロントページの続き (72)発明者 有馬 靖智 大阪府大阪市中央区道修町３丁目５番11号 日本板硝子株式会社内 (72)発明者 楠田 幸久 大阪府大阪市中央区道修町３丁目５番11号 日本板硝子株式会社内 Ｆターム(参考） 4M118 AA05 AB01 BA07 CA05 CB01 EA14 FB08 FB24 5F049 MA04 MB07 MB12 NA04 NA20 NB05 PA04 PA14 QA02 RA04 SE05 SS04 Continuation of the front page (72) Inventor Yasutomo Arima 3-5-11 Doshomachi, Chuo-ku, Osaka-shi, Osaka Inside Nippon Sheet Glass Co., Ltd. (72) Inventor Yukihisa Kusuda 3-5-2 Doshomachi, Chuo-ku, Osaka-shi, Osaka No. 11 F-term in Nippon Sheet Glass Co., Ltd. (reference) 4M118 AA05 AB01 BA07 CA05 CB01 EA14 FB08 FB24 5F049 MA04 MB07 MB12 NA04 NA20 NB05 PA04 PA14 QA02 RA04 SE05 SS04
Claims (4)
を多数配列した受光素子アレイにおいて、 前記受光素子は、ｎ型半導体基板上に、ｎ型半導体層，
ｉ型半導体層，ｐ型半導体層の順で積層されてなり、前
記受光素子間は前記ｐ型半導体層，前記ｉ型半導体層を
除去した分離溝で分離されており、前記ｐ型半導体層上
に各受光素子毎のｐ型電極が設けられ、前記ｎ型半導体
基板の裏面には、共通のｎ型電極が設けられていること
を特徴とする受光素子アレイ。1. A light-receiving element array in which a large number of light-receiving elements each composed of a pin photodiode are arranged.
An i-type semiconductor layer and a p-type semiconductor layer are stacked in this order, and the light receiving elements are separated by a separation groove from which the p-type semiconductor layer and the i-type semiconductor layer are removed. Wherein a p-type electrode is provided for each light-receiving element, and a common n-type electrode is provided on the back surface of the n-type semiconductor substrate.
を多数配列した受光素子アレイにおいて、 前記受光素子は、半絶縁性基板上に、ｎ型半導体層，ｉ
型半導体層，ｐ型半導体層の順で積層されてなり、前記
受光素子間は前記ｐ型半導体層，前記ｉ型半導体層内を
除去した分離溝で分離されており、前記ｐ型半導体層上
に各受光素子毎のｐ型電極が設けられ、前記分離溝の底
部であって前記ｎ型半導体上に各受光素子毎のｎ型電極
が設けられていることを特徴とする受光素子アレイ。2. A light-receiving element array in which a large number of light-receiving elements composed of pin photodiodes are arranged, wherein the light-receiving element is formed on an n-type semiconductor layer, i
The light receiving element is separated by a separation groove formed by removing the inside of the p-type semiconductor layer and the i-type semiconductor layer. Wherein a p-type electrode is provided for each light-receiving element, and an n-type electrode for each light-receiving element is provided at the bottom of the separation groove and on the n-type semiconductor.
ることを特徴とする請求項１記載の受光素子アレイ。3. The light receiving element array according to claim 1, wherein said separation groove is buried with a semiconductor material.
ことを特徴とする請求項３記載の受光素子アレイ。4. The light receiving element array according to claim 3, wherein said semiconductor material is formed by regrowth.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32200999A JP2001144278A (en) | 1999-11-12 | 1999-11-12 | Light receiving element array |
| CN 00802271 CN1327617A (en) | 1999-10-18 | 2000-10-11 | Light-receiving element array and light-receiving element array chip |
| CA002355146A CA2355146A1 (en) | 1999-10-18 | 2000-10-11 | Light-receiving element array and light-receiving element array chip |
| PCT/JP2000/007047 WO2001029896A1 (en) | 1999-10-18 | 2000-10-11 | Light-receiving element array and light-receiving element array chip |
| EP00966407A EP1182705A1 (en) | 1999-10-18 | 2000-10-11 | Light-receiving element array and light-receiving element array chip |
| TW89121654A TW475273B (en) | 1999-10-18 | 2000-10-17 | Light-receiving element array and light-receiving element array chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32200999A JP2001144278A (en) | 1999-11-12 | 1999-11-12 | Light receiving element array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001144278A true JP2001144278A (en) | 2001-05-25 |
Family
ID=18138911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32200999A Pending JP2001144278A (en) | 1999-10-18 | 1999-11-12 | Light receiving element array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001144278A (en) |
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