JPS6143739B2 - - Google Patents

Info

Publication number
JPS6143739B2
JPS6143739B2 JP56148632A JP14863281A JPS6143739B2 JP S6143739 B2 JPS6143739 B2 JP S6143739B2 JP 56148632 A JP56148632 A JP 56148632A JP 14863281 A JP14863281 A JP 14863281A JP S6143739 B2 JPS6143739 B2 JP S6143739B2
Authority
JP
Japan
Prior art keywords
cpu
error
circuit
logic device
normal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56148632A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5850049A (ja
Inventor
Toshimasa Takiguchi
Katsuichi Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56148632A priority Critical patent/JPS5850049A/ja
Publication of JPS5850049A publication Critical patent/JPS5850049A/ja
Publication of JPS6143739B2 publication Critical patent/JPS6143739B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
JP56148632A 1981-09-18 1981-09-18 多重論理装置システム Granted JPS5850049A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56148632A JPS5850049A (ja) 1981-09-18 1981-09-18 多重論理装置システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56148632A JPS5850049A (ja) 1981-09-18 1981-09-18 多重論理装置システム

Publications (2)

Publication Number Publication Date
JPS5850049A JPS5850049A (ja) 1983-03-24
JPS6143739B2 true JPS6143739B2 (fr) 1986-09-29

Family

ID=15457126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56148632A Granted JPS5850049A (ja) 1981-09-18 1981-09-18 多重論理装置システム

Country Status (1)

Country Link
JP (1) JPS5850049A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123150A (ja) * 1982-01-18 1983-07-22 Fujitsu Ltd デ−タ処理方式
JP2716537B2 (ja) * 1989-07-31 1998-02-18 富士通株式会社 複合システムにおけるダウン監視処理方式

Also Published As

Publication number Publication date
JPS5850049A (ja) 1983-03-24

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