JPS6142965A - Field effect transistor - Google Patents

Abstract

PURPOSE:To reduce a gate length by sequentially laminating the desired conductive type high conductive layer, a low conductive layer and a high conductive layer in this order in the thicknesswise direction of a wafer, using the surfaces of the both high conductive layers as source and drain, and forming the opposite conductive type region on the sides of the high and low conductive type layers as a gate. CONSTITUTION:An ohmic electrode 15 is positively biased to an ohmic electrode 14, the electrode 15 as a drain and the electrode 14 as a source. When the electrode 13 is set to the same voltage as the electrode 14, a current flows from the drain to the source. Then, when the electrode 13 is negatively biased to the electrode 14, a depletion layer is extended from the boundary between the P type layer of the P<+> type GaAs layer 12 and a buffer layer 9, the layer 10 and the N type layer of N<+> type GaAs layer 11. The thickness of the depletion layer is mostly extended in the layer 10 of the minimum impurity density to shut off a current between the drain and the source. Thus, a short channel effect can be eliminated at a superhigh speed to obtain low wiring resistance.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a field effect transistor (hereinafter referred to as "rFET") that utilizes a switching function and an electric 4m amplification function.
It is related to.

Conventional configurations and their problems In recent years, the demand for higher integration of transistors has become higher and higher.
The use of FETs that are most suitable for this purpose is remarkable, indeed, in pursuit of high-speed operation, from Si, which is the current mainstream material, to G
The field of development is expanding to include A, A, and S.

Figure 1 shows a conventional example of an n-Mo5-8i transistor as a typical example of an FET.
2) (3) is formed, and this partial diffusion layer (2) (3)
0 partial diffusion M (with ohmic electrodes (4) (5)
A thin film (6) of Sin is provided on the surface of the gap between 2) and (3), and an electrode (7) is provided thereon. Ohmic electrode (4
) (5) Apply a voltage between them, making the positive side the drain and the negative side the source. When the electrode (7) is at the same potential as the source, almost no current flows between the drain and the lease; when the electrode (7) is positively biased with respect to the source, S
io, an n-channel is generated near the surface of Si directly under the thin film (6), and a current flows between the ohmic electrodes (4) and (5).

The basic principle of FET operation is that the electrode (7) is called a gate, and the gate voltage controls the current between the source and drain.

The high speed of FET operation is almost determined by the distance between the source and drain, that is, the gate length, and the smaller L is, the better. The minimum value of L that can be reached is determined by the photolithography technique that separates the source and drain by a mask. The current minimum value that can be obtained relatively easily is 1μ.
It is m. Even if we use the best means, synchrotron radiation (SOR) technology, which is considered to be a vision of the future, the limit of L that can be achieved is 0.2 μm degrees. This means that
This is the first drawback common to all conventional FET structures.

Furthermore, a decrease in L narrows the line width of the wiring to the gate, and as a result, the wiring and resistance increase, reducing the high speed performance of the FET and making disconnection more likely to occur. This is the second
This is a drawback.

The third drawback is what is called the short channel effect. That is, even if L becomes small, the voltage applied between the source and drain remains constant, so a high electric field is applied within the channel, and passing carriers have high energy. This hot carrier is in the immediate vicinity (Si
n, captured by the gate oxide film consisting of a thin film (6). This capture of electrons charges the oxide film, causing changes in FET characteristics over time.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the prior art, making it easier to obtain a significantly smaller gate length, avoiding an increase in interconnect resistance due to a reduction in L, and eliminating the drawbacks of short channel effects. Removed. The objective is to provide a new field effect transistor with a three-dimensional structure that operates at ultra-high speed.

Structure of the Invention In order to achieve the above object, the field effect transistor of the present invention is provided by laminating a high conductivity layer, a low conductivity layer, and a high conductivity layer of a desired conductivity type in this order in the thickness direction of a wafer, and Guidance
Ohmic electrodes are provided on each surface of the R calendar to serve as a source and a drain, and a region of a conductivity type opposite to that of the high conductivity layer and the low conductivity layer is provided on the side surface of one of the high conductivity layers and the low conductivity layer. , and an ohmic electrode is provided in this region to serve as a gate.

According to this configuration, the thickness of the gate layer, that is, the gate length, can be made as thin as 100 nm using epitaxial growth technology, so that ultra-high-speed FET operation can be achieved, and at the same time, the line width of the gate wiring is not limited by the gate length. In addition, a field effect transistor can be obtained in which hot carrier trapping does not occur because there is no gate oxide film or crystal interface in the vicinity of the active layer.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention, in which (8) is an n''-GaAs substrate with an impurity concentration of 10''am-', and (9) is an n''-GaAs substrate with an impurity concentration of 10''cn+-'. A buffer layer of n” GaAs with a thickness of 2 μm.

(10) has an impurity concentration of 10110l4'' and a thickness of 0.lμ.
nII-GaAs active layer of rn, (11) is n''-GaA with an impurity concentration of 10110l7' and a thickness of 2 μm.
sff, (12) has an impurity concentration of 10"cm-' and a thickness of 3
．． 6 layers m of p''-GaAs layers, (13)
(14) is an ohmic electrode of Au/Zn alloy, (15
) are Au/Ge/Ni alloy ohmic electrodes,
(16) is a SiO film with a thickness of 3000 nm, and the distance between the edges of the source and drain regions is 2 μm.

Next, the operation will be explained. Now, the ohmic electrode (15) is positively biased with respect to the ohmic charge (14), the ohmic electrode (15) is drained, and the ohmic electrode (16) is
as the source. When the ohmic electrode (13) is set to the same potential as the ohmic electrode (14), a current flows from the drain to the source.
14), two layers of p”-GaAs layer (12), buffer layer (9) and active layer (10)
The depletion layer 1 spreads from the boundary with the 8th layer of n''-GaAs) fl (11). In other words, the ohmic electrode (13) functions as a gate, and the gate voltage controls the current between the drain and the source. A field effect transistor is obtained. If the gate voltage is kept constant and the drain voltage is increased, p ” -Ga A s
l (12), a buffer layer (9) and an operation layer (1)
Similarly, a reverse voltage is applied between the n''-GaAs layer (11) and the 0 layer, and the depletion layer expands, trying to block the passage of current. Therefore, the drain current increases as the drain voltage increases. In other words, the voltage-current characteristics of this field effect transistor exhibit pentode characteristics, and the speed of saturation increases as the impurity concentration of n!!J is decreased.

The maximum frequency of this field effect transistor is 100 G7.

Next, we will discuss the manufacturing method of the above field effect transistor in the third section.
This will be explained using figures. As shown in FIG. 3(A), n”
- On top of the GaAs substrate (8), a 24 m thick n''-Ga
A buffer layer (9) of As is formed, and then a layer with a thickness of 0 is formed on it.
．． A 1 μm thick n′-GaAs active layer (10) is formed, and finally a 2 μm thick n”-GaAs layer (10) is formed on top of the active layer (10).
(11) is formed by MOC and VD methods. As shown in FIG. 3(B), this wafer was coated with a buffer layer (9) of 0.0.
Perform plasma etching to leave 5 μm.

Create a striped mesa. On this wafer, as shown in FIG. 3(C), p''-G a A
When the s-layer (12) is formed, an uneven surface is formed as shown by diagonal lines. By etching, this unnecessary diagonal line portion is removed and one surface is made flat.

Finally, by SiO□ mask.

Au/Zn is deposited on the surface of the p''-GaAs layer (12), and in the same way, Au/Ge/Ni is deposited on the surface of the n''-GaAs layer (12).
11), and further Au/Ge/Ni is deposited on the n”-
After being deposited on the surface of the GaAs substrate (8), these are alloyed to complete the field effect transistor.

In this way, according to this embodiment, the gate length is determined by the operation ffi.
(10), and this thickness is determined by epitaxial growth technology and is not limited by photolithography technology as in the case of conventional FETs.Current epitaxial technology allows layer thicknesses of 100 It can be made as thin as a human being, which is more than an order of magnitude smaller than the minimum gate length allowed by photolithography technology. If the thickness of the layer is reduced, its resistivity must be increased, which is the preferred direction to obtain good crystals. On the other hand, in the case of MoS FETs and MES FETs (7), gate control is not performed through unnatural interface contact with dissimilar materials, so electrons that have become highly energized in the active layer (10) There is no cause for any change over time. In addition, since the width of the gate electrode consisting of the ohmic electrode (13) can be selected to be an appropriate width completely independent of the length, it is possible to select the width of the gate electrode made of the ohmic electrode (13) to an appropriate width, so that the wiring that inevitably accompanies the reduction of the gate length, as in the case of a normal FET, can be selected. There is no increase in resistance, this is a FET
This is advantageous when accumulating.

In the above embodiment, the material was GaAs, but
The material is not limited to these, and all materials such as single semiconductors such as Si and Ge, and compound semiconductors such as nP and Garb can be used.

Further, a complementary structure is also possible in which the n-side and n-side in the above embodiment are replaced with a P-side and an n-side, respectively.

Furthermore, the MOCVD method used in the fabrication in the above embodiments is a liquid phase epitaxial method, an MnE method, an impurity diffusion method, an ion implantation method, or the like.

In particular, the etching in the above embodiment followed by 90 layers of MO may be partially or totally replaced.
For CVD formation, it is also an excellent method to mask the outer surface of the P0 portion with Sio2 and perform p-type impurity diffusion, or to replace the p-type impurity by ion implantation. This method is.

This is particularly advantageous when using Si.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, it is possible to obtain a field effect transistor that is extremely fast, has no short channel effect, and can sufficiently reduce wiring resistance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional n-MoS-8i-FET, FIG. 2 is a cross-sectional view of an FET according to an embodiment of the present invention, and FIG.
The figure is a cross-sectional view illustrating the manufacturing process of the same FET. (8)...n"-GaAs substrate, (9)...buffer layer. (10)--active layer, (11)-n"-'GaAs
layer, (12) °=p”−GaAsFIJ, (1
3) ~(15)--ohmic electrode, (16)...
SiO, l Agent Yoshi Morimoto Personal Note 1 Figure 2

Claims (1)

[Claims] 1. A high conductivity layer, a low conductivity layer, and a high conductivity layer of the desired conductivity type are laminated in this order in the thickness direction of the wafer, and ohmic electrodes are provided on the surfaces of both the high conductivity layers to form source and drain connections. None, a region of a conductivity type opposite to that of the high conductivity layer and the low conductivity layer is formed on one of the high conductivity layers and the side surface of the low conductivity layer, and an ohmic electrode is provided in this region to serve as a gate. field effect transistor.