JPS6142962A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the disconnection of a scanning wiring by forming a gate electrode of two layers of chromium and molybdenum. CONSTITUTION:A transparent conductive layer 9 is formed on one main surface of a glass plate 8, and an oxide silicon 10 is coated on the overall surface. The gate electrode of a MIS transistor and a meal layer 4 for forming a scanning wiring are formed of two layers of chromium 19 and molybdenum 20, and a picture element electrodes 11 made of transparent conductive layer are formed on the layer 10. Then, a gate insulating layer 12 made of Si3N4 and an a-Si layer are accumulated to form an insular a-Si layer 13, and a hole 14 is formed at the layer 12. Then, a pair of metal layers partly superposed with the layer 4 are formed on the layer 13. One of the metal layers form a video signal wiring 5, and the other form the connecting wiring 15 of a MIS transistor and the electrode 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device that is combined with a liquid crystal to constitute an image display device.

The configuration of the conventional example and its problems Figure 1 shows a unit pixel consisting of a switching M/S transistor (1) and a liquid crystal cell (2), and a scanning line (4) and a signal a.
(5) This is an equivalent circuit of an image display device interconnected to form a two-dimensional matrix. A scanning pulse is applied to the scanning line (4) to turn on the MIS transistor (1) in the horizontal direction, and the signal terminal group (yl) in the horizontal direction is turned on.

yJ, □,...) to the liquid crystal cell (2)
have it written in. Next, a group of scanning terminals in the vertical direction (Xt+x
1+□, . . . ) by sequentially scanning scanning pulses to provide an image display function. The liquid crystal cell (2
) is stored in MIS) until the next write time.
Discharge occurs through the off resistance of transistor (1) and the resistance of the liquid crystal cell, and the time constant of the discharge is determined by the writing speed (
If the time is sufficiently longer than 1/60 second), a television image can be displayed. The reason why an auxiliary capacitor (3) having a sufficiently larger capacitance than the liquid crystal cell (2) is often added as a load to the MIS transistor (1) between it and the ground line (6) is for the reason described above. Note that by fixing the common electrode (7) to, for example, 6cm and switching the video signal voltage between 0 to 6V and 6 to 12V every time writing, the liquid crystal cell (2) is driven with alternating current.

Now, FIG. 2 shows a plan view of a unit picture element when MIS transistors using amorphous silicon (hereinafter abbreviated as a-8L) as a semiconductor material are integrated as switching elements, and FIG. Showing a sectional view of the main part on line A,
The manufacturing method is as described below.

A first layer is placed on the main surface of a transparent insulating substrate, for example, a glass plate (8).
A transparent conductive layer (9) is formed over the entire surface or selectively, and then a transparent insulating layer, for example silicon oxide (10), is applied over the entire surface. Then, a first metal layer (4) that constitutes the gate of the MIS transistor and also constitutes a scanning line, and a pixel electrode (11) made of a transparent conductive layer are selectively placed on the silicon oxide layer (10). Form. Next, for example, Si3
A gate insulating layer (12) made of N, and an a-5j layer containing almost no impurities are deposited on the entire surface, forming an island-like a-8i layer.
A layer (13) is formed and an opening (14) is formed in the gate insulating layer (12) on the picture element electrode (11). At the same time, although not shown, an opening is also formed in the gate insulating layer on the first metal layer (4), which will become the scanning line, in a region far away from the picture line section. Thereafter, a pair of second gold RFIIs are selectively formed of, for example, aluminum on the island-shaped a-SiM (13), partially overlapping the first metal layer (4) serving as the gate. One of the second metal layers constitutes a video signal line (5),
The other side is formed including the opening (14), and the connection line (14) between the M/S transistor (1) and the picture element electrode (11).
Although not shown, the second metal layer (5) constituting 15)
At the time of forming (15), the lead-out electrode to the scanning line (4) is also formed as described above.

In order to obtain an image display device, a polyimide thin film, for example, is applied to the surface of the semiconductor device, and after curing, an alignment treatment is performed, and a second transparent conductive layer (7), which is a common electrode, is deposited on the main surface. A liquid crystal (17) is filled between the glass plate (16) and the semiconductor device, and polarizing plates (17) are placed above and below.
lδ).

In order to improve the ohmic properties between the n-5i layer (13) and the second metal layers (5) and (15) as source and drain wiring, it is necessary to use a metal layer containing, for example, phosphorus or boron as a donor or acceptor. It is sufficient to have an a-8i layer interposed between them.

FIG. 4, like FIG. 2, is a plan view of a unit picture element, in which gate metal scraps (4') are also formed on the picture element electrode (11) in the opening (14). FIG. 5 is a sectional view taken along the line B--B in FIG. 4. The other configurations are the same as in FIGS. 2 and 3.

Now, in the semiconductor device described above, gate insulation M (1
The Si, H, layer 2) is deposited by glow discharge of SiH4 gas, and is usually etched with a mixed solution of hydrofluoric acid and ammonium fluoride to form an opening (14).

However, if the gate insulating layer (12) is hard to the etching solution, the resist is likely to peel off during long etching, and the opening (14) will not be formed properly. Therefore, such a gate insulating layer (12) can be etched by dry etching using Freon gas.

At this time, if the first gold mM (4) serving as the gate is a metal silicide such as molybdenum silicide, the gate insulating layer (12) S l, H4Jt! Since there is no etching selectivity with respect to etching 5, the first metal layer (4), which becomes the gate, is locally etched through the pinhole of the gate insulating layer (12) not only in the process where the metal silicide is exposed but also in the process where the metal silicide is not exposed. ) disappears, causing line defects that are fatal to image display devices. In addition, examples using molybdenum, chromium, and nichrome as the first metal layer (4) are known.

These are hardly etched by Freon gas, but the molybdenum is easily soluble in oxidizing acids such as nitric acid.
) When (15) is formed of aluminum, if an etching solution consisting of nitric acid and phosphoric acid is used, molybdenum will disappear through the pinholes in the gate insulating layer (12), and chromium and nichrome will be removed from the surface. It is chemically stable because it easily forms a thin oxide film and acts as a passive state. However, the presence of this stable oxide film poses a problem when forming wiring to the outside.

As mentioned above, scanning lines (4
) is exposed to an etching solution or gas for the Si, H, layer and 0□ plasma for removing the resist, resulting in the formation of a thin oxide film in a passive state. Therefore, the metal that makes up the extraction electrode is chromium via this thin oxide film.

It will come into contact with a scanning line such as nichrome. Therefore, unless heat treatment is performed at 400-500°C or higher, the contact resistance will be unstable and high, making the operation of the 1M S transistor unstable and unable to function as an image display device.On the other hand, due to glow discharge deposition Although it depends on the manufacturing conditions of the a-5i layer, if the a-5i layer is heated to a temperature of approximately 300° C. or higher, hydrogen that compensates for dangling bonds is released, and the film quality as a semiconductor material is significantly deteriorated.

OBJECTS OF THE INVENTION The present invention was made in view of the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device having scanning line wiring with fewer disconnections, and a method for manufacturing the same.

Structure of the Invention The key point of the present invention is that the gate electrode portion, which determines the characteristics of a semiconductor element, is formed of two layers of chromium and molybdenum.

DESCRIPTION OF EMBODIMENTS FIG. 6 shows a cross-sectional view of a main part of an image display device according to an embodiment of the present invention. The first metal layer also comprises chromium (19) and molybdenum (
20), and the other groove construction and manufacturing method are as described in FIG. 3. In addition,
Preferably, the formation of molybdenum (20) is done immediately after the deposition of chromium (19). At a film thickness of 1000 people, molybdenum (20) has a resistance of 1 to 2 Ω/mouth, and chromium (1
9) is 3 to 4 Ω/hole, so there is no problem with the resistance value even if molybdenum (20) is coated on chromium (19). Second metal M (5
) (15) is made of aluminum, even if some molybdenum is lost in the etching solution, it can be compensated for by the chromium in the lower layer. Note that since chromium tends to form a passive state, molybdenum (20) should be deposited immediately and preferably continuously after chromium (19) is deposited.

Further, between the a-8i layer (13) and the second metal layer (5) (15) as source and drain wiring, an amorphous semiconductor layer containing silicon as a main component and an impurity serving as a donor or acceptor is provided. Furthermore, the first transparent conductive layer (9) and the picture element electrode (1) may be interposed to improve the ohmic property.
The auxiliary capacitor (3) can also be formed through a silicon oxide layer (10) which is a transparent insulating layer formed on the entire surface of the auxiliary capacitor (3). In order to reduce the stray capacitance formed between the scanning line (4) or the signal line (5), it is preferable to pattern the first transparent conductive layer (9) selectively, rather than over the entire surface. , in which case the first transparent conductive layer (9) corresponds to the ground line (6) in FIG.

FIG. 7 shows a second embodiment of the present invention, which corresponds to the conventional example shown in FIG. The gate gold J'iCM (4) is composed of chromium (19) and molybdenum (20).

Gate insulation! The opening (14) in (12) is formed by dry etching with Freon gas, and the molybdenum (20) is exposed, but it is not destroyed and disappears.

Effects of the Invention As is clear from this explanation above, even when the step of forming an opening in the gate insulating layer is performed by dry etching using Freon gas, disconnection of the scanning line can be prevented, and the pins of the gate insulating layer can be prevented even in subsequent steps. Even if molybdenum is locally lost through the holes, it does not become the Fr line of the scanning line, and an image display device can be manufactured with a high yield.

Furthermore, since the present invention does not require heat treatment,
This is a manufacturing method suitable for a semiconductor device using an a-3 layer.

[Brief explanation of the drawing]

1st rf! i is MIS) - an equivalent circuit diagram of an image display device consisting of a transistor and a liquid crystal cell, FIGS. The figure is a schematic plan view and a cross-sectional view of a main part of a unit picture element of another example, and FIGS. 6 and 7 are schematic cross-sectional views of one embodiment of the present invention, respectively. (4)...Scan a (first metal layer), (5)...Signal 4! (second metal layer), (9)...first transparent conductive layer, (10)...silicon oxide layer, (11)...
Picture element electrode, (12)...gate insulating layer, (13) -
a-S 3 layers, (14)--opening, (15)-
... Connection line (second metal layer), (17) ... Liquid crystal, (
19)...Chromium, (20)...Molybdenum agent Yoshi Morimoto Ga Liang f figure IjJI+f Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A transparent conductive layer formed on an insulating substrate, a first metal layer consisting of two layers of chromium and molybdenum selectively formed thereon, and the first metal layer. an island-shaped non-single crystal semiconductor layer mainly composed of silicon formed on the layer through a first transparent insulating layer; and a first transparent conductive layer formed on the transparent conductive layer.
An opening is formed in the transparent insulating layer, and a pair of second metal layers are selectively formed on the island-shaped non-single crystal semiconductor layer so as to partially overlap with the first metal layer. wherein one of the second metal layers is in electrical contact with the transparent conductive layer through the opening. 2. The semiconductor according to claim 1, wherein the first metal layer is also formed on the transparent conductive layer in a pattern larger than the openings formed in the first transparent insulating layer. Device. 3. A non-single-crystal semiconductor layer containing silicon as a main component and an impurity serving as a donor or acceptor is interposed between the island-shaped non-single-crystal semiconductor layer and the second metal layer. A semiconductor device according to scope 1. 4. A step of selectively forming a transparent conductive layer on an insulating substrate, a step of selectively forming a first metal layer consisting of two layers of chromium and molybdenum, and after forming a transparent insulating layer on the entire surface,
forming an island-shaped non-single crystal semiconductor layer on the first metal layer; forming an opening in the transparent insulating layer formed on the transparent conductive layer; and forming an island-shaped non-single crystal semiconductor layer on the first metal layer; selectively forming a pair of second metal layers on the crystalline semiconductor layer that partially overlap the first metal layer and one of which contacts the transparent conductive layer through the opening; A method of manufacturing a semiconductor device, wherein the molybdenum is formed immediately after the chromium is deposited.