JPS6142939A - Chip type semiconductor device - Google Patents
Chip type semiconductor deviceInfo
- Publication number
- JPS6142939A JPS6142939A JP16530884A JP16530884A JPS6142939A JP S6142939 A JPS6142939 A JP S6142939A JP 16530884 A JP16530884 A JP 16530884A JP 16530884 A JP16530884 A JP 16530884A JP S6142939 A JPS6142939 A JP S6142939A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- type semiconductor
- external
- external conducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置に係シ、特に半導体素子から外部へ
導出されるリードに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a lead led out from a semiconductor element.
（従来の技術）
従来の大面の矩形を有するチップ型半導体装置例えば、
小屋可変容量ダ２イぞ一ド等は、第５回置および第５図
の）に示すように１絶縁体からなる封止樹脂体１０１と
所定の形状に整形された外部導出リード１０２の外部形
状を有している。このチップ型半導体装置は主にテーピ
ング、或はスティック詰等の荷・姿によって配線基板に
自動装着されることが多く、又配線基板への装着後は、
外部導出リードが半田等によりて配線基板に固定される
。(Prior Art) A conventional chip-type semiconductor device having a large rectangular shape, for example,
The variable capacitance die 2 and the like are connected to the outside of a sealing resin body 101 made of an insulator and an external lead-out lead 102 shaped into a predetermined shape, as shown in FIG. It has a shape. This chip type semiconductor device is often automatically attached to a wiring board mainly by taping or stick packaging, and after being attached to the wiring board,
The external leads are fixed to the wiring board with solder or the like.
さて、このような配線基板への自動装着時の場合チップ
型半導体装置紘第６図に示すように自動装着機の吸着ノ
ズル２０１によって吸着され基板の所定位置に仮固定さ
れるが、この仮固定の為の吸着ノズル２０１の加圧力に
よりて外部導出り−ド１０２は、第７図の矢印のような
機械的ス・ドレスをうけることになる。外部導出リード
１０２が受けるこの機械的ストレスは封止樹脂１０１に
作用し、封止樹脂体１０１のり２ツク、破壊等を発生さ
せる恐れ・がありた。Now, in the case of automatic mounting on such a wiring board, the chip type semiconductor device is sucked by the suction nozzle 201 of the automatic mounting machine and temporarily fixed at a predetermined position on the board as shown in Fig. 6. Due to the pressurizing force of the suction nozzle 201 for this purpose, the external lead-out wire 102 is subjected to mechanical stress as shown by the arrow in FIG. This mechanical stress applied to the external leads 102 acts on the sealing resin 101, and there is a fear that the sealing resin body 101 may become glued or damaged.
更にチップ半導体装置の基板装着後に第７図に示すよう
に外部導出リード１０２が半田３０１等によ□って配線
基板３０２に固定された場合、その後の温度変化による
チップ型半導体装置と配線基板３０２との熱膨張差によ
って外部導出リード２０１には、第７図の矢印に示した
よりな引張シ圧縮ストレスが加わることになる。Furthermore, if the external lead 102 is fixed to the wiring board 302 with solder 301 or the like as shown in FIG. 7 after the chip semiconductor device is attached to the board, the chip semiconductor device and the wiring board 302 may be damaged due to subsequent temperature changes. Due to the difference in thermal expansion between the external lead 201 and the external lead 201, more tensile and compressive stress is applied to the external lead 201 as indicated by the arrows in FIG.
この外部導出リード１０２への引張シ・圧縮ストレスが
繰シ返し加わると封止樹脂体１０１と外部導出リード１
０２との接着界面が剥離等を生じる為にチップ型半導体
装置の耐湿性劣化等の機能低下を生じる恐れがあった。When tensile and compressive stress is repeatedly applied to the external lead 102, the sealing resin body 101 and the external lead 1 are
Since peeling occurs at the adhesive interface with 02, there is a risk of deterioration in functionality such as deterioration in moisture resistance of the chip type semiconductor device.
（発明が解決しようとする問題点）
このように、従来のチップ型半導体装置の外部形状では
配線基板への装着時及び配線基板への固定後においてチ
ック型半導体装置の機能低下或は破壊を生じるという欠
点があった。(Problems to be Solved by the Invention) As described above, the external shape of the conventional chip-type semiconductor device causes functional deterioration or destruction of the chip-type semiconductor device when it is attached to the wiring board and after it is fixed to the wiring board. There was a drawback.
本発明の目的は、このような欠点を解決し配線基板への
装着時において機能低下或は破壊のないチップ型半導体
装置を提供することＫある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a chip-type semiconductor device which overcomes these drawbacks and which does not suffer from functional deterioration or destruction when mounted on a wiring board.
（問題点を解決するための手段）
本発明は、半導体素子を封止した絶縁体から外部へ導出
されるリードを備えたチップ型半導体装置において、外
部導出リードには外部導出リードに加わる機緘的ストレ
スを低減する為の緩衝部が設けられたチッ７°型半導体
にある。(Means for Solving the Problems) The present invention provides a chip type semiconductor device equipped with a lead led out to the outside from an insulator in which a semiconductor element is sealed. It is a chip 7° type semiconductor equipped with a buffer section to reduce physical stress.
（実施例）
次に、図面を参照しながら本発明をよシ詳細に説明する
。(Example) Next, the present invention will be explained in detail with reference to the drawings.
第１図体）、第１図の）、第１図（Ｃ）は、本発明の一
実施例のチック型半導体装置を示す正面図、側面図、外
部導出リードの展開図である。1), FIG. 1), and FIG. 1(C) are a front view, a side view, and a developed view of external leads, showing a tick-type semiconductor device according to an embodiment of the present invention.
これら図において本チップ整半導体装置は外部導出リー
ド１０２が封止樹脂体１０１の外部に導出する直後のリ
ード加工部４０１において封止樹脂体１０１に予め設け
てあった溝の内部に曲げられておシ、外部導出リード１
０２が上下左右に対するスプリング効果を出すように加
工しである。In these figures, in this chip-aligned semiconductor device, the external leads 102 are bent into the grooves previously provided in the encapsulating resin body 101 at the lead processing portion 401 immediately after they are led out of the encapsulating resin body 101. External lead 1
02 is processed to produce a spring effect in the vertical and horizontal directions.
又、外部導出リード１０２のリード加工部４０１のリー
ド幅寸法Ｌ′は基板に接解する部分である接触部４０２
のリード幅寸法りよシ細くし剛性が低くなるように加工
しである。Further, the lead width dimension L' of the lead processing portion 401 of the external lead 102 is the contact portion 402 which is the portion that is in contact with the substrate.
The lead width is narrower and the rigidity is lower.
このよりに外部導出リード１０２が、第１図のリード加
工部４０１のような緩衝作用を有する形状にすることに
よって、第６図で示した自動装着機の吸着ノズル２０１
の加圧によるストレスを吸収し、更に第７図で示した熱
膨張差によるストレスをも吸収することが可能となる利
点がある。By forming the external lead 102 into a shape having a buffering effect like the lead processing part 401 in FIG. 1, the suction nozzle 201 of the automatic mounting machine shown in FIG.
It has the advantage of being able to absorb the stress caused by pressurization, and also the stress caused by the difference in thermal expansion shown in FIG.
以上のように本発明によれば従来の標準化された外形寸
法を変えることなくしかも基板装着時のチップ型半導体
装置の座シ安定性を変えることなく基板装着上の欠点を
解決することができる。As described above, according to the present invention, it is possible to solve the drawbacks in board mounting without changing the conventional standardized external dimensions and without changing the seating stability of the chip type semiconductor device when it is mounted on the board.
次に、本発明の他の実施例を第２図および第３図に示す
。第２図は外部導出リード５０２のリード幅寸法を部分
的に細くした例であシ、第３図は外部導出リード６０２
に穴を開けることによって実質的にリード幅寸法を変え
た例である。これらの実施例でも第１図の実施例と同様
な効果が期待できることは明らかである。Next, another embodiment of the present invention is shown in FIGS. 2 and 3. FIG. 2 shows an example in which the lead width dimension of the external lead 502 is partially narrowed, and FIG. 3 shows an example of the external lead 602.
This is an example in which the lead width dimension is substantially changed by making a hole in the lead. It is clear that the same effects as the embodiment shown in FIG. 1 can be expected in these embodiments as well.
以上、本発明を外部導出リードの配線基板への接触部が
内側に整形されたチップ型半導体装置の例で説明したが
第４図に示したように外部導出リード７０２が外側に整
形されたチック型半導体装置、例えばミ＝゛モールドに
も適用できるものである。この時、外部導出リード７０
２の封止樹脂体７０１と平行する部分７０３に曲げ部や
幅狭部や開孔を設ければ良い。The present invention has been described above using an example of a chip type semiconductor device in which the contact portion of the external lead lead to the wiring board is shaped inside, but as shown in FIG. The present invention can also be applied to type semiconductor devices, such as micro-molds. At this time, the external lead 70
A bent portion, a narrow portion, or an opening may be provided in the portion 703 parallel to the sealing resin body 701 of No. 2.
（発明の効果）
このように、本発明によれば外部導出リードに外力に対
する緩衝部を有しているので自動装着機の吸着ノズルに
よる加圧や半田付時の熱膨張差によるストレスを吸収で
き、半導体装置の信頼性を高めることができる。(Effects of the Invention) As described above, according to the present invention, the external lead has a buffer against external force, so it is possible to absorb stress caused by the pressure applied by the suction nozzle of the automatic mounting machine and the difference in thermal expansion during soldering. , the reliability of the semiconductor device can be improved.
第１回置は本発明の一実施例を示す正面図、第１図（Ｂ
ｌは第１図（イ）の側面図、第１図（ｑは外部導出リー
ドの形状をわかシ易く示すための展開図でるる。第２図
および第３図は他の実施例を示す正面図と側面図でおる
。第４図は本発明が適用される他のチック型半導体装置
の正面図である。第５図（Ａ）は従来のチック型半導体
装置のリードを説明するための正面図、第５図（ト））
は第５図（Ａ）の側面図である。第６図はチップ型半導
体装置を基板に装着したときの断面図、第７図はチップ
型半導体装置を半田で基板に装着したときの断面図であ
る。
１０１，５０１，６０１，７０１・・・封止樹脂体、１
０２．５０２，６０２，７０２・・・外部導出リード、
２０１・・・装着用ノズル、２０２，３０２・・・配線
基板、３０１・・・半田、４０１・・・リード加工部、
４０２・・・リードの基板接触部、Ｌ、Ｌ’・・・リー
ド幅寸法。The first position is a front view showing one embodiment of the present invention, FIG.
1 is a side view of FIG. 1 (a), and FIG. FIG. 4 is a front view of another tick-type semiconductor device to which the present invention is applied. FIG. 5(A) is a front view for explaining the lead of a conventional tick-type semiconductor device. Figure, Figure 5 (g))
is a side view of FIG. 5(A). FIG. 6 is a cross-sectional view of the chip-type semiconductor device mounted on the substrate, and FIG. 7 is a cross-sectional view of the chip-type semiconductor device mounted on the substrate with solder. 101,501,601,701...Sealing resin body, 1
02.502,602,702...external lead,
201... Mounting nozzle, 202, 302... Wiring board, 301... Solder, 401... Lead processing section,
402... Lead contact portion with substrate, L, L'... Lead width dimension.
Claims (1)
ドを備えたチップ型半導体装置において、前記リードに
外力を吸収する緩衝部が形成されていることを特徴とす
るチップ型半導体装置。What is claimed is: 1. A chip-type semiconductor device comprising a lead extending to the outside from an insulator sealing a semiconductor element, the chip-type semiconductor device being characterized in that a buffer portion for absorbing external force is formed in the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16530884A JPS6142939A (en) | 1984-08-07 | 1984-08-07 | Chip type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16530884A JPS6142939A (en) | 1984-08-07 | 1984-08-07 | Chip type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142939A true JPS6142939A (en) | 1986-03-01 |
Family
ID=15809865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16530884A Pending JPS6142939A (en) | 1984-08-07 | 1984-08-07 | Chip type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142939A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344524U (en) * | 1986-09-08 | 1988-03-25 | ||
| EP1187227A2 (en) * | 1989-05-31 | 2002-03-13 | Osram Opto Semiconductors GmbH & Co. OHG | Surface-mountable optical element and method of fabrication |
| KR20210138100A (en) * | 2020-05-01 | 2021-11-18 | 가부시키가이샤 고요 기켄 | resistance welding device |
-
1984
- 1984-08-07 JP JP16530884A patent/JPS6142939A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344524U (en) * | 1986-09-08 | 1988-03-25 | ||
| EP1187227A2 (en) * | 1989-05-31 | 2002-03-13 | Osram Opto Semiconductors GmbH & Co. OHG | Surface-mountable optical element and method of fabrication |
| EP1187227A3 (en) * | 1989-05-31 | 2002-08-28 | Osram Opto Semiconductors GmbH & Co. OHG | Surface-mountable optical element and method of fabrication |
| EP1022787B1 (en) * | 1989-05-31 | 2003-05-07 | Osram Opto Semiconductors GmbH | Method of producing a surface-mountable optical element and surface-mountable optical element |
| KR20210138100A (en) * | 2020-05-01 | 2021-11-18 | 가부시키가이샤 고요 기켄 | resistance welding device |
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