JPS6141019B2 - - Google Patents

Info

Publication number
JPS6141019B2
JPS6141019B2 JP58056617A JP5661783A JPS6141019B2 JP S6141019 B2 JPS6141019 B2 JP S6141019B2 JP 58056617 A JP58056617 A JP 58056617A JP 5661783 A JP5661783 A JP 5661783A JP S6141019 B2 JPS6141019 B2 JP S6141019B2
Authority
JP
Japan
Prior art keywords
address
storage device
store
buffer
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58056617A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59180878A (ja
Inventor
Hirosada Tone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58056617A priority Critical patent/JPS59180878A/ja
Publication of JPS59180878A publication Critical patent/JPS59180878A/ja
Publication of JPS6141019B2 publication Critical patent/JPS6141019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58056617A 1983-03-31 1983-03-31 バツフアストア制御方式 Granted JPS59180878A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58056617A JPS59180878A (ja) 1983-03-31 1983-03-31 バツフアストア制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58056617A JPS59180878A (ja) 1983-03-31 1983-03-31 バツフアストア制御方式

Publications (2)

Publication Number Publication Date
JPS59180878A JPS59180878A (ja) 1984-10-15
JPS6141019B2 true JPS6141019B2 (enrdf_load_html_response) 1986-09-12

Family

ID=13032222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58056617A Granted JPS59180878A (ja) 1983-03-31 1983-03-31 バツフアストア制御方式

Country Status (1)

Country Link
JP (1) JPS59180878A (enrdf_load_html_response)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102344A (ja) * 1985-10-29 1987-05-12 Fujitsu Ltd バツフア・メモリ制御方式
JPS62275390A (ja) * 1986-05-22 1987-11-30 Fujitsu Ltd 連想メモリ装置
JP2596637B2 (ja) * 1990-11-09 1997-04-02 株式会社日立製作所 キャッシュ制御方式

Also Published As

Publication number Publication date
JPS59180878A (ja) 1984-10-15

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