JPS6140139B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a structure that effectively prevents malfunctions caused by undesirable parasitic elements existing between a transistor whose collector is connected to ground and other circuit elements.

Generally, integrated circuits are fabricated by fabricating the necessary circuit elements in a plurality of N-type semiconductor regions separated from a P-type semiconductor by PN junctions, including resistors and NPN transistors with collector grounding. can be integrated in the N-type semiconductor region, which has the highest potential among many circuit elements, and generally, as shown in Figures 1 and 2, examples of this are shown in Figures 1 and 2. A grounded collector NPN transistor _Q1 and a resistor R are integrated together in one N-type semiconductor region.

In Figures 1 and 2, 1 is the above-mentioned N
It is a region consisting of a shaped semiconductor, and the above transistor
It also works as a collector for _Q1 . Reference numeral 2 designates the base of the transistor _Q1 formed in the region 1, and is formed of a P-type semiconductor region. 3 is also the emitter of the above transistor _Q1 ,
It is formed by an N ⁺ type semiconductor region. Reference numeral 4 designates an N ⁺ type semiconductor region including the collector ohmic contact and power supply terminal of transistor _Q1 , and reference numeral 5 designates a resistor R region made of a P type semiconductor integrated in region ₁ together with transistor Q1. Further, numeral 6 denotes a floating collector region made of an N ⁺ type semiconductor for lowering the collector saturation resistance of the transistor _Q1 . Also, 7 is P
The type semiconductor substrate 7' is an isolation region formed by a P-type impurity diffusion method, etc., and generally has the lowest potential (earth potential). Therefore, the PN junction between the substrate 7 and region 7' and the N-type region 1 is sufficiently reverse biased and isolated. Also B, E, C, Ra,
Rb are the base, emitter, collector, and one and other electrodes of the transistor, respectively.

In this conventional example, the parts 4, 1, 6, etc. that constitute the collector of the transistor Q ₁ are kept at the highest potential, so the PN junction formed between them and the P-type semiconductor region 5 that operates as the resistor R is reversed. biased, and therefore the resistance R shows the correct resistance value originally possessed by the P-type semiconductor region 5,
There are no particular problems.

However, in such a configuration, in rare cases, undesirable coupling between the elements may occur, causing a malfunction in circuit operation. For example, when a pulse input from the base electrode B of transistor _Q1 is added,
Malfunctions often occur when a large current suddenly flows through transistor _Q1 . That is, when a large current flows through the transistor _Q1 , a collector current flows through the resistors _r1 and _r3 of the N-type region 1 shown in FIG. 2, and the resistor _r2 of the floating collector region, thereby causing The voltage at the floating collector portion is lower than the potential of the power supply voltage (Vcc) due to the voltage drop due to _r1 . At this time, if the potential of the P-type semiconductor region 5, which operates as a resistor R, is higher than the potential of the floating collector 6, a part of the PN junction _J2 becomes conductive in the forward direction, and the resistor R no longer exhibits a normal resistance value. A parasitic PNP transistor Q ₂ is generated having region 5 as an emitter, region 1 as a base, and region 2 as a collector, and this transistor Q ₂ couples the resistor R and the transistor Q ₁ to prevent normal operation. Conventionally, a method for eliminating such malfunctions is to interpose a separation diffusion region 7' between the resistor R and the transistor _Q1 , and divide the N-type semiconductor regions into regions 1 and 1', as shown in FIG. There is a known method for complete separation. However, such a method not only requires an extra isolation region 7' but also the collector contact 4'.
The contact 4'' to the N-type semiconductor region 1'' of the resistor portion must be provided separately, and furthermore, a certain distance must be maintained between the isolation region 7' and the resistor 5 and the collector 4' of the transistor _Q1 . (distance of the spread of the depletion layer and the spread of the diffusion layer in the lateral direction during separation and diffusion), and as a result, the chip area is significantly larger than in the case of Fig. 2, resulting in higher costs. It was hot.

The present invention aims to prevent the above-mentioned malfunction without having the above-described drawbacks of the prior art, and the present invention will be described below with reference to an embodiment shown in FIG. 4.

In this embodiment, the extra isolation region 7' as shown in FIG. 3 is not used, and the floating collector is divided into 6' and 6'' parts, which are placed in the parts corresponding to the transistor _Q1 and the resistor R, respectively. Deep N ⁺ diffusion regions 8' and 8'', called collector all, are arranged directly below the power supply connection region 4, corresponding to the floating collectors 6' and 6''. This makes the value of r ₁ very small. Since the floating collector is divided into 6' and 6'', even if a large current flows through the transistor and the potential of the floating collector 6' decreases due to the voltage drop due to _r1 , the floating collector 6' It does not affect the potential of ``, and the potential of 6'' is maintained at a value approximately equal to Vcc through the contact 4, so the resistor 5 and the N-type regions 1 and 6''
The PN junction between the two is always maintained in a reverse bias state, and the above-mentioned change in resistance value and operation of the parasitic PNP transistor can be completely eliminated. Furthermore, there is no need for an extra isolation region (FIG. 3, 7) as in the conventional case, and the chip can be integrated in almost the same chip area as the basic case shown in FIG.

In the above embodiment, the relationship between the resistor R and the common collector transistor _Q1 was mainly described, but
A similar problem occurs when several resistors, capacitors, and a plurality of common collector transistors are placed in the same isolation region, and this problem can also be improved by the configuration of the present invention. Furthermore, in the above embodiment, a case was explained in which the collector of transistor _Q1 is set to the power supply potential, but even if it is not a power supply, the collector potential of the common collector transistor is the highest and other resistors operate at a lower potential. It is clear that the present invention can be easily applied if the

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the generation of parasitic transistors when a resistor and transistor are formed in the same semiconductor region, and Figure 2 is a cross-section of a semiconductor integrated circuit to explain why the parasitic transistors shown in Figure 1 are formed. 3 is a cross-sectional view of a conventional semiconductor integrated circuit that prevents the generation of parasitic transistors, and FIG.
The figure is a sectional view showing one embodiment of the present invention. 1, 1', 1''...Region made of N-type semiconductor, 2
...Region (base) made of P-type semiconductor, 3...
Region made of N ⁺ type semiconductor (emitter), 4,
4', 4''...Region made of N ⁺ type semiconductor (collector ohmic contact), 5...Resistor R region,
6, 6', 6''...Region made of N-type semiconductor (floating collector), 7...P-type semiconductor substrate,
7'... Separation region, 8', 8''... Deep N ⁺ diffusion region (collector all).

Claims (1)

[Claims] 1. A semiconductor having one main surface and a back surface,
A first region of a first conductivity type having one main surface and a back surface formed on one main surface, and a second region formed on one main surface of the first region using a part of the first region as a collector. a transistor with a common collector connected as a base and an emitter, respectively, of a second region made of a conductivity type semiconductor and a third region made of a first conductivity type semiconductor formed on the one main surface portion of the second region; A semiconductor integrated circuit comprising: a circuit component including a fourth region made of a semiconductor of a second conductivity type formed in another part of the first region via a PN junction in the main surface portion; and fifth and sixth regions made of a low resistivity first conductivity type semiconductor formed independently from each other on the back surface of the first region below the fourth region;
What is claimed is: 1. A semiconductor integrated circuit comprising: seventh and eighth regions made of a first conductivity type semiconductor with low resistivity, each independently contacting the first region and reaching the surface of the first region. 2. A fourth region in which a circuit component including a fourth region made of a semiconductor of a second conductivity type formed in another part of the first region via a PN junction is separated from the first region by the PN junction. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a resistor made of the following.