JPS57166070A - Semiconductor ic device - Google Patents
Semiconductor ic deviceInfo
- Publication number
- JPS57166070A JPS57166070A JP5147181A JP5147181A JPS57166070A JP S57166070 A JPS57166070 A JP S57166070A JP 5147181 A JP5147181 A JP 5147181A JP 5147181 A JP5147181 A JP 5147181A JP S57166070 A JPS57166070 A JP S57166070A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- transistor
- substrate
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000003071 parasitic effect Effects 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 230000003321 amplification Effects 0.000 abstract 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent latch up by reducing parasitic transistor current amplification by a method wherein an inverse conductivity type region of high impurity concentration is provided reaching a buried region in a semiconductor layer near a resistor region high potential terminal in a bipolar IC. CONSTITUTION:In a bipolar IC with a plurality of P type diffused resistor regions 30 are formed in an N type epitaxial layer 20 that is an insular resistor surrounded with a P type insulating region 26, an N<+> diffused region 21 is formed around the layer 20 deep enough to reach an N<+> buried layer 22 encircling all the regions 30. An N P N transistor emitter diffused region 23 is provided partially overlapping the region 21, and a contact window 24 is bored wherein a metal wiring 25 is installed. The wiring 25 is connected to a power source and the layer 20 potential is kept at the maximum. Current amplification by a parasitic P N P transistor for which the region 30 acts as an emitter, the layer 20 as a base, and the substrate 1 as a collector, is reduced and the current into the substrate 1 via this parasitic transistor is in turn reduced and, consequentially, the false rise of the substrate potential is rendered smaller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147181A JPS57166070A (en) | 1981-04-06 | 1981-04-06 | Semiconductor ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147181A JPS57166070A (en) | 1981-04-06 | 1981-04-06 | Semiconductor ic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57166070A true JPS57166070A (en) | 1982-10-13 |
Family
ID=12887856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5147181A Pending JPS57166070A (en) | 1981-04-06 | 1981-04-06 | Semiconductor ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57166070A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237195A (en) * | 1990-07-18 | 1993-08-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit arrangement for preventing latch up |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329557A (en) * | 1976-08-31 | 1978-03-18 | Casio Comput Co Ltd | Ac power supplier |
| JPS5519870A (en) * | 1978-07-28 | 1980-02-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1981
- 1981-04-06 JP JP5147181A patent/JPS57166070A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329557A (en) * | 1976-08-31 | 1978-03-18 | Casio Comput Co Ltd | Ac power supplier |
| JPS5519870A (en) * | 1978-07-28 | 1980-02-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237195A (en) * | 1990-07-18 | 1993-08-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit arrangement for preventing latch up |
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