JPS6139969U - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS6139969U
JPS6139969U JP12492184U JP12492184U JPS6139969U JP S6139969 U JPS6139969 U JP S6139969U JP 12492184 U JP12492184 U JP 12492184U JP 12492184 U JP12492184 U JP 12492184U JP S6139969 U JPS6139969 U JP S6139969U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
conductive patterns
abstract
gaps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12492184U
Other languages
Japanese (ja)
Inventor
誠一 上野
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP12492184U priority Critical patent/JPS6139969U/en
Publication of JPS6139969U publication Critical patent/JPS6139969U/en
Pending legal-status Critical Current

Links

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す断面図である。 第2図は従来の混成集積回路の基板を示す断面図である
。 1・・・・・・絶縁性基板、2,3・・・・・・導電性
パターン、4−・・・・・半田、5・・・・・・電気部
品、6・・・・・・絶縁物層。
FIG. 1 is a sectional view showing an embodiment of the present invention. FIG. 2 is a sectional view showing a substrate of a conventional hybrid integrated circuit. 1... Insulating substrate, 2, 3... Conductive pattern, 4... Solder, 5... Electrical component, 6... insulation layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁性基板上に複数の導電性パターンが形成され、該、
導電性パターンの間隙に絶縁性の物質が印刷等により接
着していることを特徴とする混成集積回路。
A plurality of conductive patterns are formed on an insulating substrate, the
A hybrid integrated circuit characterized by having an insulating substance adhered to the gaps between conductive patterns by printing or the like.
JP12492184U 1984-08-16 1984-08-16 hybrid integrated circuit Pending JPS6139969U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12492184U JPS6139969U (en) 1984-08-16 1984-08-16 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12492184U JPS6139969U (en) 1984-08-16 1984-08-16 hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6139969U true JPS6139969U (en) 1986-03-13

Family

ID=30683617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12492184U Pending JPS6139969U (en) 1984-08-16 1984-08-16 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6139969U (en)

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