JPS6139745B2 - - Google Patents

Info

Publication number
JPS6139745B2
JPS6139745B2 JP7013877A JP7013877A JPS6139745B2 JP S6139745 B2 JPS6139745 B2 JP S6139745B2 JP 7013877 A JP7013877 A JP 7013877A JP 7013877 A JP7013877 A JP 7013877A JP S6139745 B2 JPS6139745 B2 JP S6139745B2
Authority
JP
Japan
Prior art keywords
opening
oxide film
silicon oxide
silicon nitride
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7013877A
Other languages
Japanese (ja)
Other versions
JPS544575A (en
Inventor
Kunio Aomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7013877A priority Critical patent/JPS544575A/en
Publication of JPS544575A publication Critical patent/JPS544575A/en
Publication of JPS6139745B2 publication Critical patent/JPS6139745B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法にかかり、とく
に表面安定化の為にシリコン窒化膜を使用する半
導体装置の製造方法、さらに微細パターンで浅い
接合を有する半導体装置の製造方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular a method for manufacturing a semiconductor device using a silicon nitride film for surface stabilization, and a method for manufacturing a semiconductor device having a shallow junction with a fine pattern. It is related to.

従来の微細パターンで浅い接合の半導体装置、
例えば、高周波用にウオツシユド・エミツタ構造
のトランジスタの表面安定化の為に、シリコン窒
化膜を形成する方法の一つは次の通りである。
Semiconductor devices with conventional fine patterns and shallow junctions,
For example, one method for forming a silicon nitride film to stabilize the surface of a washed emitter structure transistor for high frequency use is as follows.

第1図は従来の半導体装置の1例の製造におけ
る主な工程での断面図である。
FIG. 1 is a cross-sectional view showing the main steps in manufacturing an example of a conventional semiconductor device.

N型シリコン基板11にP型ベース領域12を
設け、基板11の表面にシリコン酸化膜13、シ
リコン窒化膜14を順次被着する(第1図a)。
A P-type base region 12 is provided on an N-type silicon substrate 11, and a silicon oxide film 13 and a silicon nitride film 14 are sequentially deposited on the surface of the substrate 11 (FIG. 1a).

次に、フオトレジスト膜15をマスクにしてシ
リコン窒化膜14及びシリコン酸化膜13を順次
選択的に除去してベース領域12に達する開孔部
を設ける(第1図b)。
Next, using the photoresist film 15 as a mask, the silicon nitride film 14 and the silicon oxide film 13 are sequentially and selectively removed to form an opening reaching the base region 12 (FIG. 1b).

次に、フオトレジスト膜を除去した後、前記開
孔部よりリンを拡散し、P型ベース領域12中に
N領域16を設け、エミツタ領域とする(第1図
c)。
Next, after removing the photoresist film, phosphorus is diffused through the opening to form an N region 16 in the P type base region 12 to serve as an emitter region (FIG. 1c).

次に、選択的にフオトレジスト膜15′を形成
し、該フオトレジスト膜15′をマスクにして、
シリコン窒化膜14及びシリコン酸化膜13を順
次除去して、ベース領域12に達する開孔部を設
ける(第1図d)。
Next, a photoresist film 15' is selectively formed, and the photoresist film 15' is used as a mask.
The silicon nitride film 14 and the silicon oxide film 13 are sequentially removed to form an opening that reaches the base region 12 (FIG. 1d).

次に、フオトレジスタ膜15′を除去し、通常
の方法により、オーム性接続の可能な金属を用い
てベース領域12及びエミツタ領域16に金属電
極17,17′,17″を形成する(第1図e)。
Next, the photoresistor film 15' is removed, and metal electrodes 17, 17', 17'' are formed on the base region 12 and the emitter region 16 using a metal capable of ohmic connection using a conventional method (first Figure e).

上記が従来の製造方法であるが、該製造方法に
は次のような欠点があつた。
Although the above is a conventional manufacturing method, this manufacturing method has the following drawbacks.

ウオツシユドエミツタ構造を形成する工程(第
1図c)において、リン拡散によりベース領域1
2中にN型領域、即ちエミツタ領域16を設けた
後、金属電極とオーム性接続を可能にする為、基
板表面に生成したリンガラス層を除去しなければ
ならない。しかるにシリコン酸化膜とシリコン窒
化膜とでリンガラスに変換する割合が異なりシリ
コン酸化膜が大きい為、リンガラス層を除去した
後では第1図cに示すようにシリコン酸化膜13
の方がシリコン窒化膜14より、多量に除去さ
れ、ひさし状にシリコン窒化膜14が残る。この
まま金属電極を形成すると第1図eに示すように
このひさし状の下に空隙18が発生し、金属電極
の断線が起りやすくなり歩留の低下を招く一方、
信頼性の低下の原因にもなつていた。
In the step of forming the washed emitter structure (Fig. 1c), the base region 1 is
After providing the N-type region, ie the emitter region 16, in the substrate 2, the phosphorus glass layer formed on the substrate surface must be removed in order to enable an ohmic connection with the metal electrode. However, since the silicon oxide film and the silicon nitride film have different conversion rates to phosphorous glass and the silicon oxide film is larger, after the phosphorous glass layer is removed, the silicon oxide film 13 is converted into phosphorous glass as shown in FIG. 1c.
A larger amount of the silicon nitride film 14 is removed than that of the silicon nitride film 14, and the silicon nitride film 14 remains in a canopy shape. If the metal electrode is formed in this state, a void 18 will be generated under the eaves as shown in FIG.
This was also a cause of decreased reliability.

本発明は上記欠点を除き、安定かつ容易に高歩
留で、高信頼性を有する半導体装置を製造する方
法を提供するものである。
The present invention eliminates the above drawbacks and provides a method for stably and easily manufacturing a semiconductor device with high yield and high reliability.

本発明は、シリコン基板の一導電性のベース領
域上にシリコン酸化膜および第1のシリコン窒化
膜を順次被着する工程と、該第1のシリコン窒化
膜に選択的に該シリコン酸化膜に達する第1の開
孔部を設けた後、該シリコン酸化膜に該第1の開
孔部より面積の広い第2の開孔部を設ける工程
と、気相成長による第2のシリコン窒化膜を該第
2の開孔部のシリコン酸化膜の全側面に被着さ
せ、これにより該第1の開孔部より広くなつてい
る該第2の開孔部の部分を埋めかつ該第1の開孔
部から前記ベース領域に達しかつ該第2のシリコ
ン窒化膜に囲まれた第3の開孔部を形成する工程
と、しかる後にリンを該第1、第3の開孔部を通
して該ベース領域に導入して逆導電型のエミツタ
領域を形成する工程と、該エミツタ領域表面に生
成されたリンガラスを除去した後に該第1、第3
の開孔部を通して該エミツタ領域に接続せるエミ
ツタ電極を形成する工程とを有することを特徴と
する半導体装置の製造方法である。
The present invention includes a step of sequentially depositing a silicon oxide film and a first silicon nitride film on a conductive base region of a silicon substrate, and selectively reaching the first silicon nitride film. After providing the first opening, a second opening having a larger area than the first opening is provided in the silicon oxide film, and a second silicon nitride film is formed by vapor phase growth. A second opening is coated on all sides of the silicon oxide film, thereby filling a portion of the second opening that is wider than the first opening, and filling the second opening with a second opening. forming a third opening that reaches the base region from the bottom and is surrounded by the second silicon nitride film, and then introducing phosphorus into the base region through the first and third openings. and forming an emitter region of opposite conductivity type, and after removing the phosphorus glass generated on the surface of the emitter region, the first and third
forming an emitter electrode connected to the emitter region through the opening of the semiconductor device.

次に本発明の実施例を説明する。 Next, embodiments of the present invention will be described.

第2図は本発明の半導体装置の製造方法の実施
例を示す製造工程断面図である。
FIG. 2 is a manufacturing process sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

まず、P型ベース領域32の形成されたN型シ
リコン基板31にシリコン酸化膜33、シリコン
窒化膜34をそれぞれ膜厚約2000Å、約1000Åで
順次被着する(第2図a)。
First, a silicon oxide film 33 and a silicon nitride film 34 are sequentially deposited on an N-type silicon substrate 31 on which a P-type base region 32 is formed to a thickness of about 2000 Å and about 1000 Å, respectively (FIG. 2a).

次にフオトレジスト膜をマスクにして、シリコ
ン窒化膜34を選択的に除去し、シリコン酸化膜
33に達する開孔部を設け、続いて、残存シリコ
ン窒化膜をマスクにして前記開孔部を用いて自己
整合的にバツフアード弗酸液にて、前記開孔部よ
り面積の広い、P型ベース領域32に達する開孔
部をシリコン酸化膜3に設ける(第2図b)。
Next, using the photoresist film as a mask, the silicon nitride film 34 is selectively removed to form an opening that reaches the silicon oxide film 33, and then, using the remaining silicon nitride film as a mask, the opening is removed. Then, in a self-aligned manner, a buffered hydrofluoric acid solution is used to form an opening in the silicon oxide film 3, which has a larger area than the opening and reaches the P-type base region 32 (FIG. 2b).

次に全面にシリコン窒化膜39を気相成長法に
より約1500Å成長させ、前工程で形成されたシリ
コン窒化膜34とシリコン基板との間の約2000Å
の空隙に、新しく被着されたシリコン窒化膜39
を埋め込む(第2図c)。
Next, a silicon nitride film 39 is grown to a thickness of approximately 1500 Å over the entire surface by vapor phase growth, and a thickness of approximately 200 Å is grown between the silicon nitride film 34 formed in the previous step and the silicon substrate.
A newly deposited silicon nitride film 39 is placed in the void of
(Figure 2c).

次に、前工程で気相成長させたシリコン窒化膜
39をその成長膜厚分、即ち、約1500Åのシリコ
ン窒化膜を制御よく除去し、ベース領域32の表
面を露出させる(第2図d)。
Next, the silicon nitride film 39 grown in the vapor phase in the previous step is removed by the thickness of the grown film, that is, about 1500 Å, in a controlled manner to expose the surface of the base region 32 (FIG. 2 d). .

次に、前工程で設けられた開孔部よりリン拡散
をしてベース領域中32にN型領域、即ち、エミ
ツタ領域36を形成した後エミツタ領域表面のリ
ンガラス層を除去する(第2図e)。
Next, phosphorus is diffused through the openings provided in the previous step to form an N-type region, that is, an emitter region 36 in the base region 32, and then the phosphorus glass layer on the surface of the emitter region is removed (see Fig. 2). e).

次に、選択的にフオトレジスト膜35を形成
し、該フオトレジスト膜35をマスクにして、ベ
ース領域32に達する開孔部を設ける(第2図
f)。
Next, a photoresist film 35 is selectively formed, and using the photoresist film 35 as a mask, an opening reaching the base region 32 is provided (FIG. 2f).

次に、該開孔部と、前記エミツタ領域36上面
に設けられた開孔部とを覆い、かつ、ベース領域
32及びエミツタ領域36とオーム性接続を可能
にする為アルミニウムによる金属電極37,3
7′,37″を選択的に形成する(第2図g)。
Next, metal electrodes 37 and 3 made of aluminum are used to cover the opening and the opening provided on the upper surface of the emitter region 36 and to enable ohmic connection with the base region 32 and the emitter region 36.
7', 37'' are selectively formed (Fig. 2g).

この実施例では、リン拡散する以前に、開孔部
の周囲を同質の絶縁膜で形成している為、リン拡
散で形成されるリンガラス層の膜層が同じにな
り、リンガラス層除去後も、異質の2層構造の場
合と違い、ひさし状の構造にはならない。又、こ
の実施例ではエミツタ領域の面積を小さくできる
為、より高性能の半導体装置の製造に適してい
る。
In this example, since the periphery of the opening is formed with a homogeneous insulating film before phosphorus diffusion, the film layer of the phosphorus glass layer formed by phosphorus diffusion is the same, and after the phosphorus glass layer is removed. However, unlike the case of a two-layered structure, it does not form an eave-like structure. Further, in this embodiment, since the area of the emitter region can be reduced, it is suitable for manufacturing higher performance semiconductor devices.

以上詳細に説明したように、本発明によれば、
安定かつ容易に高歩留で高信頼性の半導体装置が
得られるのでその効果は大きい。
As explained in detail above, according to the present invention,
The effect is great because a semiconductor device with high yield and high reliability can be obtained stably and easily.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の1例の製造におけ
る主な工程での断面図、第2図は本発明の半導体
装置の製造方法の実施例を示す製造工程断面図で
ある。 11,31……N型シリコン基板、12,32
……P型ベース領域、13,33……シリコン酸
化膜、14,34……シリコン窒化膜、15,3
5……フオトレジスト膜、16,36……N型エ
ミツタ領域、17,37……金属電極、18……
空隙、39……絶縁膜。
FIG. 1 is a cross-sectional view of the main steps in manufacturing an example of a conventional semiconductor device, and FIG. 2 is a cross-sectional view of the manufacturing process showing an embodiment of the method of manufacturing a semiconductor device of the present invention. 11, 31...N-type silicon substrate, 12, 32
...P-type base region, 13,33...Silicon oxide film, 14,34...Silicon nitride film, 15,3
5... Photoresist film, 16, 36... N-type emitter region, 17, 37... Metal electrode, 18...
Void, 39...Insulating film.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン基板の一導電型のベース領域上にシ
リコン酸化膜および第1のシリコン窒化膜を順次
被着する工程と、該第1のシリコン窒化膜に選択
的に該シリコン酸化膜に達する第1の開孔部を設
けた後、該シリコン酸化膜に該第1の開孔部より
面積の広い第2の開孔部を設ける工程と、気相成
長による第2のシリコン窒化膜を該第2の開孔部
のシリコン酸化膜の全側面に被着させ、これによ
り該第1の開孔部より広くなつている該第2の開
孔部の部分を埋めかつ該第1の開孔部から前記ベ
ース領域に達しかつ該第2のシリコン窒化膜に囲
まれた第3の開孔部を形成する工程と、しかる後
にリンを該第1、第3の開孔部を通して該ベース
領域に導入して逆導電型のエミツタ領域を形成す
る工程と、該エミツタ領域表面に生成されたリン
ガラスを除去した後に該第1、第3の開孔部を通
して該エミツタ領域に接続せるエミツタ電極を形
成する工程とを有することを特徴とする半導体装
置の製造方法。
1. A step of sequentially depositing a silicon oxide film and a first silicon nitride film on a base region of one conductivity type of a silicon substrate, and a step of depositing a first silicon oxide film selectively on the first silicon nitride film. After providing the opening, a second opening having a larger area than the first opening is provided in the silicon oxide film, and a second silicon nitride film is grown by vapor phase growth into the second silicon oxide film. The silicon oxide film is deposited on all sides of the opening, thereby filling the part of the second opening that is wider than the first opening, and depositing the silicon oxide film from the first opening. forming a third aperture reaching the base region and surrounded by the second silicon nitride film; and then introducing phosphorus into the base region through the first and third apertures. a step of forming an emitter region of opposite conductivity type; and a step of forming an emitter electrode connected to the emitter region through the first and third openings after removing phosphorus glass generated on the surface of the emitter region. A method of manufacturing a semiconductor device, comprising:
JP7013877A 1977-06-13 1977-06-13 Production of semiconductor devices Granted JPS544575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7013877A JPS544575A (en) 1977-06-13 1977-06-13 Production of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7013877A JPS544575A (en) 1977-06-13 1977-06-13 Production of semiconductor devices

Publications (2)

Publication Number Publication Date
JPS544575A JPS544575A (en) 1979-01-13
JPS6139745B2 true JPS6139745B2 (en) 1986-09-05

Family

ID=13422900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7013877A Granted JPS544575A (en) 1977-06-13 1977-06-13 Production of semiconductor devices

Country Status (1)

Country Link
JP (1) JPS544575A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58206158A (en) * 1982-05-27 1983-12-01 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS544575A (en) 1979-01-13

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