JPS6139740B2 - - Google Patents

Info

Publication number
JPS6139740B2
JPS6139740B2 JP56193519A JP19351981A JPS6139740B2 JP S6139740 B2 JPS6139740 B2 JP S6139740B2 JP 56193519 A JP56193519 A JP 56193519A JP 19351981 A JP19351981 A JP 19351981A JP S6139740 B2 JPS6139740 B2 JP S6139740B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
wiring area
package
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56193519A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5892248A (ja
Inventor
Takashi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56193519A priority Critical patent/JPS5892248A/ja
Publication of JPS5892248A publication Critical patent/JPS5892248A/ja
Publication of JPS6139740B2 publication Critical patent/JPS6139740B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/879—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP56193519A 1981-11-28 1981-11-28 大規模実装化半導体装置 Granted JPS5892248A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56193519A JPS5892248A (ja) 1981-11-28 1981-11-28 大規模実装化半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56193519A JPS5892248A (ja) 1981-11-28 1981-11-28 大規模実装化半導体装置

Publications (2)

Publication Number Publication Date
JPS5892248A JPS5892248A (ja) 1983-06-01
JPS6139740B2 true JPS6139740B2 (pl) 1986-09-05

Family

ID=16309412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56193519A Granted JPS5892248A (ja) 1981-11-28 1981-11-28 大規模実装化半導体装置

Country Status (1)

Country Link
JP (1) JPS5892248A (pl)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216250A (ja) * 1985-11-06 1987-09-22 Shinko Electric Ind Co Ltd プリント基板型ｐｇａパツケ−ジの製造方法

Also Published As

Publication number Publication date
JPS5892248A (ja) 1983-06-01

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