JPS6139131A - Data processor - Google Patents

Abstract

PURPOSE:To specify a machine cycle with a microinstruction by the processor which has a high rate of hardware control by providing a mechanism which determines the machine cycle on the basis of machine cycle specification information on a microinstruction and machine cycle request information by hardware control. CONSTITUTION:A register 1 holds machine cycle (MC) specification information from a hardware control part 10 and a register 2 holds an MC specification field; and either one has 3-bit length and specifies MC. An MC specifying circuit 3 ANDs respective bits of the registers 1 and 2, one by one, and then generates a machine cycle specifying code. A clock generating circuit 4 which receives it generates a clock with MC based upon the code. Consequently, MC specification by a microinstruction is performed through the processor which has a high rate of hardware control such as advanced control and cache memory control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device having a function of dynamically varying machine cycles.

[Technical background of the invention and its problems]

In a microprogram-controlled data processing device, the time required to execute a microinstruction varies depending on the function specified by the microinstruction, but usually the longest time is defined as a machine cycle. This value is often fixed. In this case, microinstructions that can be completed in a short execution time do not do anything and wait for the machine cycle to complete, which is inefficient. Therefore, a method was created to improve processing efficiency and performance by preparing hardware that can dynamically change the machine cycle and determining the optimal machine cycle by specifying microinstructions.

At this time, the machine cycle may be specified according to the operation part of the microinstruction, or may be directly provided with a field for specifying the cycle, as shown in FIG. In any case, the machine cycle is determined at the time of firmware creation.

By the way, as hardware operations become more complex and the number of parts that operate independently of microinstructions increases, such as instruction prefetching and cache memory, machine cycles are limited by these hardware as well. You will begin to receive

However, with the conventional means, the machine cycle is determined at the time of firmware creation, so it is not possible to satisfy the machine cycle requirement for one piece of hardware.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is suitable for processing devices using a microlog system in which hardware operations are performed independently of the execution of microinstructions, such as in instruction prefetching and cache memory control. An object of the present invention is to provide a variable clock type data processing device that can specify machine cycles corresponding to each operation.

[Summary of the invention]

The present invention provides a mechanism for determining a machine cycle based on machine cycle designation information of a microinstruction and machine cycle request information based on hardware control.
Even in processing devices with a high ratio of hardware control, such as cache memory control, it is possible to specify machine cycles using microinstructions, and coexist with machine cycle specification using hardware control. The machine can be used efficiently even if there are variations in operation.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a register that holds machine cycle designation information from the hardware control unit 10, and 2 is a register that holds a machine cycle designation field that is a part of the microinstruction register, both of which are composed of 3 bits. be done. Reference numeral 3 denotes a machine cycle designation circuit that designates a machine cycle according to the contents of each register 1.2. 4
is a clock generation circuit which generates a clock according to a machine cycle determined according to the output (2-bit machine cycle designation code) 5 of the machine cycle designation circuit 3, and 6 is its clock output line.

2 to 5 are for explaining the operation of one embodiment, and FIG. 2 is a diagram showing the correspondence between machine cycle designation bits and machine cycles in the information stored in the registers 1 and 2, FIG. 3 is a diagram showing the correspondence between a 2-bit machine cycle designation code outputted from the machine cycle designation circuit 3 and a machine cycle. FIG. 4 shows the output 5 of the machine cycle designation circuit 3, that is, the period of the clock that is output multiple times from the clock generation circuit 4 according to the 2-bit machine cycle designation code shown in FIG. The period is expressed as τ. FIG. 5 is a diagram showing signal states of each part in the above embodiment.

, Here, the operation of one embodiment will be explained with reference to FIGS. 1 to 5. Registers 1 and 2 shown in FIG. 1 are both three bits long and specify machine cycles according to the formation shown in FIG. The machine cycles in FIG. 2 are shown as integral multiples of τ, where τ is the basic clock cycle of the clock generation circuit 4. In addition, in Figure 2, the value of each pit is
This indicates that 'O' or '1# may be used in the part marked with '.
．． After calculating the logical sum for each bit of 2, a machine cycle designation code is generated according to the code correspondence shown in FIG. Upon receiving the 2-bit machine cycle designation code shown in FIG. 3, the clock generation circuit 4 generates a machine cycle clock according to the code. An example of this clock output is shown in FIG.

Next, specific operations will be further explained with reference to FIG.

When the machine cycle specified by the microinstruction is 5τ, "o o i" is set in register 2. On the other hand, "011" is set in register 1 due to a hardware control request unrelated to the execution of the microinstruction.Here, bit 1 and bit 2 are set at the same time (pa 1) because This is because the part of the hardware control part that requests 5τ sets bit 2, and the part that requests 6τ sets bit 1. The logical sum of the registers 1 and 2 above is 0'011'', and as a result, the machine cycle is 6τ. The longest cycle specification among the specifications from is valid.

By controlling the machine cycle variably in this way, even in processing devices with a high ratio of hardware control, such as advance control and cache memory control, it is possible to specify machine cycles using microinstructions. Coexistence with machine cycle specification can be realized, which allows efficient machine use even if there are operations with varying execution times.

〔Effect of the invention〕

As detailed above, according to the data processing device of the present invention,
A mechanism is provided to determine the machine cycle based on the machine cycle specification information of microinstructions and the machine cycle request information based on hardware control. However, it is possible to specify a machine cycle using microinstructions, and it is possible to coexist with machine cycle specification using hardware control. 0 available

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 5 are for explaining the operation of the above embodiment, and FIG. 2 shows the relationship between machine cycle designation bits and machine cycles. 3 is a diagram showing the machine cycle designation code and its contents; FIG. 4 is a time chart showing the relationship between the basic clock and the variable clock output from the clock generation circuit according to the machine cycle designation code;
FIG. 5 is a diagram showing the signal status of each part in the above embodiment,
FIG. 6 is a diagram showing the format of a microinstruction. 1.2...Register, 3...Machine cycle designation circuit, 4...Clock generation circuit, 10...No.1-Dware control section. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] a first means for holding a part of a microinstruction that specifies a machine cycle; a second means for instructing a request for a machine cycle by hardware control; It is characterized by comprising a machine cycle designation circuit that determines the cycle, and a clock generation circuit that outputs a clock with a period designated by the machine cycle designation circuit, and changes the machine cycle according to a request by hardware control. data processing equipment.