JPS613584A - Reproducing signal processing method of vtr - Google Patents

Abstract

PURPOSE:To correct a discontinuous part of a video signal caused at head changeover by reading a storage signal before several lines in place of reading a signal on a line on which a video head is switched. CONSTITUTION:A reproducing signal from a video head 1 is fed to a demodulator 2, where is demodulated into a reproducing video signal and fed to an A/D converter 10 and a synchronizing signal/burst separating circuit 11. The reproduced video signal subject to A/D conversion is written in a main storage device 4. The main storage device 4 consists of three RAMs 7, 8, 9 and an output signal of the A/D converter 10 is fed to the RAMs 7, 8, 9 switchingly. When the video head is switched, the writing to the RAM8 on the n-th line is inhibited and the signal of the (n-1)th line stored in the RAM7 is read for the read of the n-th line. Thus, the discontinuous part of the video signal caused at the changeover of the video head is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reproduction signal processing method for correcting time axis errors in a reproduced video signal of a VTR and for correcting discontinuities in the video signal that occur when switching video heads.

Conventional configuration and its problems Traditionally, in broadcast VTRs, reproduced video signals with time axis errors are stored in a plurality of storage elements, such as digital memories such as random access memory (hereinafter referred to as RAM) and shift registers. , or CCD.

By writing and storing data in a main memory device such as a BBD using a write clock according to the time axis error of the reproduced video signal, and sequentially reading it using a reference read clock, the time can be stored. A method is used to obtain a video signal with axis errors corrected.

First, a conventional reproduction method for correcting time axis errors will be explained.

FIG. 1 is a block diagram showing the configuration of an yrR reproduction system that corrects time axis errors. A reproduced signal from a video head (1) is supplied to a demodulator (2) and demodulated into a reproduced video signal. Note that when the reproduced signal is a mixed output of a frequency-modulated luminance signal and a low-frequency converted carrier chrominance signal, the demodulator (2) Fi outputs a luminance signal whose frequency is Ikf modulated. It includes a circuit that performs frequency demodulation and reconverts the low-frequency-converted carrier color signal to the original carrier color signal, and mixes these two signals to obtain a reproduced video signal. The reproduced video value Jij obtained from the demodulator (2) is supplied to the time axis correction device (3), and is stored in the main memory (
4) and is stored. This main storage device (4) is a line memory that can store information for one line of a video signal, for example, RAM (7), (8), (9).
). (6) is a reference signal input terminal, into which reference horizontal and vertical synchronization signals and subcarrier signals are input and supplied to the time axis correction device (3). A read clock is formed from this reference signal, and the main memory (
By reading out the stored signal in step 4) using the readout clock, a video signal whose time axis error has been corrected is obtained and outputted to the output terminal (5).

Figure 2 shows the output signal (a) of the demodulator (2) when the video head switching position is within the video signal of the nth line.
and the signal (b) output to the output terminal (5) and each RAM (
7) It is a diagram showing the operational relationship of (8) and (9). In the figure, W indicates that a sneaking operation is performed, and R indicates that a read operation is performed. As is clear from FIG. 2, by sequentially writing the reproduced video signal (a) Id having a time axis error into each RAM, temporarily storing it, and reading it using the reference clock, the time axis error is corrected. Signal (b
) has been obtained.

However, the discontinuous portion of the video signal that occurs when switching the video head cannot be corrected by the above-described reproduction method. For example, if two video heads are mounted on a rotary cylinder at a spacing of 180°,
In a VTR that records and reproduces video signals by rotating the VTR at rpm, the video head/do switch time is within the vertical retrace period, so discontinuous portions of the video signal do not appear on the monitor screen F. However, in VTRs in which the rotary cylinder rotates at 860 rpm, or in VTRs in which one field of video signals is recorded and played back by multiple video heads, a discontinuous portion of the video signal appears on the monitor screen H, making the screen very difficult to see. There was a point.

OBJECTS OF THE INVENTION An object of the present invention is to provide a reproduction signal processing method capable of correcting a discontinuous portion of a video signal that occurs when replacing a video head 9J.

Structure of the Invention The VTR playback/signal processing method of the present invention writes the playback video signal of the VTR into a storage device using a write clock formed from the playback video signal, and when reading it out using a reference read clock, the video head is switched. Instead of reading out the signal of the line where the video signal has been changed, the stored signal of several lines before is read out to correct the discontinuous part of the video signal that occurs when the video signal is switched.

DESCRIPTION OF EMBODIMENTS Specific embodiments of the present invention will be described below with reference to FIGS. 8 to 7.

FIG. 8 is a 5079 diagram of a reproduction system of a VTR that implements the reproduction signal processing method of the present invention. Components showing the same operations as those shown in FIG. 1 are given the same reference numerals and their explanations will be omitted. The reproduced signal '8' from the video head (1) is sent to the demodulator (2).
), the signal is demodulated into a reproduced video signal, and then supplied to the A/D converter interperiod signal/degree burst separation circuit (b). The reproduced video signal supplied to the A/D converter (to) is digitally converted and written to the main storage device (4). The A/D converter αQ is controlled by a write clock y-CLOCKJK that corresponds to the time axis error of the reproduced video signal, and this write clock is a horizontal/vertical synchronization signal obtained by a synchronization signal/burst separation circuit (b). and a burst signal are supplied to the write clock generator (2) and generated by the write clock generator (b). Main memory (4) is 8 RAM (7) (8) (9)
The output signal from the A/D converter a is RA
M(7), (8), and (9) are switched to be written using the write clock and read using the subsequent clock formed by the reference signal.

The control circuit (6) receives the write clock generated by the write clock generator (b) and the write t! o pulse,
The readout clock [R-CLOCKI and readout t] formed by the video head switching signal [H-5W] input from the input terminal (to) and the reference signal input from the input terminal (6) to the readout clock generator) ! o pulse [R-ZERO] is supplied, and this control circuit Q
I is the supply of write clock and read clock to the main memory (4), and each clock I (7) (8) (9
) controls writing and continuation selection. RAM
(7) (8) The signal read out from (9) using the reference read clock is supplied to the D/A converter a◆, where it is converted into an analog signal, and then sent to the output terminal (5) with a time axis error. A corrected video signal is output. In addition, the D/A conversion converter α said read clock [R-CLOCK]
Controlled by K.

Figure 4 shows the reproduced video signal (a) and each RAM (7/8) when video head switching occurs on the nth line.
FIG. 9 is a diagram showing the relationship between the operating state of (9) and the video signal ij (c) output to the output terminal (5).

Writing and reading signals up to the (n-1)th line operates in the same way as the conventional example shown in FIG.
When video head switching occurs, writing of the n-th n-line signal to RAM (8) is prohibited midway;
When reading the nth line of RAM (8), the RAM
The signal of the (n-1)th number from M(7) is read again. In other words, the signal on the nth line is replaced with the signal on the (n-1)th line line by line.

Furthermore, conventionally, the signal of the n-th line was read from the RAM (8), but the signal of the (n-th) line was read from the RAM (7).
1) In order to read the signal of the th line, the writing and reading timing J) of the RAM (7) of this embodiment after switching the video head is the same as that of the conventional RA shown in FIG.
The timing for writing and reading M (8) is reached,
The writing and reading timings of the RAM (8) of this embodiment are tied to the writing and reading timings of the conventional RAM (7).

In this way, instead of reading the signal of 9 lines when the video head is switched, the signal of 1 line before is read again, thereby making it possible to correct the discontinuity of the video signal that occurs when switching the video head.

Next, another embodiment of the present invention will be explained based on FIGS.
A VT that records and reproduces the (R-Y) signal and (B-Y) signal of two types of color difference signals by performing time-axis multiplexing.
The reproduced signal processing method of the present invention is used for R. Figure 5 shows the time-axis multiplexed Y signal, (RY) signal, and (B
-Y) is a diagram showing the compression relationship of signals. Figure 5 ASB,
The Y signal, (R-Y) signal, and (T-Y) signal shown in C are converted into a time-domain multiplexed signal shown in Figure 5 in a time-domain compressor.

In the case of this embodiment, the Y signal, the (RY) signal, and the (B-Y
) Signal compression ratio (8A'): (115):
(IA).

The time domain multiplexed signal is frequency modulated by a modulator and recorded on a magnetic tape. FIG. 6 is a block diagram of a reproduction thread of a VTR that reproduces time-axis multiplexed signals. In FIG. 6, components having the same functions as those in FIG. 8 are designated with the same symbol -8. 4 is a demodulator which demodulates the frequency modulated signal from the video head (1) and generates a time axis multiplexed signal [Y+(R-Y
) + (Obtain B-Y sword.

side is a synchronization signal separation circuit, (to) is a write clock generator, (6) is a control circuit, (7) ep is a D/A converter, (
2) is a read clock generator, and 2) is an output terminal, which outputs a Y signal, a (RY) signal, and a (B-Y) signal, respectively. (e) to (b) are tongs.

In FIG. 6, the transmission and reception of signals is the same as in FIG. 8, but the major difference from FIG. The clock generator ■ generates a readout clock (hereinafter referred to as R-CLOCK 1) that serves as a reference for the time axis and a readout clock for Y signal expansion (hereinafter referred to as R-CLOCK 2).
The frequency ratio of each clock is (faboak, ): (faIIoak, )
: (foLoak, )=6:8:t. FIG. 7 is a diagram showing how time axis errors and signal discontinuities due to video head switching are corrected when the reproduced signal processing method of the present invention is used in a VTR configured as described above. The signal on the (n-1)th line is R
AM (7) (E) 4 is stored, and the R11Ab signal is
- Obtain the time-coaxially expanded Y signal by reading according to CLOCK 2, RAM @ f) signal, RA
By reading the M m o signal with R-CLOCK 8 K, the time axis expanded (toY) signal, (B
-Y) Obtain the signal.

The signal of the nth line where the video head has been switched is prohibited from being written to RAM (s) @ (to) in the middle, and reading from RAM (7) (to) 4th to (nth line) is prohibited.
−1) By rereading the signal of the th line,
Discontinuous portions of the reproduced signal can be corrected.

After the (n+1)th line, the Y signal is RAM (7)
(8) (9) (R-Y) signal is RAM (e) cap book (
The B-Y) signal is obtained sequentially by writing and reading six times, and its operation is the same as in the first embodiment.

Note that the time axis expanded Y signal, (RY) signal,
(Y) It goes without saying that the time axis error of the signal has been corrected.

In this way, the Y signal, (RY) signal, and (B-Y) signal are time-axis-expanded by temporarily storing the time-axis multiplexed signals in the RAM and reading them out using the reference clock for time-axis expansion. , as in the first embodiment, instead of reading the signal of the line at the time of video head switching, the signal of one line before is read out to correct the discontinuous portion of the reproduced signal that occurs at the time of head switching. I can do it.

Note that in the first embodiment, when the phase of the color subcarrier signal is inverted line by line, such as a PAL signal, instead of reading the signal of the line where the radio head has been switched, Needless to say, all you have to do is read out the previous signal.

As described in the detailed description of the invention, the VTR reproduction value 8 processing method of the present invention is as follows:
To write the reproduced video signal of a VTR to a storage device using a write clock formed from the reproduced video signal, and when reading this using a reference read clock, instead of reading the signal of the line where the video head has been switched. Since the memory signal of several rai-J# is read out, the time axis error is corrected, and the discontinuity of the video signal that occurs when switching the video head can be corrected, which has a great practical effect. .

[Brief explanation of drawings]

Figure 1 shows a VTR that obtains a video signal with time axis errors corrected.
Figure 2 is a block diagram of a conventional playback system for the VTR shown in Figure 1.
FIG. 8 is a block diagram of the VTR playback system in the first embodiment of the present invention; FIG. 4 is a timing chart diagram for explaining the reproduction method of FIG. 8; FIG. The figure is a waveform diagram for explaining a specific second embodiment of the present invention, FIG. 6 is a block diagram of a VTR playback system in the second embodiment of the present invention, and FIG. It is a timing chart figure. (4)...Main memory device,...n-...Write clock generator, (31, lI...Control circuit, Qf9)...
・Readout 0゛Shiku generator, 4...Video head switching signal input terminal agent Yoshihiro Moriki 1st rgJ Fig. 2 Fig. 4 Fig. 5 - 4 weak

Claims (1)

[Scope of Claims] 1. When writing a reproduced video signal of a VTR to a storage device using a write clock formed from the reproduced video signal and reading it using a reference read clock, the line where the video head was switched Instead of reading out the signal of
TR reproduction signal processing method. 2. Claim 1, characterized in that the storage device performs time axis expansion of the luminance signal and color signal during reproduction of the VTR.
A method for processing a reproduced signal of a VTR as described in Section 1.