JPS61177083A - Method and apparatus for recording video signal - Google Patents

Abstract

PURPOSE:To execute efficient time base compensation at the time of reproduction by delaying a video signal in the m-th, 1/n vertical scanning period by (m-1)tau, recording the delayed signal in the m-th track and setting up a position forming a blanking period to a horizontal blanking period. CONSTITUTION:Scanning line Nos.0-139 are read out after being delayed by a prescribed time tau0 or immediately. Scanning lines Nos.140-279 are read out after being delayed by time tau (- horizontal scanning period) moreover. After reading out up to scanning line No.559, scanning lines are continuously read out from the scanning line No.563 corresponding to the 2nd field similarly to said procedure by delaying them by the time tau every block. In the time corresponding to three horizontal scanning periods delayed by forming three blanking positions in each field, the scanning line Nos.560-652 are not readout to compensate the time axis and the delay time of writing and reading is returned to the original status tau0 every appearance of the vertical blanking period.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a method for recording a video signal in a magnetic recording and reproducing apparatus such as a VTR, which divides one vertical scanning period of a video signal into a plurality of parts and records them on a magnetic tape. This is related to the device.

[Background of the invention]

A conventional example of a magnetic recording/playback device using the so-called segment recording method, in which one vertical scanning period (one field) of a video signal is divided into multiple parts and recorded on magnetic tape, is a 4-head VTR for commercial use such as broadcasting stations. Details are described in, for example, the literature (edited by Japan Broadcasting Publishing Association, Television Society, supervised by Minoru Inazu, Takashi Iwasawa, VTR Technology). In the above-mentioned segment recording type VTR, one field of the video signal is divided into multiple tracks and recorded, so during playback, so-called so-called problems that occur when switching tracks due to mounting errors of the rotating head, expansion and contraction of the tape, etc. A time axis correction circuit is essential to correct skinny (rapid changes in the time axis). As a method for correcting this skinny, as detailed in the above-mentioned document (chapter 7), in 5K, the video signal is passed through a variable delay line, etc., and its delay time is varied according to the amount of skinny. A time axis correction method is known in which the phases of a video signal and a horizontal synchronization signal are made continuous by temporally expanding or contracting the horizontal blanking period of the signal, more specifically, the front porch period immediately before the horizontal synchronization signal. It is.

According to the above conventional method, the amount of skinny that can be corrected is determined by the time width of the front porch of the video signal, and in the current television system, the skinny amount is limited to 1 to 2 μsec.

Furthermore, current home VTRs do not use segment recording as described above, and one field of the video signal is
The so-called helical scan type that records on one track is generally used, but in order to make the rotating drum smaller in diameter and make the VTR even more compact and lightweight, the number of revolutions of the rotating drum was increased. In order to improve image quality,
In addition, new VTRs that can record video signals with a bandwidth several times wider than conventional TVs, such as so-called high-definition televisions that provide significantly higher definition and higher image quality than current television systems, have also been introduced.
In order to realize this, attempts have been made to perform segment recording as described above in home VTRs as well. However, in helical scan type home VTRs, due to manufacturing constraints, the finishing precision of mechanical systems such as the rotating head system and tape transport system is not always sufficient, and the storage conditions for tapes in general homes are not always sufficient. If these factors are taken into account, the amount of skinny noise generated will amount to several μ5eck, and when compatible playback is taken into consideration, it is necessary to allow for an additional margin in the above value.

In addition, according to some of the methods proposed for the above-mentioned high-definition television, the literature (Television Society Technical Report VQL 7
．． N, 144. May 1984 i ``High Definition Television Satellite Single Channel Transmission System MULE'') As described, the horizontal blanking period allocated to the video signal is small (1 μsec or less).

Therefore, considering the actual situation of skinny generation in the above-mentioned home VTRK, even if the current TV system smells bad, and even in the above-mentioned high-definition TV system, the above-mentioned conventional method
It is extremely difficult to completely remove skew;
It has been difficult to put into practical use a VTR that achieves the above objectives.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems and to perform segment recording of a video signal with an extremely short horizontal blanking period.
It is an object of the present invention to provide a video signal recording method and an apparatus therefor, which enable good time axis correction during reproduction also in TR.

[Summary of the invention]

For the above purpose, in the present invention, - vertical scanning periods are set n times (n
The following five recording methods are used in a segment type helical scan type VTR that records data by dividing it into tracks (integer greater than or equal to 2).

Based on the appropriately determined position of the vertical blanking period of the video signal, the video signal of the first vertical scanning period is recorded on the first track, and the video signal of the second vertical scanning period is recorded. , is delayed by a time τ corresponding to one horizontal scanning period sufficient to correct the skinny, that is, after providing a blanking period of time τ, the recording is completed in the second trunk. Generally speaking, the video signal of the m-th (an integer where m≦n) dodari scanning period is delayed by (m-1)τ and then recorded on the m-th track. The position where the blanking period is provided is the horizontal blanking period.

When the above operation buttons are pressed, the video signal is delayed by a maximum of (n-1) τ within one vertical scanning period compared to the input original signal. Although the video signal is delayed by a maximum of (n-1)τ, by shortening the vertical blanking period, it is possible to perform the above-mentioned time delay operation without missing transmitted information.

During playback, the head is switched during the blanking period thus provided, and by removing the provided blanking period, a series of signals can be obtained and a signal without human skew distortion can be reproduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to a block diagram of a blanking processing circuit shown in FIG. 1 and a timing diagram shown in FIG. 2.

In FIG. 1, 10 is an input terminal for a video signal, 11 is an input terminal for a check signal; 12 is an output terminal for a blanked video signal, 20 is an A/D conversion circuit, 30 is a memory, and 41 is a writing terminal. 42 is a read address generation circuit; 50) is a synchronization information separation circuit; 75 is a blanking level setting circuit for setting a signal level during the blanking period; and 80 is a D/A conversion circuit.

The video signal input from the terminal 10 is sent to the A/D conversion circuit 20.
is input. A clock signal whose phase is synchronized with the horizontal synchronization information of the video signal is inputted from the terminal 11. The clock signal input from the terminal 11 is sent to the A/D conversion circuit 20.
is input. Based on this clock signal, the video signal is converted from an analog signal to a digital signal. A/D
The digital video signal I)V, which is the output signal of the transformation circuit 20, is input to the memory 30.

On the other hand, the video signal input from the terminal 10 is input to the synchronization information separation circuit 50. Then, the signal V is separated and output based on the signal date based on the horizontal synchronization information and the vertical synchronization information.

The horizontal synchronization information H1, vertical synchronization information V, and the clock signal input from the terminal 11 are respectively written and output.
Address generation circuit 41, read address generation circuit 42
is input. The write address generation circuit 41 and the read address generation circuit 42 are composed of a counter circuit or a ROM that generates a predetermined address. In either case, it is reset with a signal based on the vertical synchronization information V, and a predetermined address is generated by counting the water synchronization information H and the clock signal. The address signal WAD generated by the address generation circuit 41 is input to the memory 30, and the digital video signal DV is sent to the memory 3.
0 at a predetermined location. Further, the address signal RAD generated by the read address generation circuit 42 is also input to the memory 30, and the video signal stored in the memo 1J30 is read after being delayed for a predetermined time.

FIG. 2 is a timing chart showing the timing of loading and reading video signals into the memory 30. Figure @2 shows, as an example, the number of scanning lines per frame: 1125 (scanning line numbers 0 to 1124) when a 2:1 interlaced video signal is recorded in 4 segments on a 2-head helical scan type VTR. A timing diagram is shown. Vertical synchronization information is provided for each field, i.e. 2 per frame.
It is assumed that vertical synchronization information has been entered. Therefore, one frame of signal is divided into eight tracks and recorded, and approximately 140 scanning lines are allocated to each track. In order to eliminate the skinny caused by head switching, a blanking period is provided at each predetermined position in the vicinity of about 140 scanning lines in the horizontal blanking period based on the vertical synchronization information.

FIG. 2 (1) shows the write timing to the memory 30,
(2) indicates the reading timing. Mo and Wl
indicates that the signal of scanning line number 1 is written to the memory 30, and R1 indicates that the signal of scanning line number 1 is read from the memory 30. Further, blanking for head switching is indicated by diagonal lines in FIG. 2(2).

As shown in FIG. 2(1), video signals are sequentially and cyclically written into the memory 30. Reading from the memory 30 is performed as shown in FIG. 2 (2). The predetermined time τ is for scanning line numbers 0 to 139. It may be read after a delay (one horizontal scanning period in FIG. 2) (which need not be equal to the time τ of the blanking period) or immediately. Scanning line numbers 140 to 279 are read with a further delay of time τ (one horizontal scanning period). Therefore, a blanking period of time τ occurs between scan line numbers 139 and 140. Thereafter, each block recorded on one track is read with a further delay of time τ, thereby creating a blanking period of time τ between scanning line numbers 279, 280, 419, and 42C1).

After reading up to scanning line number 559, reading continues from scanning line number 563 corresponding to the second field with a delay of time τ for each block in the same manner as described above.

The deleted scanning line numbers 560 to 562 are set so that no video information is superimposed within the vertical blanking period, and the positions do not include vertical synchronization information to avoid the effects of scanning line deletion. K. In addition, the time for 4 seconds in the 3 horizontal scanning periods delayed from K to blank 3 places per field is for the above scanning line numbers 560 to 56.
2 by not reading, and each time a vertical blanking period appears, the write and read delay time is set to the initial state τ. Return to.

The following reading is performed in the same way, and a blanking period is set at a predetermined position counted from the vertical synchronization information near the head switching position.The reading time delay corresponding to 3 horizontal scanning periods due to the provision of the blanking period is By deleting scan line numbers 1122 to 1124 within the vertical blanking period, the write and read delay time within the vertical blanking period is compensated for to the initial state τ. Return to.

Although no blanking period is provided between scanning line numbers 559, 563.1121, and 0, a vertical blanking period may be set in this vicinity.

The video signal read from the memory 30 as described above is input to the blanking level setting circuit 75. The blanking level setting circuit 75 also includes a signal BL indicating the blanking position generated by the read address generation circuit.
is also entered. After setting the signal level of the signal BLK image and the blanking period to a predetermined level, the image signal is converted to D/D.
The signal is input to the A conversion circuit and output from the terminal 12 as an analog signal with a blanking period.

The position where the blanking period is provided need not be limited to the example shown in FIG. 2, but may be within the overlap period in which the two heads are in simultaneous contact with the tape.

Furthermore, the number of scanning lines and the number of segments are not limited to those shown in Figure 2; in any case, the blanking periods should be set so that the position is within the overlap period and the intervals between the blanking periods are approximately equal. Good.

The clock signal input from the terminal 11 is phase-synchronized with the horizontal synchronization information of the video signal input from the terminal 10.

This clock signal may be generated by a conventionally known PLL circuit, or a method may be used in which the phase of the clock signal is reset using horizontal synchronization information and phase synchronization is performed for each horizontal synchronization information.

FIG. 3 is a waveform diagram of various parts when a video signal is recorded and reproduced in a two-head helical scan type VTR using the four-segment recording system. - FIG. 3(1) shows the video signal waveform that is also input to the terminal 10 in FIG. 1, and the shaded area shows the position of the vertical synchronization information V. Further, the blanking period immediately before the vertical synchronization information V indicates the vertical blanking period. In Figure 3, the vertical blanking position or its signal is
Indicated by LK.

By passing the video signal shown in FIG. 3(1) through the circuit shown in FIG. 1, three blanking periods for head switching can be provided for each field. The position of the blanking period or the signal of that period is indicated by HBLK. FIG. 3(2) shows the output signal of the above circuit.

The video signal subjected to the blanking process shown in FIG. 3(2) is recorded on a VTR, and the reproduced waveform reproduced by each head is shown in FIG. 3(5), +41. Blanking position HB
By alternately switching the heads for LK and VBLK and selecting the head from which the signal is being reproduced, a series of reproduced video signals shown in FIG. 5(6)K is obtained. Blanking position H
BLK.

Since the head is switched only by VBLK, there will be no loss or discontinuity of the video signal. FIG. 3 (5) shows a control signal for controlling head switching, and shows the control signal for controlling head switching.
Head switching is performed using LK and VBLK.

The series of reproduced video signals shown in FIG. 4 (611C) includes a blanking signal HBLK, so by removing this blanking signal HBLK, the same reproduced video signal as the original video signal without skew can be obtained. Obtainable.

FIG. 4 is a block diagram of a circuit that corrects a time axis error occurring in the VTR recording/reproduction process and simultaneously removes the blanking signal HBLK, and a circuit that generates the head switching signal shown in FIG. 3 (5).

In FIG. 4, 110 is an input terminal for the reproduced video signal shown in FIG. 113 is an output terminal for a head switching signal, 114 is an input terminal for a stable reference clock signal RCK, 115 is an output terminal for vertical synchronization information generated from the reference clock signal RCK, 120 is an A/D conversion circuit , 130 is memory, 141
142 is a read address generation circuit, 150 is a synchronization information separation circuit, and 180 is a D/
A conversion circuit 190 is a reference synchronization signal generation circuit.

A video signal (FIG. 5, 16) inputted from the terminal 110 is inputted to an A/D conversion circuit 120 and a synchronization information separation circuit 150. The write clock signal WCK input from the terminal 111 is input to the A/D conversion circuit 120, and the video signal is sampled using the write clock signal WCK to become a digital signal, and this digital video signal is input to the memory 130. do.

On the other hand, the synchronization information separation circuit 150 separates and outputs a signal PH based on the horizontal synchronization information and a signal PV based on the vertical synchronization information from the input 4-way signal. Reproduction horizontal synchronization information PH, reproduction vertical synchronization information Pv, and write clock signal WCK are input to write address generation circuit 141. The write address generation circuit 141 counts the reproduction horizontal synchronization information PH based on the reproduction vertical synchronization information Pv,
Address control is performed so that the blanking signal HBLK is not written into the memory 130. Furthermore, a write address signal is generated by counting the busy write clock signal WCK, and the write input address signal is input to the memory 130, and a digital video signal is written in accordance with the address value. In this state, the blanking signal HBLK for head switching is removed and the digital video signal is continuously stored in the memory 160.
It would have been written in.

Next, reading from memory 130 will be explained. The reference clock signal RCK input from the terminal 114 is sent to the reference synchronization signal generation circuit 190 and the read address generation circuit 1.
42. The reference synchronization signal generation circuit 190 generates stable vertical synchronization information R and V serving as a reference based on the reference clock signal BeK. The vertical synchronization information FLv is input to the read address generation circuit 142, which generates a read address signal to the memory 130 by counting the reference clock signals R and CK based on the vertical synchronization information R and V, and continuously Reads and reads digital video signals.

The blanking signal HBLK for head switching has already been removed from the video signal read from the memory 130. This digital video signal is converted into a D/A conversion circuit 180.
The signal is converted into an analog signal and output from the terminal 112. Through the above operations, a video signal without skew distortion can be output from the terminal 112.

On the other hand, the head switching signal shown in FIG. Based on the reproduction vertical synchronization information PV, the reproduction water 7 weighing period information PH is counted, and a signal whose state is inverted at the blanking position HBLK for head switching set in the circuit shown in FIG. 1 is generated and output from the terminal 113. do. Terminal 113 is a VTR
(not shown), and the VTR and reproduction system alternately select the signals reproduced from each head according to the head switching signal described above, as shown in Fig. 3 (6).
We obtain the series of signals shown in .

As the write clock WCK input from the terminal 111, a clock signal generated in instantaneous phase synchronization with the horizontal synchronization information of the video signal input from the terminal 110 is used,
Read/read clocks R, CK input from terminal 114
By using a stable lock signal generated by a crystal oscillator or the like, it is possible to remove the blanking signal HBLK and at the same time correct time axis errors such as jitter.

Skiing - The maximum amount of generation is a few μs for general home VTRs.
ec, and considering the skew amount, it is sufficient to set the blanking period τ to be the time of one horizontal travel period. Furthermore, the head switching position can be reliably performed within the blanking period of one horizontal scanning period by counting the horizontal synchronization information.

Considering the periodicity of the swimmer synchronization information, it is optimal to set the blanking period τ to one horizontal scanning period.

Note that the reference vertical synchronization signal KV from the reference synchronization signal generation circuit 190 shown in FIG. 4 is outputted via the terminal 115 as a reference signal to a servo control device (not shown).

This servo control device controls the relative phase between the head and the magnetic tape to correctly reproduce signals in a VTR that applies a blanking signal removal device that also serves as a time axis error correction device based on the embodiment shown in FIG. 4 above. It is composed of a tracking control system and the like for the purpose of achieving this, and a conventionally known system is used. By inputting the basic vertical synchronizing signal RV from the terminal 115 to this servo control device, the terminal 1
The input video signal from 10 is the reference vertical synchronizing signal R, V.
is servo controlled to be phase synchronized with.

Next, another embodiment of the blanking processing circuit of the present invention will be described in the fifth embodiment.
This will be explained using the block diagram shown in the figure. Parts of FIG. 5 are the same as those of FIG. 1, and the common parts are designated by the same reference numerals and detailed explanation thereof will be omitted.

In FIG. 5, 31.32 is a memory, 40 is the above-mentioned memory, and an address generation circuit that specifies the storage location of 32.
60 is a W/R control circuit for controlling writing, reading and reading of the memo 1731.32, and 70 is a selection circuit for signals read from the memo 1J31.32.

The video signal input from the terminal 10 is sent to the A/D conversion circuit 20.
is input. The A/D conversion circuit 20 samples the clock signal input from the terminal 11 and converts the video signal from an analog signal to a digital signal. Digital video signal DV which is an output signal from the A/D conversion circuit 20
is input into the memory 61°32.

10,000, the video signal input from the terminal 10 is input to the synchronization information separation circuit 50, and the signal H1 based on the horizontal synchronization information (signal V) is separated and output based on the vertical synchronization information. H and vertical synchronization information V are input to the W/R, control circuit consisting of a kakunta circuit, etc., and the W/R,
The control circuit outputs control signals WR1 and WR2 for controlling the write and read modes of the memories 51 and 52, as shown in FIG.

Further, the clock signal inputted from the terminal 11 is inputted to the address generation circuit 40, and the storage position of the digital video signal DV inputted to the memory 31.52 and the memo I73 are inputted to the address generation circuit 40.
1.32, an address signal AD is generated which specifies the read position when reading the digital video signal DV.

Memo +731.32 contains the digital video signal D mentioned above.
V, write/read control signals WR1, V12, and address signal AD are input as shown in FIG. 5, respectively. The digital video signal DV is sent to the memory 3 according to the write/read control signals WR1, WRz and the address signal AD.
1.32, the signal is read after a blanking period, the selection circuit 70 selects the signal from the memory in read mode, and the signal is input to the D/A conversion circuit 80 via the blanking level setting circuit 75. , which is converted into an analog video signal and then outputted from the terminal 12 as a blanked video signal.

6+11 and 121 are timing diagrams showing the process of writing, reading and blanking the digital video signal DV in the memories 31 and 32, respectively.

Wl indicates that the video signal of scanning line number 1 is written, and R1 indicates that the video signal is read. In Figure 6, the number of scanning lines in one frame is 1125 (scanning line numbers 0 to 112).
4), and the case where 4 segments are recorded will be illustrated.

In the first field, signals with horizontal scanning numbers 0 to 561 are divided into four tracks and recorded, and in the second field, signals with horizontal scanning numbers 562 to 1124 are divided and recorded into four tracks.

In the first track of the first field, signals of horizontal scanning line numbers O to 140 are recorded.
2+1 Figure 6+1), +21 shows Wl, W2,...
・Digital video signals DV are stored alternately. Therefore, the memory 31 stores signals of odd-numbered scanning lines, and the memory 32 stores signals of even-numbered scanning lines. Also, read Figure 6+11. R1 shown at +21
, R2, . . . are carried out alternately starting from both the scan lines 31, 32, and moreover, immediately after the signal for one scanning line is written, the signal is read. Memo 1J50.3
The output signals of 1 are input to the selection circuit 70, and are alternately selected every horizontal scanning period to produce the original series of signals.

The second track has horizontal scan line numbers 141-280.
The signals up to the point are recorded. Up to horizontal scanning line number 140, each scanning line is stored alternately in the memo 1751.32, but from scanning line number 141, two scanning lines are stored according to W 141 , W 142 , - shown in FIG. 6(1), +21. memorize each time alternately. Also, read Figure 6 11 +, +
Both memories 51 and 5 according to R141 and R142 shown in 2)
This is done alternately every 2 to 2 scan lines, and the signals for two scan lines are read immediately after being written. Therefore, the time between scanning line numbers 140 and 141 corresponds to one horizontal scanning period.

The signal is not read and a blanking period is created.

Similar operations are performed for the third and fourth tracks as well.

The third track has horizontal scan line numbers 281-421.
In the fourth track, signals of horizontal scanning line numbers 422 to 557 are recorded. Memo IJ3L
Writing to 32 is performed alternately every three scanning lines from scanning line number 281, and every four scanning lines from scanning line number 422. Reading is done in 3 scans from scan line number 281,
This is done line by line, alternating every fourth scan line starting from scan line number 422, and immediately after the third and fourth scan lines have been stored, respectively. Therefore, scan line numbers 280 and 281
Between 421 and 422, no signal is read for a time corresponding to one horizontal scanning period, creating a blanking period.

Regarding scanning line numbers 558 to 561, four scanning lines are also continuously stored in the memory 32. However, horizontal scan line number 562
~1124 becomes the second field, with scan line number 56
From 2 onwards, each scanning line is stored in memo 1J31.32 again. Therefore, Fig. 6(1).

As shown in (2), scanning line 558 is read, but scans #J559 to #J561 are deleted. Note that if the vicinity of the scanning lines 559 to 561 is set to be a vertical blanking period, no video content will be lost even if the scanning lines 559 to 561 are deleted.

By performing a similar operation in the field of cylinder 2, blanking periods for head switching can be provided almost periodically. Although there is no blanking period between the 4th track and the 1st track of the next field, this part is a vertical blanking period, and the video signal is superimposed and the skew due to There will be no impact.

In the block diagram of the embodiment shown in FIG. 5, the W/R control circuit 60 can be constructed from a commonly used counter circuit. The W/R control circuit 60 receives vertical synchronization information V
By counting the horizontal synchronization information H, the signal having the timing shown in FIG. 6 is output. Alternatively, it can also be created using ROM. In this case as well, by resetting with the vertical synchronization information V and counting the horizontal synchronization information H, it is possible to easily output a signal with the timing shown in FIG.

In the embodiment shown in FIG. 5, the storage capacity required for the memo 1731.32 is equivalent to the amount of information for four horizontal scans in five minutes from the timing diagram shown in FIG. If the method shown in FIG. 5 is used, it is possible to configure it with two memories each having a capacity for four horizontal scanning lines.

In addition, since the blanking period τ is one horizontal scanning period, the memory capacity can be minimized, and the memory write address circuit and read address circuit can be shared, which has the effect of making it possible to downsize the circuit. be.

The blanking level setting circuit 75 shown in FIGS. 1 and 5 sets the blanking level to a predetermined level. The level of the blanking period may hold the value immediately before the blanking period.

If it is set so that it is always at a predetermined level, clamping can be performed using the blanking period. This is especially effective when the horizontal blanking period is extremely short and there is not enough time to perform sufficient clamping.

In addition, if the clamp level is set to a gray level instead of a pedestal level, even when the S/N ratio is insufficient and a large level of noise is superimposed, a margin is given to the threshold for separating synchronization information, and the noise causes synchronization. This has the effect of making it difficult to mistakenly separate it from information.

Furthermore, the MUSB signal, which is one of the high-definition television signals mentioned in the above-mentioned literature, has a luminance signal and a chromaticity signal multiplexed on the time axis, and the synchronization signal is also a so-called positive synchronization signal within the video signal level. There is. Moreover, the horizontal blanking period is short. When such a high-definition television signal is recorded and reproduced on a direct segment recording type VTR, the phase of the positive synchronization signal becomes discontinuous in the segment portion, making it impossible to separate the positive synchronization signal using periodicity.

It is possible to separate the synchronization information by compressing the time axis of the high-definition television signal in one horizontal scanning period and inserting negative polarity synchronization information or a burst signal into the resulting no-signal period. When a blanking period is provided in the high-quality television signal, it is possible to perform synchronization insertion and blanking processing by time axis compression by simply changing a part of the circuit block diagram shown in FIG.

In FIG. 1, the same clock signal input from the terminal 11 is used as the clock signal for the write address generation circuit 41 and the read address generation circuit 42. When compressing the time axis, the clock signal of the write address generation circuit 41 and the clock signal of the read address generation circuit 42 are separated, and the high frequency clock signal generated in synchronization with the clock signal of the write address generation circuit 41 is read. This is used as a clock signal for the address generation circuit 42. Therefore, signals are read from the memory 30 intermittently every horizontal scanning period. Note that when the synchronization information is read in a period other than one horizontal scanning period, for example, in two horizontal scanning periods, reading is also performed intermittently according to the period of &97.

The blanking for head switching may be inserted into the high-definition television signal at the same position as the synchronization information to be added, between the positive synchronization information and the chromaticity signal, between the chromaticity signal and the luminance signal,
Any one between a luminance signal and a positive synchronization signal may be used.

Furthermore, in order to expand the time-base compressed signal and remove the blanking period, the frequency of the write clock signal WCK shown in FIG. 4 may be increased. In this case, the button writes intermittently to the memory 130 except for the added synchronization information and burst signal.

As described above, the present invention can also be applied to high-definition television signals.

〔Effect of the invention〕

According to the present invention, even when recording a video signal with an extremely short horizontal blanking period using the segment recording method VTR+, it is possible to record a video signal with a very short horizontal blanking period by using the segment recording method VTR+. A margin is obtained, and signal loss and discontinuity on the reproduced image caused by skew can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a Plan Young processing circuit showing an embodiment of the present invention, FIG. 2 is a timing diagram thereof, FIG. 3 is a waveform diagram when a video signal subjected to blanking processing is reproduced with VTRK recording, and FIG. 4 is a block diagram of the blanking removal circuit, FIG. 5 is a block diagram showing another embodiment of the blanking processing circuit, and FIG. 6 is its timing diagram.
1.32...Memory, 40...Address generation circuit, 41...Write/leave address generation circuit, 42...Read address generation circuit, 60...W/R control circuit, 70... Selection circuit, 75...Blanking level setting circuit.

Claims (1)

[Claims] 1. Video in a rotary head magnetic recording and reproducing device that divides one vertical scanning period of a video signal into n (n is an integer of 2 or more) tracks and sequentially and cyclically records them on a magnetic tape. In the signal recording method, the rotary head is composed of a plurality of heads, at least two of the heads have overlapping areas in which they simultaneously contact the magnetic tape, and the rotating head is configured to record signals from a predetermined line in a vertical blanking period of the video signal. A video signal of a first block divided to include a predetermined number of lines is divided into a video signal of a second block subsequent to the first block divided to include a predetermined number of lines for a time corresponding to one horizontal scanning period. Delayed by τ, and thereafter similarly divided to include a predetermined number of lines (m-1) (m is an integer of 2 or more)
For the video signal of the block, the video signal of the m-th block divided to include a predetermined number of lines following this is delayed by the above time, and the above delay operation is repeated every vertical scanning period of the video signal. A method for recording a video signal, characterized in that the above-mentioned overlapping area includes the blanking period between each block obtained by the above-mentioned delay operation. 2. A video signal recording method according to claim 1, characterized in that the blanking period is recorded at a constant level. 3. A synchronization information separation circuit that outputs a signal based on vertical synchronization information and a signal based on horizontal synchronization information included in the video signal, and a predetermined memory that samples the video signal and can be written or read sequentially for each sample value. a memory having a capacity, a write clock generation circuit that generates a write clock synchronized with the video signal, means for sequentially writing the video signal into the memory in accordance with an output of the write clock generation circuit, and the write clock generation circuit. Means for sequentially reading the video signal written in the memory according to the output from the circuit or a read clock generated in synchronization with the output, and means for supplying the output from the synchronization information separation circuit to the writing means. and means for counting the horizontal synchronization information based on the vertical synchronization information, and means for controlling reading start, continuation, and stop of the reading means according to the output of the counting means, and separating the synchronization information. Writing is sequentially and cyclically from a predetermined position in the memory according to the output from the circuit, and a blanking period of one horizontal scanning period is generated from the memory between blocks of the video signal according to the output from the control means. A video signal recording device characterized in that the signal read in the above manner is recorded on the magnetic tape.