JP3259324B2 - Digital signal recording device and reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording and reproducing digital audio signals on a magnetic tape by using a rotating magnetic head.

[0002]

2. Description of the Related Art Conventionally, digital V of D1 format
There have been proposed various VTRs capable of simultaneously recording and reproducing a digital video signal and a digital audio signal on a tape, such as a TR and a D2 format digital VTR.

[0003]

In such a VTR, a digital video signal and a digital video signal are recorded on a tape together with a digital audio signal even when there is no change in an image or when sound is more important than an image such as speech. Since recording is performed, there is a disadvantage that the tape is wasted.

In view of the above, the present invention provides a digital signal recording apparatus and a digital signal recording / reproducing apparatus capable of recording and reproducing a digital audio signal while consuming less tape.

[0005]

According to the first aspect of the present invention,
In the first mode, the tape is continuously run, and a digital video signal and a digital audio signal are applied to the tape.
Are simultaneously recorded using a predetermined recording section , and in the second mode, the tape is run intermittently and only digital audio signals for a predetermined period are recorded on the tape in each running period.
Is recorded using a predetermined recording section .

According to a second aspect of the present invention, a digital video signal and a digital audio signal are simultaneously recorded in a predetermined recording area.
When playing back a tape having a first mode portion recorded using a time interval and a second mode portion recording a digital audio signal using a predetermined recording section , the tape is continuously played back in the first mode portion. The digital video signal and the digital audio signal are reproduced by running, and the digital audio signal is reproduced by intermittently running the tape in the second mode portion.

According to a third aspect of the present invention, a digital video
Signal and digital audio signal recorded simultaneously
Mode part and digital audio signal recorded
When playing a tape having the second mode portion,
When playing back the mode part of 1, the tape is continuously
Run the digital video signal and digital audio
When playing back the audio signal and playing back the second mode part
Then, the tape is run intermittently and the digital audio
A signal is reproduced and the second mode part is changed to the first mode.
When the digital audio signal is continued after the digital video signal, the last digital video signal reproduced from the first mode part is output as a still picture video signal while the digital audio signal is being reproduced.

[0008]

According to the first aspect of the present invention, in the second mode, the tape is intermittently run and a digital audio signal for a predetermined period is recorded on the tape in each running period, so that consumption of the tape is suppressed. Digital audio signals can be recorded for a long time.

According to the second aspect of the present invention, in the second mode portion, the digital audio signal is reproduced by intermittently running the tape, so that the digital audio signal can be reproduced for a long time while consuming less tape. Become.

[0010] According to the third aspect of the invention, the second aspect is provided.
In addition to obtaining the same operation as the described invention, while reproducing the digital audio signal from the second mode portion, a still image based on the last digital video signal reproduced from the first mode portion is displayed. It becomes possible.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital VTR according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration on the recording side as a whole. Input terminals 1Y, 1U, and 1V are supplied with a digital luminance signal Y and digital color difference signals U and V formed from three primary color signals R, G, and B from a color video camera, for example. In this case, the clock rate of each signal is 13.5 MHz and 6.75 MHz, respectively, similarly to the frequency of each component signal in the well-known D1 format. The number of bits per sample is 8 bits. Therefore, the data amount of the video signal supplied to the input terminals 1Y, 1U, and 1V is about 216 Mbps. The data in the blanking period is removed from the video signal, and only the information in the effective area is extracted from the effective information extracting circuit 2.
And the data amount is compressed to about 167 Mbps.

The luminance signal Y output from the effective information extraction circuit 2 is supplied to a frequency conversion circuit 3, and the sampling frequency is converted from 13.5 MHz to 3/4 of the frequency. For example, a thinning filter is used as the frequency conversion circuit 3 so that aliasing distortion does not occur. The output signal of the frequency conversion circuit 3 is supplied to the blocking circuit 5, and the order of the luminance data is converted into the order of the blocks.
The blocking circuit 5 is provided for a block coding circuit 8 provided at a subsequent stage.

FIG. 3 shows a block structure of a unit of encoding. This example is a three-dimensional block, for example, 2
By dividing the screen spanning the frames, a large number of (4 lines × 4 pixels × 2 frames) unit blocks are formed as shown in FIG. In FIG. 3, a solid line indicates an odd field line, and a broken line indicates an even field line.

Returning to FIG. 1, the color difference signals U and V output from the effective information extraction circuit 2 are supplied to a sub-sampling and sub-line circuit 4, and after the sampling frequency is converted from 6.75 MHz to half thereof, respectively. Two digital color difference signals are alternately selected for each line and are combined into one channel of data. Therefore, the sub-sampling and sub-line circuit 4 provides a line-sequential digital color difference signal. FIG. 4 shows a pixel configuration of a signal sub-sampled and sub-lined by the circuit 4. In FIG. 4, “○” indicates a sampling pixel of the first color difference signal U, “△” indicates a sampling pixel of the second color difference signal V, and “×” indicates a position of a pixel thinned out by sub-sampling. Is shown.

Sub-sampling and sub-line circuit 4
Are output to the blocking circuit 6. In the blocking circuit 6, similarly to the blocking circuit 5, the color difference data in the scanning order of the television signal is converted into the data in the block order. In this blocking circuit 6, as in the blocking circuit 5, the color difference data is (4 lines × 4).
It is converted into a block structure of (pixel × 2 frames). Output signals of the blocking circuits 5 and 6 are supplied to a synthesis circuit 7.

In the synthesizing circuit 7, the luminance signal and the chrominance signal converted in the block order are converted into one-channel data, and the output signal of the synthesizing circuit 7 is
Supplied to The block coding circuit 8 includes a coding circuit (referred to as ADRC) adapted to a dynamic range of each block, a DCT (Discret
e Cosine Transform) circuit or the like can be applied. An output signal of the block encoding circuit 8 is supplied to a framing circuit 9 and is converted into data having a frame structure. The framing circuit 9 switches between the image system clock and the recording system clock.

A digital audio signal is supplied from an input terminal 1 A and supplied to an audio encoding circuit 15. In the audio encoding circuit 15, the data amount of the audio data is compressed by the DPCM. The output data of the audio encoding circuit 15 is supplied to the framing circuit 9 and is converted into a frame structure together with the block-encoded video data. The audio data supplied to the framing circuit 9 is real-time in the sense related to the video data.

An output signal of the framing circuit 9 is supplied to an error correction code parity generation circuit 10 to generate an error correction code parity. The output signal of the parity generation circuit 10 is supplied to the mixing circuit 14. The output signals of the parity generation circuits 16 and 17 are supplied to the mixing circuit 14, respectively. The parity generation circuit 16 generates an error correction code parity for the output data of the audio encoding circuit 15. At the time of the first recording,
The audio data supplied to the framing circuit 9 and the audio data supplied to the parity generation circuit 16 are the same. In the parity generation circuit 17, an error correction encoding process is performed on the sub data from the input terminal 1S, and a parity is generated.

In the mixing circuit 14, data in which these video data, audio data, and sub-data are inserted are formed at predetermined positions of one segment described later. The output signal of the mixing circuit 14 is supplied to the channel encoder 11, where channel coding is performed to reduce the low-frequency portion of the recording data. The output signal of the channel encoder 11 is supplied to the mixing circuit 18. A pilot signal for ATF (automatic track following control) is supplied to the mixing circuit 18 from an input terminal 19. This pilot signal is a low-frequency signal that can be separated in frequency from recording data. The output signal of the mixing circuit 18 is
A and 12B are supplied to magnetic heads 13A and 13B via a rotary transformer (not shown), and are recorded on a magnetic tape.

By the above-described signal processing, the input data amount 216 Mbps can be reduced to about 1 by extracting only the effective scanning period.
It is reduced to 67 Mbps and further reduced to 84 Mbps by frequency conversion and sub-sampling, sub-line. This data is compressed to about 25 Mbps by compression coding in the block coding circuit 8, and after adding additional information such as parity and audio signals, the recording data amount becomes about 31.56 Mbps. .

Next, FIG. 2 shows the configuration of the reproducing side as a whole. Reproduction data from the magnetic heads 13A and 13B is supplied to a rotary transformer (not shown) and a reproduction amplifier 21.
A, 21B and channel decoder 22 and ATF
Each is supplied to a circuit 34. Channel decoder 22
Demodulation of channel coding is performed, and an output signal of the channel decoder 22 is output to a TBC circuit (time axis correction circuit) 2
3 is supplied. The TBC circuit 23 removes the time axis fluctuation component of the reproduction signal. The ATF circuit 34 generates a tracking error signal from the level of the beat component of the reproduced pilot signal, and this tracking error signal is supplied to, for example, a phase servo circuit of a capstan servo (not shown). The operation of such an ATF basically consists of 8
This is the same as that used in the mmVTR.

The reproduced data from the TBC circuit 23 is ECC
The signals are supplied to the circuits 24, 37 and 39, where error correction using an error correction code and error correction are performed. EC
The C circuit 24 performs error correction and error correction on video data, the ECC circuit 37 performs error correction and error correction on audio data recorded in the audio-only section, and the ECC circuit 39 corrects and corrects sub data error. Error correction is performed.
The output signal of the ECC circuit 37 is supplied to an audio decoding circuit 38, and the audio signal is compressed and decoded. The decoded data of the audio decoding circuit 38 is
6. Reproduced sub data is taken out from an output terminal 33S of the ECC circuit 39. The sub-data is supplied to a system controller (not shown) for controlling the operation of the entire VTR. ECC circuit 24
Is supplied to the frame decomposition circuit 25.

Each component of the block coded data of the video data is separated by the frame decomposition circuit 25, and the clock of the recording system is switched to the clock of the image system. Each data separated by the frame decomposing circuit 25 is supplied to the block decoding circuit 26, and the original data and the restored data corresponding to each block are decoded. In the frame decomposition circuit 25, the audio data is separated, and the audio data is supplied to the audio decoding circuit 35, and decoded data corresponding to the original audio data is obtained. The decoded audio data is supplied to the synthesis circuit 36. In the synthesizing circuit 36, the two input audio signals are synthesized by switching or crossfading.

The decoded data of the image data from the block decoding circuit 26 is supplied to a distribution circuit 27. In the distribution circuit 27, the decoded data is separated into a luminance signal and a color difference signal. The luminance signal and the chrominance signal are converted by the block decomposition circuit 28,
29. Block decomposition circuit 28, 2
In 9, the decoded data in the block order is converted in the order of raster scanning, contrary to the blocking circuits 5 and 6 on the transmission side.

The decoded luminance signal from the block decomposition circuit 28 is supplied to an interpolation filter 30. In the interpolation filter 30, the sampling rate of the luminance signal is 3fs to 4fs.
(4fs = 13.5 MHz). The digital luminance signal Y from the interpolation filter 30 is taken out to an output terminal 33Y.

On the other hand, the digital color difference signals from the block separation circuit 29 are supplied to a distribution circuit 31, and the line-sequentialized digital color difference signals U and V are separated into digital color difference signals U and V, respectively. The digital color difference signals U and V from the distribution circuit 31 are supplied to an interpolation circuit 32 and interpolated. The interpolating circuit 32 interpolates the thinned-out line and pixel data using the restored pixel data. The interpolating circuit 32 obtains digital color difference signals U and V having a sampling rate of 4 fs.
U and 33V respectively.

Next, a specific configuration of the framing circuit 9 will be described with reference to FIG. In the figure, audio data DA output from the audio encoding circuit 15 is supplied to a movable terminal of a changeover switch 41. The changeover switch 41 is connected to the n side in the normal mode, and is connected to the a side in the audio mode. Audio data obtained on the n side of the changeover switch 41 is stored in a memory 42.
a and 42b are supplied as write data.

These memories 42a and 42b have a capacity enough to store audio data for one frame period. A write enable signal WEAa and a read enable signal REAa are supplied to the memory 42a, and a write enable signal WEAb and a read enable signal REAb are supplied to the memory 42b. Then, in a certain frame period, the memory 42a is in a write state and the memory 42b is in a read state, and in a subsequent frame period, the memory 42a is in a read state and the memory 42b is in a write state.

The audio data output from the memories 42a and 42b are supplied to fixed terminals a and b of the changeover switch 43, respectively. The changeover switch 43 is connected to the side a during the frame period when the memory 42a is in the read state, and is connected to the side b during the frame period when the memory 42b is in the read state. The audio data output from the changeover switch 43 is supplied to a framing circuit 44.

The audio data obtained on the a side of the changeover switch 41 is supplied to a fixed terminal on the a side of the changeover switch 46 via a FIFO memory 45 constituting a clock change circuit from an audio system to a video system. .
The FIFO memory 45 has a write enable signal WE
F is supplied (shown in FIG. 6E), and a read enable signal REF is supplied (shown in FIG. 6F). FI
In the FO memory 45, writing and reading operations are performed in the audio mode. That is, in the audio mode, the audio data is sequentially written in synchronization with the audio system clock, and the audio data for that period is read out every predetermined period in synchronization with the video system clock.

Video data DV output from the block encoding circuit 8 is supplied to a fixed terminal on the n side of the changeover switch 46. The changeover switch 46 is connected to the n side in the normal mode, and is connected to the a side in the audio mode. The output data of the changeover switch 46 is stored in the memory 4
7a and 47b are supplied as write data. These memories 47a and 47b have a capacity enough to store video data for one frame period. Memory 4
A write enable signal WEVa and a read enable signal REVa are supplied to 7a (shown in FIGS. 6A and 6B), and a write enable signal WEVb is supplied to the memory 47b.
And a read enable signal REVb are supplied (shown in FIGS. C and D).

In the normal mode, the memory 47a is in a write state and the memory 47b is in a read state in a certain frame period, and in the subsequent frame period, the memory 47a is in a read state and the memory 47b is in a write state. Is done.

On the other hand, in the audio mode, first, the memory 47a is intermittently set to the write state corresponding to the period in which the FIFO memory 45 is in the read state, and audio data for a predetermined period is sequentially written in each write state. When the audio data for one second is written to the memory 47a, the FIFO memory 45
The memory 47b is intermittently put into the write state in correspondence with the period during which the data is in the read state, and data for a predetermined period is sequentially written in each write state. When one second of audio data is written to the memory 47b,
Next, the memory 47a is intermittently set to the write state corresponding to the period in which the FIFO memory 45 is in the read state, and the same write operation as described above is repeated.

Also, as described above, the memories 47a, 47
After one second of audio data has been written to b, the read state is set for one frame period, and one second of audio data is read.

Output data from the memories 47a and 47b are supplied to fixed terminals on the a and b sides of the changeover switch 48, respectively. The changeover switch 48 is connected to the side a during the frame period in which the memory 47a is in the read state.
7b is connected to the b side during the frame period in the read state. Output data of the changeover switch 48 is supplied to the framing circuit 44.

In the framing circuit 44, in the normal mode, video data output from the changeover switch 48 is converted into a frame structure together with audio data output from the changeover switch 43. On the other hand, in the audio mode, only the audio data output from the changeover switch 48 is converted into a frame structure. The output data of the framing circuit 44 becomes the output of the framing circuit 9.

Next, the operation of the VTR in each mode during recording will be described with reference to FIG. 6G. In the normal mode, a recording (REC) state is set. When the mode is changed from the normal mode to the audio mode, the recording mode is set until the data of one frame that has been subjected to the normal mode processing by the framing circuit 9 is recorded, and then stopped (S
(TOP) state. Then, the tape is rewound (REW), the tape is rewound for a predetermined period, and the tape is stopped. Then, when a reproduction (PB) state is reached and a position on the tape to be written is reached, a recording state is set. Then, after data for one frame period subjected to the audio mode processing by the framing circuit 9 is recorded, the frame is stopped. Then, a rewinding state is set and the above-described operation is repeated. That is, in the audio mode,
The recording is performed by intermittently controlling the running of the tape. When the mode is changed from the audio mode to the normal mode,
The recording state is continuously set.

It is to be noted that the determination as to whether or not the writing position has been reached can be made by reading the track number of the sub-data, without being described above.

Whether recording in the normal mode or recording in the audio mode is recorded as sub-data. That is, data indicating whether a frame after one frame is a normal frame or an audio frame is recorded as sub data.

Next, the operation of the VTR during reproduction will be described with reference to FIG. 8G. Playback (P
B) state. Further, when the mode is changed from the normal mode to the audio mode based on the information of the sub-data, the reproduction mode is set until the data for one frame period subjected to the normal mode processing is reproduced, and then the operation is stopped (STOP).
State. Then, the tape is rewound (REW), the tape is rewound for a predetermined period, and the tape is stopped. Then, the reproduction state is set to the reproduction state until the data for one frame period which has been normally processed from the tape is reproduced, and then the stop state is set. Then, a rewinding state is set and the above-described operation is repeated.
When the mode is changed from the audio mode to the normal mode based on the information of the sub data, the reproduction mode is continuously performed. In the example of FIG. 8, at time t1, it is detected that the data after one frame is an audio frame, and at time t2, 1
It is detected that the data after the frame is a normal frame.

Next, referring to FIG.
5 will be described. In FIG.
The output data DD of the circuit 24 is supplied to the deframing circuit 51. When in the normal mode, the output data DD consists of video data and audio data,
Audio data and video data separated from the data DD are obtained at output terminals 51a and 51b of the deframing circuit 51, respectively. On the other hand, in the audio mode, the output data DD consists of only audio data, and the audio data is obtained at the output terminal 51b of the deframing circuit 51.

Output terminal 51b of deframing circuit 51
Is supplied to the memories 52a and 52b as write data. These memories 52a, 52
b has a capacity enough to store video data for one frame period. The memory 52a has a write enable signal WEVa and a read enable signal REVa.
(Shown in FIGS. 8A and 8B), and a write enable signal WEVb and a read enable signal REVb are supplied to the memory 52b (shown in FIGS. 8C and 8D).

In the normal mode, the memory 52a is in a write state and the memory 52b is in a read state in a certain frame period, and in the subsequent frame period, the memory 52a is in a read state and the memory 52b is in a write state. Is done.

On the other hand, in the audio mode, the memories 52a and 52b are alternately put into the writing state each time data of one frame period (audio data of one second) subjected to the audio mode processing is reproduced from the tape. , One second worth of audio data is written to each. When data is written to the memories 52a and 52b, the data is intermittently set to the read state, similarly to the write control of the memories 47a and 47b in the example of FIG.

Output data from the memories 52a and 52b are supplied to fixed terminals on the a and b sides of the changeover switch 53, respectively. The changeover switch 53 is connected to the side a during the frame period in which the memory 52a is in the read state.
During the frame period in which 2b is in the read state, it is connected to the b side. The output data of the changeover switch 53 is supplied to the block decoding circuit 26 (see FIG. 2) as a video data output.

The output data of the changeover switch 53 is supplied to a fixed terminal on the a side of the changeover switch 55 via a FIFO memory 54 constituting a clock change circuit from a video system to an audio system. FIFO memory 5
4 is supplied with a write enable signal WEF (shown in FIG. 8E) and a read enable signal REF.
Is supplied (illustrated in FIG. F). In the FIFO memory 54, writing and reading operations are performed in the audio mode.

That is, in the audio mode, audio data is sequentially written in synchronization with the video clock in accordance with the period in which the memories 52a and 52b are in the read state, and the audio data is synchronized with the audio clock. Are continuously read.

The data Da obtained from the output terminal 51a of the deframing circuit 51 is supplied to the fixed terminal on the n side of the changeover switch 55. The changeover switch 55 is connected to the n side in the normal mode, and is connected to the a side in the audio mode. The audio data output from the changeover switch 55 is stored in memories 56a and 56b.
Is supplied as write data.

These memories 56a and 56b have a capacity enough to store audio data for one frame period. The write enable signal WEAa and the read enable signal REAa are supplied to the memory 56a, and the write enable signal WEAb and the read enable signal REAb are supplied to the memory 56b. Then, in a certain frame period, the memory 56a is in a write state and the memory 56b is in a read state, and in a subsequent frame period, the memory 56a is in a read state and the memory 56b is in a write state.

The audio data output from the memories 56a and 56b are supplied to fixed terminals on the a and b sides of the changeover switch 57, respectively. The changeover switch 57 is connected to the a side during one frame period when the memory 56a is in the read state, and is connected to the b side during one frame period when the memory 56b is in the read state. The audio data output from the changeover switch 57 is output to the audio decoding circuit 3
5 (see FIG. 2).

In the above configuration, in the normal mode, the changeover switch 55 is connected to the n side, and the audio data obtained at the output terminal 51a of the deframing circuit 51 is transmitted to the changeover switch 55, the memories 56a and 56b and the changeover switch 57. Audio output via
The video data obtained at the output terminal 51b of the deframing circuit 51 is output as video output via the memories 52a and 52b and the changeover switch 53.

On the other hand, in the audio mode, the changeover switch 55 is connected to the side a and the deframing circuit 5
The audio data obtained at one output terminal 51b is output as an audio output via the memories 52a and 52b, the changeover switch 53, the FIFO memory 54, the changeover switch 55, the memories 56a and 56b, and the changeover switch 57.

In this audio mode,
Since no video data is output from the changeover switch 53, the last video data stored in the block decomposition circuits 28 and 29 and reproduced in the normal mode is output to the output terminals 33Y, 33U and 33V in FIG. Is output repeatedly.

Next, the schematic configurations of the channel encoder 11 (see FIG. 1) and the channel decoder 22 (see FIG. 2) will be described with reference to FIGS. For details of these, refer to Japanese Patent Application No. Hei.
No. 3491.

In FIG. 9, reference numeral 71 denotes an adaptive scrambling circuit to which the output of the mixing circuit 14 is supplied, in which a plurality of M-sequence scrambling circuits are prepared. It is configured such that an M sequence from which an output is obtained is selected. 7
Reference numeral ² denotes a precoder for a partial response class 4 detection method, which performs an arithmetic operation of 1 / 1-D ² (D is a unit delay circuit). The precoder output is recorded / reproduced by the magnetic heads 13A and 13B via the recording amplifiers 12A and 12B, and the reproduced output is reproduced by the reproducing amplifiers 21A and 21B.
Is amplified.

In FIG. 10, reference numeral 73 denotes an arithmetic processing circuit on the reproduction side of the partial response class 4;
The operation of 1 + D is performed on the outputs of the reproduction amplifiers 21A and 21B. 74 denotes a so-called Viterbi decoding circuit,
By performing an arithmetic operation on the output of the arithmetic processing circuit 73 using the correlation, certainty, and the like of the data, decoding of data resistant to noise is performed. The output of the Viterbi decoding circuit 74 is supplied to a descrambling circuit 75, and the data rearranged by the scrambling process on the recording side is returned to the original sequence, and the original data is restored. By using this Viterbi decoding circuit 74, compared to the case of performing decoding for each bit,
An improvement of 3 dB is obtained in terms of reproduction C / N.

Next, the tape head system will be described with reference to FIGS. The above-described magnetic head 13A
And 13B, as shown in FIG.
6 are attached at an interval of 180 ° facing each other. Alternatively, as shown in FIG.
And 13B are attached to drum 76 in a unitary fashion. A magnetic tape (not shown) is obliquely wound around the peripheral surface of the drum 76 at a winding angle slightly larger than 180 ° or slightly smaller than 180 °. In the head arrangement shown in FIG. 11A, the magnetic head 13A
And 13B substantially alternately contact each other, and in the head arrangement shown in FIG. B, the magnetic heads 13A and 13B scan the magnetic tape simultaneously.

The extending directions (referred to as azimuth angles) of the gaps of the magnetic heads 13A and 13B are different. For example, as shown in FIG.
An azimuth angle of ± 20 ° is set between 3A and 13B. Due to this difference in azimuth angle, a recording pattern as shown in FIG. 13 is formed on the magnetic tape. As can be seen from FIG. 13, adjacent tracks TA and TB formed on the magnetic tape are formed by magnetic heads 13A and 13B having different azimuth angles, respectively. Therefore, during reproduction, the amount of crosstalk between adjacent tracks can be reduced due to azimuth loss.

FIGS. 14A and 14B show the magnetic heads 13A and 13B.
A more specific configuration when B is an integrated structure (a so-called double azimuth head) is shown. For example, 150
Upper drum 7 rotated at a high speed of rps (NTSC system)
6, the integrated magnetic heads 13A and 13B
And the lower drum 77 is fixed. Therefore, data of one field is recorded on the magnetic tape 78 while being divided into five tracks. By this segment system, the length of the track can be shortened,
Errors in track linearity can be reduced. The winding angle θ of the magnetic tape 78 is, for example, 166 °, and the drum diameter φ is 16.5 mm.

Simultaneous recording is performed using a double azimuth head. Normally, the magnetic tape 78 vibrates due to the eccentricity of the rotating portion of the upper drum 76, and a track linearity error occurs. As shown in FIG. 15A,
The magnetic tape 78 is pressed down, and the magnetic tape 78 is pulled upward as shown in FIG. B, whereby the magnetic tape 78 vibrates and the linearity of the track deteriorates. However, by performing simultaneous recording with a double azimuth head as compared with the case where a pair of magnetic heads are arranged facing each other at 180 °, the linearity error amount can be reduced. Further, the double azimuth head has an advantage that the pairing adjustment can be performed more accurately because the distance between the heads is small. With such a tape head system, recording / reproducing of a narrow track can be performed.

Next, a track pattern will be described with reference to FIGS. As described above, the magnetic heads 13A and 13B are rotated at a high speed of, for example, 150 rps, and data of one field is divided into five tracks and recorded. Therefore, as shown in FIG.
Data of each frame in the normal mode is recorded on ten tracks, and audio data for one second in the audio mode is also recorded on ten tracks. Also, whether the next frame is a normal frame,
Alternatively, information indicating whether the frame is an audio frame is recorded as sub-data on a track one frame before.

FIG. 17A shows an arrangement of data recorded on one track (or one segment). In the figure, the left end of the track is the head entry side, and the right end is the head separation side. The shaded area is
This is a margin or IBG (interblock gap) where data is not recorded. In the preamble or postamble, for example, a pulse signal having a frequency equal to the bit frequency of the data is recorded, so that the PLL provided on the reproducing side for extracting a bit clock is easily locked.

An ATF is provided at the end of the head entry side of one track.
Is recorded. In the next section, encoded video data and audio data (only audio data in the case of the audio mode) are recorded. Further, a recording section of only audio data is provided after the video and audio sections. Then, the sub data is recorded in the recording section closest to the head separation side.

The video and audio sections are composed of a number of sync blocks. FIG. 17B shows a configuration of a sync block in the normal mode, and FIG.
Indicates a sync block in the audio mode. In the figure, SYNC is a block synchronization signal indicating the start of a block, ID is an identification signal for identifying recording data, and BA is a block address, which is for an address on the screen.

In this embodiment, by setting the audio mode at the time of recording, the tape can be run intermittently and only the audio data can be recorded on the inclined track on the tape. For a long time.

When reproducing the tape recorded in this way, information on whether a normal frame or an audio frame can be read one frame before from the sub data of each track, and the part recorded in the audio mode can be read. Then, the audio mode is automatically set and the tape is intermittently run to perform the reproducing operation, and the digital audio signal is reproduced satisfactorily. That is, it is possible to achieve long-term reproduction of the digital audio signal while suppressing tape consumption.

Further, a digital video signal cannot be obtained at the time of reproduction in the audio mode. However, in this example, the video signal relating to the last frame reproduced in the normal mode is repeatedly output to the output terminals 33Y, 33U and 33V. , And still images can be displayed.

It is to be noted that a recording operation in which only one normal mode is inserted between a plurality of audio modes, for example, can also be considered in a similar manner. In this case, at the time of reproduction, a still image display in which the screen changes every predetermined period can be performed, and an approximate image change can be recognized.

[0070]

According to the first aspect of the present invention, in the second mode, the tape is run intermittently and a digital audio signal for a predetermined period is recorded on the tape in each running period. , And long-term recording of the digital audio signal can be achieved.

According to the second aspect of the present invention, in the second mode portion, the digital audio signal is reproduced by intermittently running the tape, so that the digital audio signal can be reproduced for a long time while the tape consumption is suppressed. can do.

According to the third aspect of the invention, the same effects as those of the second aspect of the invention can be obtained. In addition, while the digital audio signal is reproduced from the second mode portion, the first mode There is an advantage that a still image by the last digital video signal reproduced from the part can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration on a recording side of a signal processing unit according to an embodiment.

FIG. 2 is a block diagram showing a configuration on a reproduction side of a signal processing unit in the embodiment.

FIG. 3 is a schematic diagram illustrating an example of a block for block encoding.

FIG. 4 is a schematic diagram used for explaining a subsample and a subline.

FIG. 5 is a block diagram illustrating an example of a framing circuit.

FIG. 6 is a diagram for explaining the operation of the framing circuit.

FIG. 7 is a block diagram illustrating an example of a frame decomposition circuit.

FIG. 8 is a diagram for explaining the operation of the frame decomposition circuit.

FIG. 9 is a block diagram schematically illustrating an example of a channel encoder.

FIG. 10 is a block diagram schematically illustrating an example of a channel decoder.

FIG. 11 is a schematic diagram used for describing a head arrangement.

FIG. 12 is a schematic diagram used to explain azimuth of a head.

FIG. 13 is a schematic diagram used for describing a recording pattern.

FIG. 14 is a top view and a side view showing an example of a tape head system.

FIG. 15 is a schematic diagram for explaining that tape vibration occurs due to eccentricity of the drum.

FIG. 16 is a schematic diagram illustrating a track pattern.

FIG. 17 is a schematic diagram used for describing a data array of the embodiment.

[Explanation of symbols]

 Input terminals for component signals 1Y, 1U, 1V 5, 6 Blocking circuit 8 Block coding circuit 9 Frame forming circuit 11 Channel encoder 13A, 13B Magnetic head 22 Channel decoder 25 Frame decomposition circuit 26 Block decoding circuit 28, 29 Block decomposition circuit

Claims (3)

(57) [Claims] In a first mode, a tape is continuously run, and a digital video signal and a digital audio signal are simultaneously recorded on the tape by using a predetermined recording section . In a second mode, the tape is recorded. An apparatus for recording a digital signal, wherein the digital audio signal is recorded on the tape only in a predetermined period during each running period by running intermittently using the predetermined recording section . Wherein the digital video signal and a first mode portion recorded with the same time a predetermined recording area of the digital audio signal, the office digital audio signal
When reproducing a tape having a second mode portion recorded using a fixed recording section, in the first mode portion, the tape is continuously run to reproduce the digital video signal and the digital audio signal. In the second mode portion, the digital audio signal is reproduced by intermittently running the tape to reproduce the digital audio signal. 3. A digital video signal and a digital audio signal.
A first mode part in which the audio signal is recorded simultaneously,
Digital audio signal is recorded.
When playing back the first mode portion when playing back a tape to be played ,
Continuously running the digital video signal and
When reproducing the digital audio signal and reproducing the second mode portion, the tape
To intermittently drive the digital audio signal
At the same time as playback, the second mode part is changed to the first mode.
In the case where the digital video signal continues after the digital audio signal, the last digital video signal reproduced from the first mode part is output as a still picture video signal while the digital audio signal is reproduced. Digital signal playback device.