JPH05314667A - Recorder for digital signal and reproducing device therefor - Google Patents

Abstract

PURPOSE:To record and reproduce a digital audio signal by suppressing the consumption of a tape. CONSTITUTION:Video data from a block coding circuit 8 and audio data from an audio encoding circuit 15 are supplied to a framing circuit 9. In a normal mode, the video data and the audio data are converted to a frame structure by the framing circuit 9 and also and recorded in an inclined track by rotary heads 13A, 13B by running continuously a tape. In an audio mode, by the framing circuit 9, the clock of the audio data is transferred to the clock of a video system and subjected to time base compression and subsequently only the audio data are converted to the frame structure and also recorded in the inclined track by the rotary heads 13A, 13B by running intermittently the tape. Since recording is executed by running intermittently the tape, the consumption of the tape is suppressed and the long time recording and reproduction of a digital audio signal can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording / reproducing digital audio signals on a magnetic tape using a rotary magnetic head.

[0002]

2. Description of the Related Art Conventionally, a digital V of D1 format is used.
Various VTRs capable of simultaneously recording and reproducing a digital video signal and a digital audio signal on a tape, such as a TR and a D2 format digital VTR, have been proposed.

[0003]

In such a VTR, even when there is no change in the image or when the voice is more important than the image such as speech, the digital video signal and the digital video signal are recorded on the tape. Since the data is recorded, there is an inconvenience that the tape is uselessly consumed.

Therefore, the present invention provides a digital signal recording apparatus and reproducing apparatus capable of recording and reproducing a digital audio signal while suppressing the consumption of a tape.

[0005]

The invention according to claim 1 is
In the first mode, the tape is continuously run to simultaneously record a digital video signal and a digital audio signal on the tape, and in the second mode, the tape is run intermittently and a predetermined tape is provided on each tape during each running period. The digital audio signal for the period is recorded.

According to a second aspect of the invention, there is provided a first aspect in which a digital video signal and a digital audio signal are simultaneously recorded.
In reproducing the tape having the second mode portion on which the digital audio signal is recorded, the tape is continuously run in the first mode portion to reproduce the digital video signal and the digital audio signal. In the second mode portion, the tape is run intermittently to reproduce the digital audio signal.

According to a third aspect of the present invention, in the second aspect of the invention, while the digital audio signal is reproduced from the second mode portion which is continuous with the first mode portion,
The final digital video signal reproduced from the first mode portion is output as a still picture video signal.

[0008]

In the second aspect of the present invention, in the second mode, the tape is run intermittently and the digital audio signal for a predetermined period is recorded on the tape during each running period, so that the consumption of the tape is suppressed. It is possible to record a digital audio signal for a long time.

According to the second aspect of the present invention, in the second mode portion, the tape is run intermittently to reproduce the digital audio signal. Therefore, it is possible to suppress the consumption of the tape and reproduce the digital audio signal for a long time. Become.

In the invention according to claim 3, claim 2
In addition to obtaining the same operation as the described invention, while reproducing the digital audio signal from the second mode portion, the still image by the last digital video signal reproduced from the first mode portion is displayed. It becomes possible.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital VTR which is an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the entire structure of the recording side. The input terminals 1Y, 1U, 1V are supplied with a digital luminance signal Y and digital color difference signals U, V formed from, for example, three primary color signals R, G, B from a color video camera. In this case, the clock rates of the signals are 13.5 MHz and 6.75 MHz, respectively, like the frequencies of the component signals of the well-known D1 format. The number of bits per sample is 8 bits. Therefore, the data amount of the video signal supplied to the input terminals 1Y, 1U and 1V is about 216 Mbps. Data of the blanking period is removed from this video signal, and only the information of the effective area is extracted by the effective information extraction circuit 2.
And the data amount is compressed to about 167 Mbps.

The luminance signal Y output from the effective information extraction circuit 2 is supplied to the frequency conversion circuit 3 and the sampling frequency is converted from 13.5 MHz to 3/4 thereof. As the frequency conversion circuit 3, for example, a thinning filter is used so that aliasing distortion does not occur. The output signal of the frequency conversion circuit 3 is supplied to the blocking circuit 5, and the order of luminance data is converted into the order of blocks.
The block forming circuit 5 is provided for the block encoding circuit 8 provided in the subsequent stage.

FIG. 3 shows the structure of a block as a coding unit. This example is a three-dimensional block, for example, 2
By dividing the screen across the frames, as shown in FIG. 3, a large number of unit blocks of (4 lines × 4 pixels × 2 frames) are formed. In FIG. 3, a solid line indicates an odd field line, and a broken line indicates an even field line.

Returning to FIG. 1, the color difference signals U and V output from the effective information extraction circuit 2 are supplied to the sub-sampling and sub-line circuit 4, and after the sampling frequencies are each converted from 6.75 MHz to half thereof, Two digital color difference signals are alternately selected for each line and combined into one-channel data. Therefore, from this sub-sampling and sub-line circuit 4, a line-sequential digital color difference signal is obtained. FIG. 4 shows a pixel configuration of the signal subsampled and sublined by the circuit 4. In FIG. 4, “◯” indicates the sampling pixel of the first color difference signal U, “Δ” indicates the sampling pixel of the second color difference signal V, and “x” indicates the position of the pixel thinned out by the subsampling. Is shown.

Subsampling and subline circuit 4
The line-sequential output signal of is supplied to the blocking circuit 6. Similar to the blocking circuit 5, the blocking circuit 6 converts color difference data in the scanning order of the television signal into data in the block order. In the blocking circuit 6, the color difference data is (4 lines × 4) as in the blocking circuit 5.
It is converted into a block structure of (pixels × 2 frames). The output signals of the blocking circuits 5 and 6 are supplied to the synthesizing circuit 7.

In the synthesizing circuit 7, the luminance signal and chrominance signal converted in the order of blocks are converted into 1-channel data, and the output signal of the synthesizing circuit 7 is a block coding circuit 8.
Is supplied to. As the block coding circuit 8, as will be described later, a coding circuit (referred to as ADRC) adapted to the dynamic range of each block, a DCT (discrete).
An e Cosine Transform) circuit or the like can be applied. The output signal of the block encoding circuit 8 is supplied to the framing circuit 9 and converted into frame structure data. In the framing circuit 9, the image system clock and the recording system clock are changed.

Further, a digital audio signal is supplied from the input terminal 1A and supplied to the audio encoding circuit 15. In the audio encoding circuit 15, the data amount of audio data is compressed by DPCM. The output data of the audio encoding circuit 15 is supplied to the framing circuit 9, and is converted into a frame structure together with the block-encoded video data. The audio data supplied to the framing circuit 9 is real-time in the sense related to the video data.

The output signal of the framing circuit 9 is supplied to an error correction code parity generation circuit 10 to generate an error correction code parity. The output signal of the parity generation circuit 10 is supplied to the mixing circuit 14. The output signals of the parity generation circuits 16 and 17 are supplied to the mixing circuit 14, respectively. The parity generation circuit 16 generates the error correction code parity for the output data of the audio encoding circuit 15. At the time of the first recording,
The audio data supplied to the framing circuit 9 and the audio data supplied to the parity generation circuit 16 are the same. In the parity generation circuit 17, error correction encoding processing is performed on the sub data from the input terminal 1S, and parity is generated.

In the mixing circuit 14, data in which these video data, audio data and sub data are inserted is formed at a predetermined position of one segment which will be described later. The output signal of the mixing circuit 14 is supplied to the channel encoder 11 and subjected to channel coding so as to reduce the low frequency part of the recording data. The output signal of the channel encoder 11 is supplied to the mixing circuit 18. A pilot signal for ATF (automatic track following control) from the input terminal 19 is supplied to the mixing circuit 18. This pilot signal is a low frequency signal that can be frequency separated from the recorded data. The output signal of the mixing circuit 18 is the recording amplifier 12
It is supplied to the magnetic heads 13A and 13B via A and 12B and a rotary transformer (not shown) and recorded on a magnetic tape.

By the above-mentioned signal processing, the input data amount of 216 Mbps is about 1 by extracting only the effective scanning period.
67 Mbps, which is further reduced to 84 Mbps by frequency conversion and sub-sampling and sub-lines. This data is compressed and coded by the block coding circuit 8 to about 25 Mbps, and then additional information such as parity and audio signal is added to make the recording data amount about 31.56 Mbps. ..

Next, FIG. 2 shows the entire structure on the reproducing side. The reproduction data from the magnetic heads 13A and 13B is supplied to a rotary transformer (not shown) and a reproduction amplifier 21.
Channel decoder 22 and ATF via A, 21B
Each is supplied to the circuit 34. Channel decoder 22
Then, the channel coding is demodulated, and the output signal of the channel decoder 22 becomes TBC circuit (time base correction circuit) 2
3 is supplied. The TBC circuit 23 removes the time-axis fluctuation component of the reproduced signal. The ATF circuit 34 generates a tracking error signal from the level of the beat component of the reproduced pilot signal, and this tracking error signal is supplied to, for example, a phase servo circuit of a capstan servo (not shown). The operation of such an ATF is basically 8
It is the same as that used in the mmVTR.

The reproduced data from the TBC circuit 23 is ECC.
It is supplied to the circuits 24, 37 and 39, and error correction and error correction using the error correction code are performed. EC
The C circuit 24 performs error correction and error correction on the video data, the ECC circuit 37 performs error correction and error correction of the audio data recorded in the audio-dedicated section, and the ECC circuit 39 performs error correction and error correction on the sub data. Error correction is performed.
The output signal of the ECC circuit 37 is supplied to the audio decoding circuit 38, and the compression encoding of the audio signal is decoded. The decoded data of the audio decoding circuit 38 is the synthesis circuit 3
6 is supplied. The reproduced sub data is taken out from the output terminal 33S of the ECC circuit 39. Although not shown, this sub data is supplied to a system controller for controlling the operation of the entire VTR. ECC circuit 24
Is output to the frame decomposition circuit 25.

The frame decomposing circuit 25 separates the respective components of the block coded data of the video data from each other and changes the clock of the recording system to the clock of the image system. Each data separated by the frame decomposition circuit 25 is supplied to the block decoding circuit 26, and the restored data corresponding to the original data is decoded in each block. Also, in the frame disassembling circuit 25, the audio data is separated, and this audio data is supplied to the audio decoding circuit 35 to obtain the decoded data corresponding to the original audio data. The decoded audio data is supplied to the synthesis circuit 36. In the synthesizing circuit 36, the two input audio signals are synthesized by switching or crossfade.

The decoded data of the image data from the block decoding circuit 26 is supplied to the distribution circuit 27. The distribution circuit 27 separates the decoded data into a luminance signal and a color difference signal. The luminance signal and the color difference signal are block decomposition circuits 28,
29 respectively. Block decomposition circuit 28, 2
In 9, the decoded data in the order of blocks is converted in the order of raster scanning, contrary to the blocking circuits 5 and 6 on the transmission side.

The decoded luminance signal from the block decomposition circuit 28 is supplied to the interpolation filter 30. In the interpolation filter 30, the sampling rate of the luminance signal is 3 fs to 4 fs.
(4fs = 13.5 MHz). The digital luminance signal Y from the interpolation filter 30 is taken out to the output terminal 33Y.

On the other hand, the digital color difference signal from the block decomposition circuit 29 is supplied to the distribution circuit 31, and the line-sequential digital color difference signals U and V are separated into the digital color difference signals U and V, respectively. The digital color difference signals U and V from the distribution circuit 31 are supplied to the interpolation circuit 32 and are interpolated. The interpolating circuit 32 interpolates the thinned-out line and pixel data using the restored pixel data, and the interpolating circuit 32 obtains digital color difference signals U and V with a sampling rate of 4 fs, and the output terminal 33.
It is taken out to U and 33V, respectively.

Next, a specific configuration of the framing circuit 9 will be described with reference to FIG. In the figure, the audio data DA output from the audio encoding circuit 15 is supplied to the movable terminal of the changeover switch 41. The changeover switch 41 is connected to the n side in the normal mode and connected to the a side in the audio mode. The audio data obtained on the n side of the changeover switch 41 is stored in the memory 42.
It is supplied as write data to a and 42b.

These memories 42a and 42b have a capacity enough to store audio data for one frame period. The memory 42a is supplied with a write enable signal WEaa and a read enable signal REAa, and the memory 42b is supplied with a write enable signal WEab and a read enable signal REAb. Then, the memory 42a is set to the writing state and the memory 42b is set to the reading state in a certain frame period, and the memory 42a is set to the reading state and the memory 42b is set to the writing state in the subsequent frame period.

The audio data output from the memories 42a and 42b are supplied to the fixed terminals on the side a and the side b of the changeover switch 43, respectively. The changeover switch 43 is connected to the a side during the frame period when the memory 42a is in the read state, and is connected to the b side during the frame period when the memory 42b is in the read state. The audio data output from the changeover switch 43 is supplied to the framing circuit 44.

Audio data obtained on the a side of the changeover switch 41 is supplied to a fixed terminal on the a side of the changeover switch 46 via a FIFO memory 45 which constitutes a clock transfer circuit from the audio system to the video system. ..
The FIFO memory 45 has a write enable signal WE.
While F is supplied (shown in FIG. 6E), the read enable signal REF is supplied (shown in FIG. 6E). FI
In the FO memory 45, writing and reading operations are performed in the audio mode. That is, in the audio mode, the audio data is sequentially written in synchronization with the audio system clock, and the audio data for that period is read out in synchronization with the video system clock at every predetermined period.

Video data DV output from the block encoding circuit 8 is supplied to a fixed terminal on the n side of the changeover switch 46. The changeover switch 46 is connected to the n side in the normal mode, and is connected to the a side in the audio mode. The output data of the changeover switch 46 is the memory 4
It is supplied as write data to 7a and 47b. These memories 47a and 47b have a capacity capable of storing video data for one frame period. Memory 4
The write enable signal WEVa and the read enable signal REVa are supplied to 7a (shown in FIGS. 6A and 6B), and the write enable signal WEVb is supplied to the memory 47b.
And a read enable signal REVb is supplied (shown in C and D in the same figure).

In the normal mode, the memory 47a is set to the writing state and the memory 47b is set to the reading state in a certain frame period, and the memory 47a is set to the reading state and the memory 47b is set to the writing state in the subsequent frame period. To be done.

On the other hand, in the audio mode, first, the memory 47a is intermittently set to the write state corresponding to the period when the FIFO memory 45 is in the read state, and the audio data for a predetermined period is sequentially written in each write state. Then, when one second of audio data is written in the memory 47a, the FIFO memory 45
The memory 47b is intermittently set to the write state corresponding to the period in which the read state is set, and the data for a predetermined period is sequentially written in each write state. When one second of audio data is written in the memory 47b,
Next, the memory 47a is intermittently set to the write state corresponding to the period when the FIFO memory 45 is in the read state, and the same write operation as described above is repeated.

Further, as described above, the memories 47a, 47
After the audio data for 1 second is written in b, the read state is set for only one frame period, and the audio data for 1 second is read.

The output data of the memories 47a and 47b are supplied to the fixed terminals on the side a and the side b of the changeover switch 48, respectively. The changeover switch 48 is connected to the a side during the frame period when the memory 47a is in the read state, while the memory 4
7b is connected to the b side during the frame period in which it is in the read state. The output data of the changeover switch 48 is supplied to the framing circuit 44.

In the framing circuit 44, in the normal mode, the video data output from the selector switch 48 is converted into a frame structure together with the audio data output from the selector switch 43. On the other hand, in the audio mode, only the audio data output from the changeover switch 48 is converted into the frame structure. The output data of the framing circuit 44 becomes the output of the framing circuit 9.

Next, the operation of the VTR in each mode during recording will be described with reference to FIG. 6G. In the normal mode, the recording (REC) state is set. When the normal mode is changed to the audio mode, the framing circuit 9 keeps recording until one frame of data processed in the normal mode is recorded, and then stops (S
It is set to the TOP) state. Then, the tape is rewound (REW), the tape is rewound for a predetermined period, and the tape is stopped. Then, when the reproduction (PB) state is reached and the position to write on the tape is reached, the recording state is set. Then, after the data for one frame period which has been subjected to the audio mode processing by the framing circuit 9 is recorded, it is brought into a stopped state. Then, the rewinding state is set and the above-described operation is repeated. That is, in audio mode,
Recording is performed by intermittently controlling the running of the tape. When the audio mode is changed to the normal mode,
The recording state is continuously set.

The determination as to whether or not the write position has been reached can be made by reading the track number of the sub data, not described above.

Further, whether the recording is in the normal mode or in the audio mode is recorded as sub data. That is, as sub data, data indicating whether the one frame after is a normal frame or an audio frame is also recorded.

Next, the operation of the VTR during reproduction will be described with reference to FIG. 8G. Play (P in normal mode)
B) The state is set. When the normal mode is changed to the audio mode based on the information of the sub data, the reproduction mode is maintained until the data for one frame period processed in the normal mode is reproduced, and then stopped (STOP).
To be in a state. Then, the tape is rewound (REW), the tape is rewound for a predetermined period, and the tape is stopped. Then, the reproduction state is set, and the reproduction state is maintained until the data for one frame period which is normally processed and continues on the tape is reproduced, and then the stop state is set. Then, the rewinding state is set and the above-described operation is repeated.
Further, when the audio mode is changed to the normal mode based on the information of the sub data, the reproduction state is continuously set. In the example of FIG. 8, it is detected that the data one frame after is an audio frame at time t1, and 1 is detected at time t2.
It is detected that the data after the frame is a normal frame.

Next, referring to FIG. 7, the frame decomposing circuit 2
A specific configuration of No. 5 will be described. In the figure, ECC
The output data DD of the circuit 24 is supplied to the deframing circuit 51. In the normal mode, the output data DD consists of video data and audio data,
Audio data and video data separated from the data DD are obtained at the output terminals 51a and 51b of the deframing circuit 51, respectively. On the other hand, in the audio mode, the output data DD includes only audio data, and the audio data is obtained at the output terminal 51b of the deframing circuit 51.

Output terminal 51b of the deframing circuit 51
The data Db obtained in the above is supplied to the memories 52a and 52b as write data. These memories 52a, 52
b has a capacity enough to store video data for one frame period. The memory 52a has a write enable signal WEVa and a read enable signal REVa.
Is supplied (shown in FIGS. 8A and 8B), and the write enable signal WEVb and the read enable signal REVb are supplied to the memory 52b (shown in FIGS. 8C and 8D).

In the normal mode, the memory 52a is set to the write state and the memory 52b is set to the read state in a certain frame period, and the memory 52a is set to the read state and the memory 52b is set in the write state in the subsequent frame period. To be done.

On the other hand, in the audio mode, the memories 52a and 52b are alternately written each time data for one frame period (audio data for one second) processed in the audio mode is reproduced from the tape. , 1 second of audio data is written in each. Then, when the data is written in the memories 52a and 52b, similarly to the write control of the memories 47a and 47b in the example of FIG. 5, the reading state is intermittently set.

The output data of the memories 52a and 52b are supplied to the fixed terminals on the side a and the side b of the changeover switch 53, respectively. The changeover switch 53 is connected to the a side during the frame period in which the memory 52a is in the read state, while the memory 5
The frame period in which 2b is in the read state is connected to the b side. The output data of the changeover switch 53 is supplied to the block decoding circuit 26 (see FIG. 2) as a video data output.

The output data of the changeover switch 53 is supplied to a fixed terminal on the side a of the changeover switch 55 via a FIFO memory 54 which constitutes a clock transfer circuit from the video system to the audio system. FIFO memory 5
4 is supplied with a write enable signal WF (shown in FIG. 8E) and a read enable signal REF.
Are supplied (shown in FIG. 4F). In the FIFO memory 54, writing and reading operations are performed in the audio mode.

That is, in the audio mode, the audio data is sequentially written in synchronization with the video clock in correspondence with the period in which the memories 52a and 52b are in the read state, and the audio data is synchronized with the audio clock. Are read continuously.

The data Da obtained at the output terminal 51a of the deframing circuit 51 is supplied to the fixed terminal on the n side of the changeover switch 55. The changeover switch 55 is connected to the n side in the normal mode, and is connected to the a side in the audio mode. Audio data output from the changeover switch 55 is stored in the memories 56a and 56b.
Is supplied as write data.

These memories 56a and 56b have a capacity capable of storing audio data for one frame period. The memory 56a is supplied with the write enable signal WEaa and the read enable signal REAa, and the memory 56b is supplied with the write enable signal WEab and the read enable signal REAb. Then, the memory 56a is set to the writing state and the memory 56b is set to the reading state in a certain frame period, and the memory 56a is set to the reading state and the memory 56b is set to the writing state in the subsequent frame period.

The audio data output from the memories 56a and 56b are supplied to the fixed terminals on the side a and the side b of the changeover switch 57, respectively. The changeover switch 57 is connected to the a side during one frame period when the memory 56a is in the read state, and is connected to the b side during the one frame period when the memory 56b is in the read state. The audio data output from the changeover switch 57 is the audio decoding circuit 3
5 (see FIG. 2).

In the above configuration, in the normal mode, the changeover switch 55 is connected to the n side, and the audio data obtained at the output terminal 51a of the deframing circuit 51 is transferred to the changeover switch 55, the memories 56a, 56b and the changeover switch 57. Is output as audio.
Also, the video data obtained at the output terminal 51b of the deframing circuit 51 is output as video through the memories 52a and 52b and the changeover switch 53.

On the other hand, in the audio mode, the changeover switch 55 is connected to the a side, and the deframing circuit 5
The audio data obtained at the output terminal 51b of No. 1 is output as audio through the memories 52a and 52b, the changeover switch 53, the FIFO memory 54, the changeover switch 55, the memories 56a and 56b, and the changeover switch 57.

In this audio mode,
Since no video data is output from the changeover switch 53, the final video data stored in the block decomposition circuits 28 and 29 and reproduced in the normal mode is output as still image data to the output terminals 33Y, 33U and 33V in FIG. Is repeatedly output as.

Next, the schematic configurations of the channel encoder 11 (see FIG. 1) and the channel decoder 22 (see FIG. 2) will be described with reference to FIGS. 9 and 10. For details of these, Japanese Patent Application No. 1-14 of the present applicant
3491.

In FIG. 9, reference numeral 71 denotes an adaptive scramble circuit to which the output of the mixing circuit 14 is supplied. A plurality of M-sequence scramble circuits are prepared, and among them, the input signal has the least high frequency component and DC component. The M-sequence is selected so that an output can be obtained. 7
Reference numeral 2 is a precoder for the partial response class 4 detection method, and the arithmetic processing of 1 / 1-D ² (D is a unit delay circuit) is performed. This precoder output is recorded / reproduced by the magnetic heads 13A and 13B via the recording amplifiers 12A and 12B, and the reproduction output is reproduced amplifiers 21A and 21B.
It is designed to be amplified by.

Further, in FIG. 10, reference numeral 73 denotes an arithmetic processing circuit on the reproducing side of the partial response class 4.
The operation 1 + D is performed on the outputs of the reproduction amplifiers 21A and 21B. 74 is a so-called Viterbi decoding circuit,
The output of the arithmetic processing circuit 73 is subjected to an operation using the correlation and the likelihood of the data, etc., so that the data resistant to noise is decoded. The output of the Viterbi decoding circuit 74 is supplied to the descramble circuit 75, the data rearranged by the scrambling process on the recording side is returned to the original series, and the original data is restored. By using this Viterbi decoding circuit 74, as compared with the case of performing bit-by-bit decoding,
An improvement of 3 dB can be obtained in terms of reproduction C / N.

Next, the tape head system will be described with reference to FIGS. The magnetic head 13A described above
And 13B are rotating drums 7 as shown in FIG. 11A.
6 are attached at an opposing interval of 180 °. Alternatively, as shown in FIG.
And 13B are attached to the drum 76 in an integrated form. A magnetic tape (not shown) is obliquely wound around the peripheral surface of the drum 76 at a winding angle slightly larger than 180 ° or slightly smaller than 180 °. In the head arrangement shown in FIG. 11A, the magnetic head 13A is attached to the magnetic tape.
And 13B almost alternately contact each other, and in the head arrangement shown in FIG. 9B, the magnetic heads 13A and 13B simultaneously scan the magnetic tape.

The extension directions (called azimuth angles) of the gaps of the magnetic heads 13A and 13B are made different. For example, as shown in FIG. 12, the magnetic head 1
An azimuth angle of ± 20 ° is set between 3A and 13B. Due to this difference in azimuth angle, a recording pattern as shown in FIG. 13 is formed on the magnetic tape. As can be seen from FIG. 13, the adjacent tracks TA and TB formed on the magnetic tape are formed by the magnetic heads 13A and 13B having different azimuth angles, respectively. Therefore, during reproduction, the amount of crosstalk between adjacent tracks can be reduced due to azimuth loss.

14A and 14B show magnetic heads 13A and 13A.
A more specific configuration in the case where B is an integral structure (so-called double azimuth head) is shown. For example, 150
Upper drum 7 rotated at high speed of rps (NTSC system)
6, the magnetic heads 13A and 13B having an integral structure
Is attached, and the lower drum 77 is fixed. Therefore, on the magnetic tape 78, one field of data is divided into five tracks and recorded. With this segment system, the length of the track can be shortened,
The error of track linearity can be reduced. The winding angle θ of the magnetic tape 78 is, for example, 166 °, and the drum diameter φ is 16.5 mm.

Simultaneous recording is performed by using a double azimuth head. Normally, the magnetic tape 78 vibrates due to the eccentricity of the rotating portion of the upper drum 76, and an error in the linearity of the track occurs. As shown in FIG. 15A,
The magnetic tape 78 is pressed downward, and as shown in FIG. 9B, the magnetic tape 78 is pulled upward, which vibrates the magnetic tape 78 and deteriorates the linearity of the track. However, by performing simultaneous recording with the double azimuth head, the error amount of the linearity can be reduced as compared with the case where a pair of magnetic heads are arranged facing each other at 180 °. Further, the double azimuth head has the advantage that the pairing adjustment can be performed more accurately because the distance between the heads is small. With such a tape head system, recording / reproduction of a narrow track can be performed.

Next, the track pattern will be described with reference to FIGS. 16 and 17. As described above, the magnetic heads 13A and 13B are rotated at a high speed of, for example, 150 rps, and one field of data is divided into five tracks and recorded. Therefore, as shown in FIG.
The data of each frame in the normal mode is recorded on 10 tracks, and the audio data for each 1 second in the audio mode is also recorded on 10 tracks. Also, if the next frame is a normal frame,
Alternatively, information indicating whether the frame is an audio frame is recorded on the track one frame before as sub data.

FIG. 17A shows an array of data recorded on one track (or one segment). In the figure, the left end of the track is the head entry side, and the right end thereof is the head separation side. Also, the shaded area is
It is a margin or IBG (inter block gap) where data is not recorded. For example, a pulse signal having a frequency equal to the bit frequency of data is recorded in the preamble or the postamble, and it is easy to lock the PLL for extracting the bit clock provided on the reproducing side.

ATF is provided at the end of the head entry side of one track.
A pilot signal for is recorded. Coded video data and audio data (only audio data in the audio mode) are recorded in the next section. Further, a recording section for only audio data is provided after the video and audio sections. Then, the sub data is recorded in the recording section closest to the head separation side.

The video and audio sections are composed of many sync blocks. FIG. 17B shows the structure of the sync block in the normal mode.
Indicates a sync block in the audio mode. In the figure, SYNC is a block synchronization signal indicating the start of a block, ID is an identification signal for identifying recorded data, BA is a block address, and is for an address on the screen.

In this example, by setting the audio mode at the time of recording, the tape can be intermittently run and only the audio data can be recorded on the inclined track on the tape, and the consumption of the tape can be suppressed and the digital audio signal can be suppressed. It is possible to achieve long-time recording.

Further, when reproducing the tape recorded in this way, the information of the normal frame or the audio frame can be read one frame before from the sub-data of each track, and in the portion recorded in the audio mode. The audio mode is automatically set, the tape is intermittently run, and the reproducing operation is performed, so that the digital audio signal is reproduced well. That is, it is possible to reduce the consumption of the tape and achieve long-term reproduction of the digital audio signal.

Further, although a digital video signal cannot be obtained during reproduction in the audio mode, in this example, the video signal relating to the last frame reproduced in the normal mode is repeatedly output to the output terminals 33Y, 33U, 33V. , Still images can be displayed.

It should be noted that the recording operation of inserting only one frame in the normal mode between a plurality of audio modes can be considered in the same manner as described above, though not described above. In this case, at the time of reproduction, it is possible to display a still image in which the screen changes every predetermined period, and it is possible to recognize an approximate image change.

[0070]

According to the first aspect of the present invention, in the second mode, the tape is run intermittently and a digital audio signal for a predetermined period is recorded on the tape during each running period. It is possible to achieve long-term recording of a digital audio signal by suppressing this.

According to the second aspect of the present invention, in the second mode portion, the tape is run intermittently to reproduce the digital audio signal. Therefore, consumption of the tape is suppressed and long-time reproduction of the digital audio signal is achieved. can do.

According to the third aspect of the present invention, the same effect as that of the second aspect of the invention can be obtained, and the first mode is provided while the digital audio signal is being reproduced from the second mode portion. There is a benefit of being able to display a still picture from the last digital video signal that is reproduced from the part.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration on a recording side of a signal processing unit in an embodiment.

FIG. 2 is a block diagram showing a configuration on a reproducing side of a signal processing unit in the embodiment.

FIG. 3 is a schematic diagram showing an example of a block for block coding.

FIG. 4 is a schematic diagram used to describe a subsample and a subline.

FIG. 5 is a block diagram showing an example of a framing circuit.

FIG. 6 is a diagram for explaining the operation of the framing circuit.

FIG. 7 is a block diagram showing an example of a frame decomposition circuit.

FIG. 8 is a diagram for explaining the operation of the frame disassembling circuit.

FIG. 9 is a block diagram showing an outline of an example of a channel encoder.

FIG. 10 is a block diagram showing an outline of an example of a channel decoder.

FIG. 11 is a schematic diagram used to describe a head arrangement.

FIG. 12 is a schematic diagram used to describe the azimuth of the head.

FIG. 13 is a schematic diagram used to describe a recording pattern.

FIG. 14 is a top view and a side view showing an example of a tape head system.

FIG. 15 is a schematic diagram for explaining that the tape vibration occurs due to the eccentricity of the drum.

FIG. 16 is a schematic diagram showing a track pattern.

FIG. 17 is a schematic diagram used to explain a data array of an example.

[Explanation of symbols]

 1Y, 1U, 1V Component signal input terminals 5, 6 blocking circuit 8 block coding circuit 9 framing circuit 11 channel encoder 13A, 13B magnetic head 22 channel decoder 25 frame decomposing circuit 26 block decoding circuit 28, 29 block decomposing circuit

Claims (3)

[Claims] 1. In a first mode, a tape is continuously run to simultaneously record a digital video signal and a digital audio signal on the tape, and in a second mode, the tape is run intermittently for each run. A digital signal recording apparatus for recording a digital audio signal for a predetermined period on the tape for a predetermined period. 2. When reproducing a tape having a first mode portion in which a digital video signal and a digital audio signal are simultaneously recorded and a second mode portion in which a digital audio signal is recorded, the above-mentioned first mode portion is used. A digital tape characterized in that the tape is continuously run to reproduce the digital video signal and the digital audio signal, and in the second mode portion, the tape is intermittently run to reproduce the digital audio signal. Signal playback device. 3. The still picture video is the last digital video signal reproduced from the first mode portion while the digital audio signal is reproduced from the second mode portion following the first mode portion. The digital signal reproducing apparatus according to claim 2, wherein the reproducing apparatus outputs the signal as a signal.