JPH06342565A - Magnetic tape and digital video tape recorder - Google Patents

Abstract

PURPOSE:To improve an interchangeability between devices at the time of post-recording and also to prevent a magnetic tape from being damaged at the time of high speed search. CONSTITUTION:Data of 1st and 2nd sub-code areas of the magnetic tape and their error flags are supplied to a switch circuit 53. At the time of normal reproduction, the data of the 1st sub-code area are supplied as a signal (a) and thr error flag is supplied as a signal (b) to a D-flip-flop 55, then they are supplied to a switch circuit 56 as a signal (e), and also the signal (b) is supplied to a switch controller 57 as a signal (f). The data of the 2nd sub-code area are supplied to the switch circuit 56 as a switch (c) and the error flag is supplied to the switch controller 57 as a signal (d) respectively. In the switch controller 57, a control signal (g) is supplied to the switch circuit 56 in accordance with the supplied two error flags. By this control signal (g), the signal (e) or the signal (f) is outputted from the switch circuit 56.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic tape and a digital video tape recorder for recording digital video data and digital audio data.

[0002]

2. Description of the Related Art For example, a digital VTR for recording digitized digital video data and audio data
It has been known. The structure of this digital VTR is shown in FIG. In the digital VTR of FIG. 5, the digital luminance signal Y and the digital color difference signals U and V are input to the recording processing circuit 101 during recording. Each of these signals is blocked, shuffled, discrete cosine transformed (D
CT), compression by quantization and tunable coding, and framing, and then supplied to the parity generation circuit 102.

The data supplied to the parity generation circuit 102 is added with the parity of the product code here, and then supplied to the sync and ID generation circuit 103, where the synchronization code and I
D is added. Then, the channel encoder 104 performs parallel / serial conversion and conversion into a recording code, and the amplifier 105 amplifies. Amplifier 10
The output of No. 5 is supplied to the magnetic head 107 via the recording side terminal R of the switching circuit 106, and the magnetic tape 108 is supplied.
Recorded above. Here, the video data for one frame is recorded as a plurality of diagonal tracks.

The audio data, the subcode and the ATF pilot signal are supplied to the channel encoder 104, and the magnetic head 107 drives the magnetic tape 108.
The video data and the video data are recorded in a time-divisional manner in the divided predetermined area of each track.

During reproduction, the data reproduced from the magnetic tape 108 by the magnetic head 107 is supplied to the amplifier and equalizer 109 via the terminal P on the reproducing side of the switching circuit 106. Here, amplification and frequency characteristic correction are performed, and the channel decoder 110 performs decoding of the recording code and serial / parallel conversion.
The sync code and ID are detected by the sync and ID detection circuit 111, and are supplied to the TBC (time base collector) circuit 112 together with the reproduction data. In the data supplied to the TBC circuit 112, the time base fluctuation is removed, and then the ECC
The circuit 113 performs error correction processing using the product code and then supplies it to the reproduction processing circuit 114.

The video data supplied to the reproduction processing circuit 114 is subjected to deframing, decoding of a tunable code, inverse quantization, inverse DCT, deshuffling, and deblocking, and then a luminance signal Y and color difference. It is output as signals U and V.

Although not shown here, EC
Audio data and subcode are also output from the C circuit 113, and the same processing as described above is performed. Further, the ATF pilot signal is separated from the output of the channel decoder 110 and supplied to the ATF circuit for tracking correction.

FIGS. 6 and 7 show an example of the track format of the magnetic tape for a digital VTR constructed as described above.

In FIG. 6, the left end of the track is the head entrance (rush) side, and the right end of the track is the head exit (separation) side. Further, no data is recorded in the gap (area used for editing). In the track shown in FIG. 6, the order of scanning by the head is as follows. That is, the first gap, the subcode area (preamble, subcode, and postamble) is provided after the ITI area in which the data for creating the recording area at the time of after-recording is recorded as well as the reproduction phase servo area at the time of after-recording. Consists of). next,
The second gap, the digitally recorded audio data area, the third gap, and the digitally recorded video data area similar to the audio data are scanned. Data for enabling high-speed search is recorded in the sub-code area. Also, the ITI area is 3450 bytes, the first gap is 725 bytes,
The subcode area is 1900 bytes, the second gap is 750 bytes, the audio data area is 11425 bytes, the third gap is 900 bytes, and the video data area is 112,100 bytes.

The track format shown in FIG. 7 is a track format in which a margin is added to the one shown in FIG. 6 and the subcode position is replaced.
No data is recorded in this margin. In FIG. 7, the order of scanning by the head is as follows. That is, the margin, the ITI area, the first gap,
Scanning is performed in the order of audio data area, second gap, video data area, third gap, subcode area, and margin. The ITI area is 3,45
0 bytes, first gap is 725 bytes, audio data area is 12,175 bytes, second gap is 900 bytes, video data area is 110,600 bytes, third gap is 1,100 bytes, subcode area Has a capacity of 2,900 bytes.

By the way, when data such as post-recording or high-speed search is performed on the data recorded in the above-mentioned track format, the data recorded in the ITI area or the subcode area is used.

For example, when post-recording is performed, in the track format shown in FIG. 6, the reproduction phase servo is applied in the ITI area. Therefore, the track servo can be accurately applied to the magnetic tape, and the data recorded in the sub code area can be read. However, in the track format shown in FIG. 7, the subcode area is provided after the fourth gap,
Servo cannot be applied accurately to the sub code. Therefore, the data in the sub code area cannot be read accurately. Also, the VT is
A track is formed by the characteristic of R. When the magnetic tape having the tracks formed in this way is reproduced by another VTR, the formed tracks may not be accurately scanned because the characteristics of the device are different. In other words, the post-recorded data may not be reproducible by devices having different characteristics.

When the subcode area shown in FIG. 6 is used, that is, when a high speed search for immediately searching for desired data is used, the data recorded in the subcode area on the ITI area side is written. In order to read it, the tension on the tape must be increased. If the tension is increased too much, the magnetic tape will be damaged. On the other hand, in the track format shown in FIG. 7, since the subcode is provided after the fourth gap, the data in the subcode area can be accurately read without increasing the tension of the tape. .

As described above, in the magnetic tape of the trunk format shown in FIG. 6, the magnetic tape may be damaged during high speed search. Further, in the magnetic tape having the track format shown in FIG. 7, there is a possibility that the post-recorded data cannot be accurately read when different devices are used during the post-recording.

Therefore, an object of the present invention is to improve the compatibility between devices and to record the post-recorded data to different VTRs.
It is an object of the present invention to provide a digital VTR which can be reproduced by the method described above and can reduce the damage of the magnetic tape during a high speed search.

[0016]

According to a first aspect of the present invention, there is provided a magnetic tape on which video data and audio data are digitally recorded, wherein a plurality of tracks are formed on the magnetic tape and the tracks are formed on the tracks. A first subcode recording area in which a subcode associated with audio data and video data is recorded, an audio data recording area in which audio data is recorded, a video data recording area in which video data is recorded, and a first subcode recording area. This is a magnetic tape in which data is recorded in the order of the second subcode recording area in which similar data is recorded.

According to a second aspect of the present invention, in a digital video tape recorder having video data and audio data digitally recorded on a track on a magnetic tape and having a normal reproduction mode and a high speed search mode, First selection means to which the data of the code area and the data of the second sub-code area are supplied, a controller to which the output of the first selection means is supplied, data of the first sub-code area and the second The second selection means to which the data of the subcode area is supplied, and the subcode output from the second selection means is controlled by a control signal supplied from the controller to the second selection means. It is a tape recorder.

[0018]

In the dubbing mode, the first sub-code provided on the front part of the magnetic tape and the second sub-code provided on the rear part of the magnetic tape are supplied to the switch circuit 56. In addition, the error code associated with the first subcode and the second code
The error code associated with the sub-code is supplied to the switch controller 57. The switch controller 57 supplies a control signal to the switch circuit 56 based on the supplied two error codes. With this control signal,
The subcode output from the switch circuit 56 is determined. Further, during the high speed search, the second sub-code is output from the switch circuit 56.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of the recording side of a digital VTR to which the present invention is applied. 1Y, 1U and 1V
The digital luminance signal Y formed from the three primary color signals R, G, and B and the digital color difference signals U and V are input to the input terminal shown by. In this case, the clock rate of each signal is 13.5 MHz or 6.75 MHz, and the number of bits per sample is 8 bits.

Of these signals, the amount of data is compressed by the effective information extraction circuit 2 which removes the data in the blanking period and extracts only the information in the effective area. Of the output of the effective information extraction circuit 2, the luminance signal Y is supplied to the frequency conversion circuit 3 and the sampling frequency is 13.5 MHz.
To 3/4 of that. As the frequency conversion circuit 3, for example, a thinning filter is used so that aliasing distortion does not occur. The output signal of the frequency conversion circuit 3 is supplied to the blocking circuit 5, and the order of luminance data is converted into the order of blocks. Blocking circuit 5
Are provided for the block encoding circuit 8 arranged in the subsequent stage.

For block coding, DCT, ADRC
(Coding adapted to the dynamic range) or the like can be used. Note that one block has 8 × 8 pixels.

Of the outputs of the effective information extraction circuit 2,
Two color difference signals U and V are supplied to the subsampling and subline circuit 4. In the sub-sampling and sub-line circuit 4, the sampling frequency is 6.7, respectively.
After being converted from 5 MHz to half thereof, two digital color difference signals are alternately selected for each line and combined into one-channel data. Therefore, the sub-sampling and sub-line circuit 4 outputs a line-sequential digital color difference signal.

The line-sequential output signal of the sub-sampling and sub-line circuit 4 is supplied to the blocking circuit 6. Similar to the blocking circuit 5, the blocking circuit 6 converts color difference data in the scanning order of the television signal into data in the block order. Similar to the blocking circuit 5, the blocking circuit 6 converts the color difference data into a block structure of 8 × 8 pixels. The output signals of the blocking circuits 5 and 6 are supplied to the synthesizing circuit 7.

In the synthesizing circuit 7, the luminance signal and the color difference signal converted in the order of blocks are converted into one-channel data. The output signal of the combining circuit 7 is supplied to the block encoding circuit 8. The block coding circuit 8 is, like the blocking circuits 5 and 6, a coding circuit (ADRC) adapted to the dynamic range of each block,
A DCT circuit or the like can be applied. The output signal of the block code interposing circuit 8 is supplied to the framing circuit 9 and converted into frame structure data. In the framing circuit 9, the image system clock and the recording system clock are transferred.

Further, the digital audio data input from the input terminal 1A ₁ is supplied to the audio processing circuit 18 and subjected to processing necessary for recording. The output data of the audio processing circuit 18 is the parity generation circuit 19
And the parity of the product code which is the error correction code is generated. In this way, the audio data and parity recorded in the audio data area are mixed by the mixing circuit 1.
2 is supplied.

The output signal of the framing circuit 9 is supplied to the parity generation circuit 11 via the contact a of the switch 10 and the parity of the product code is generated. The output signal of the parity generation circuit 11 is supplied to the mixing circuit 12. The output signals of the parity generation circuits 19 and 27 are supplied to the mixing circuit 12, respectively. The parity generation circuit 19 generates the parity of the error correction code for the output data of the audio encoding circuit 18. The parity generation circuit 27 performs error correction coding processing on the subcode input from the input terminal 1S to generate parity. Of the product codes having the inner code and the outer code as error correction codes, only the inner code is used for the subcode.

The sub-code supplied to the input terminal 1S is
It is generated from the subcode generation circuit 24. Further, the ID or sync generated by the ID generation circuit 25 or the sync generation circuit 26 is supplied to the input terminal 1S. The timing signal generating circuit 23 includes a sub code generating circuit 24,
The ID generating circuit 25 and the sync generating circuit 26 are respectively supplied with necessary predetermined timing signals.

In the mixing circuit 12, data in which these video data, audio data, and subcode are inserted is formed at a predetermined position of one track described later. The output signal of the mixing circuit 12 is supplied to the channel encoder 13, and channel coding is performed so as to reduce the low frequency part of the recording data. Channel encoder 1
The output signal of 3 is supplied to the mixing circuit 14. Mixing circuit 1
An ATF pilot signal f1, f2, and fN is supplied to the input terminal 4 from the input terminal 15. This pilot signal is a low frequency signal that can be frequency separated from the recorded data. The output signal of the mixing circuit 14 is the recording amplifier 16
It is supplied to the magnetic heads 17A and 17B through A and 16B and a rotary transformer (not shown) and recorded on a magnetic tape (not shown).

On the other hand, the audio data input from the input terminal 1A ₂ (this audio data is
₁ may be the same as or different from the data inputted from ₁ ) and is inputted to the audio compression circuit 21 and, for example, about 300 by DPCM.
It is compressed to kbps. This data is recorded in the memory 22. The memory 22 is controlled by the framing circuit 9, and the audio data stored in the memory 22 is read out. At this point, the framing circuit 9 switches the switch 10 to the contact b side.
As a result, the audio data read by the memory 22 is supplied to the parity generation circuit 11 via the contact b of the switch 10, and the parity data is added. This data is supplied to the mixing circuit 12 and is recorded on the magnetic tape via the magnetic heads 17A and 17B as described above.

Next, a digital V to which the present invention is applied
The structure on the reproducing side of the TR will be described with reference to FIG.

In FIG. 2, magnetic heads 17A and 17A are provided.
The reproduction data extracted by B is supplied to the channel decoder 32 and the ATF circuit 52 via a rotary transformer (not shown) and reproduction amplifiers 31A and 31B, respectively. In the channel decoder 32, the channel code is demodulated (decoded), and its output signal is supplied to the TBC circuit 33. The TBC circuit 33 removes the time-axis fluctuation component of the reproduced signal. In the ATF circuit 52, a tracking error signal is generated from the level of the crosstalk component of the reproduced pilot signal. This tracking error signal is supplied to, for example, a phase servo (not shown) of a capstan servo.

The reproduced data from the TBC circuit 33 is ECC
It is supplied to the circuit 34, the ECC circuit 44, and the ECC circuit 46, and the error correction using the product code and the error that cannot be corrected are performed. The ECC circuit 34 performs error correction and error correction on the video data. Further, the ECC circuit 44 performs error correction and error correction of the audio data recorded in the audio data. Further, the ECC circuit 46 performs error correction on the subcode. The output signal of the ECC circuit 44 is supplied to the audio processing circuit 45, and processing necessary for reproducing the audio signal is performed. The output data of the audio processing circuit 45 is output to another circuit via the output terminal 43A ₁ . The reproduced subcode is taken out from the subcode output terminal 43S of the ECC circuit 46. This subcode is supplied to a system controller (not shown) for controlling the operation of the entire VTR via a subcode selection circuit described later. The output signal of the ECC circuit 34 is supplied to the frame decomposition circuit 35.

In the frame disassembling circuit 35, each component of the block coded data of the video data is disassembled and the clock of the recording system is changed to the clock of the pixel system. The respective data separated in the frame disassembling circuit 35 are supplied to the block decoding circuit 36, and the restored data corresponding to the original data is decoded for each block.

The decoded data of the video data from the block decoding circuit 36 is supplied to the distribution circuit 37. In the distribution circuit 37, the decoded data is divided into a luminance signal and a color difference signal. The luminance decomposition signal and the color difference signal are processed by the block decomposition circuit 3
8 and 39 respectively. Block decomposition circuit 3
In 8 and 39, contrary to the block circuits 5 and 6 on the reproduction side, the decoded data in block order is converted in the raster scanning order.

The decoded luminance signal from the block decomposition circuit 38 is supplied to the interpolation filter 40. In the interpolation filter 40, the sampling rate of the luminance signal is 3fs (fs is
4 fs (4 fs = 1) from the color subcarrier frequency
3.5 MHz). The digital luminance signal Y from the interpolation filter 40 is taken out via the output terminal 43Y.

On the other hand, the digital color difference signal from the block decomposition circuit 39 is supplied to the distribution circuit 41, and the line-sequential digital color difference signals U and V are separated. The digital color difference signals U and V separated by the distribution circuit 41 are supplied to the interpolation circuit 42 and interpolated. The interpolation circuit 42 uses the restored video data to interpolate the thinned pixel data. Digital color difference signals U and V having a sampling rate of 4 fs are obtained from the interpolation circuit 42, and output terminals 43U and 43V are provided.
Are taken out respectively.

On the other hand, the audio data output from the ECC circuit 34 is supplied to the memory 49 and stored therein after being subjected to error correction. The ECC circuit 34 supplies to the memory 49 an error flag indicating the position of the error that could not be corrected. In the memory 49, the data that is input corresponding to this error flag and that could not be error-corrected is also written. The data written in the memory 49 is supplied to the compression audio decoding circuit 50, and compression decoding is performed. The decoded data is further supplied to the interpolation circuit 51. In the interpolation circuit 51, the data corresponding to the error flag is interpolated. The output of the interpolation circuit 51 is output to a circuit (not shown) via the output terminal 43A ₂ .

The signal output from the TBC circuit 33 is
It is input to the f _T signal processing circuit 47. The f _T signal processing circuit 47 detects the sync and ID in the ITI area of the track format described later from the input signal. Then, the position is determined from the data (sync number) indicating the sync position in this ID, and the counter 48 is operated at a predetermined timing. The counter 48 outputs a timing signal corresponding to the reproduction position of the magnetic heads 17A and 17B from the output terminal 43T. Therefore, the system controller controls the post-recording with reference to the timing signal output from the output terminal 43T.

FIG. 3 shows a track format of a magnetic tape used in the above digital VTR.
In FIG. 3, the left end of the track is the head entrance (rush) side, and the right end of the track is the head exit (separation) side.
Further, no data is recorded in the gap (area used for editing). In the track format shown in FIG. 3, the order of scanning by the head is as follows. That is, after the first margin and the ITI area, the first gap, the first subcode area, the second gap, the audio data area, the third gap,
The video data area, the fourth gap, the second subcode area, and the second margin are scanned. In addition, ITI
The area is 3450 bytes, the first gap is 725 bytes, the second subcode area is 1975 bytes, the second gap is 750 bytes, and the audio data area is 1
1425 bytes, the third gap is 900 bytes, the video data area is 112,850 bytes, the fourth gap is 1,100 bytes, and the second subcode area is 2.
It has a capacity of 900 bytes.

In the track format shown above, two subcode areas are provided. That is, the first sub-code is provided after the first gap and the second sub-code is provided after the fourth gap. As the data recorded in the second sub-code, for example, the same data as the data recorded in the first sub-code is recorded.

Thus, in the track format shown in FIG. 3, two sub code areas are provided.
For example, during normal reproduction such as after-recording, the data recorded in the first subcode area is read. As a result, the reproduction phase servo is applied in the ITI area.
Therefore, accurate track servo can be applied to the magnetic tape, and the data recorded in the subcode area can be read. Further, when performing a high speed search, the data recorded in the second sub code area is read. As a result, when the data in the sub code area is read, the data can be read accurately without increasing the tension of the magnetic tape.

FIG. 4 shows a block diagram of a subcode selection circuit for deciding which of the above two subcode areas is to be used. In FIG. 4, the data in the subcode area and the error flag generated in the ECC circuit 46 are input to the switch circuit 53 via the subcode output terminal 43S. A timing generator 54 is connected to the switch circuit 53, and data is output from the switch circuit 53 as signals a and c and error flags are output as signals b and d in accordance with the timing signal output from the timing generator 54. Is output. It should be noted that signal a is data in the first subcode area, signal b is an error flag relating to data in the first subcode area, signal c is data in the second subcode area, and signal d is the second subcode area. Is an error flag related to the data.

The signals a and b are supplied to a D-flip-flop (hereinafter referred to as D-FF) 55 and are synchronized with the data of the second sub code area and the timing of its error flag. Data is output from the D-FF 55 as a signal e.
Is supplied to the switch circuit 56, and the error flag is supplied to the switch controller 57 as a signal f. On the other hand, the signal c is supplied to the switch circuit 56, and the signal d is supplied to the switch controller 57. The switch controller 57 generates the control signal g based on the supplied two error flags d and f. The control signal g is supplied to the switch circuit 56. Control signal g
Accordingly, one of the two data supplied to the switch circuit 56 is output to the interface 58. The data of the sub-code area supplied to the interface 58 is converted into a signal format suitable for the system controller and supplied to the system controller via the output terminal 59.

Here, for example, at the time of after-recording, the signal d
When the (error flag) is at a high (hereinafter, referred to as H) level (indicating occurrence of an error) and the signal f is at a low (hereinafter, referred to as L) level, the switch circuit 56 selectively outputs the signal e. On the other hand, when the signal d is L level and the signal f is H level, the switch circuit 56 selectively outputs the signal c.
In this way, the signal c or e can be used during dubbing. Further, when both the signals d and f are at the L level, either of the signals c or e may be used.

Further, at the time of high speed search, as described above,
The data in the second sub code area is read. In this case, the mode selection signal input to the switch circuit 56 is set to "high speed search", whereby the switch circuit 56 preferentially outputs the signal c. As a result, accurate data can always be retrieved from the subcode area during high-speed search.

[0046]

According to the present invention, data is read from the first sub-code area or the second sub-code area during dubbing and from the second sub-code area during high-speed search. The data is read. This makes it possible to maintain compatibility even when different devices are used during dubbing. Further, it can be used without damaging the magnetic tape during high-speed search.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration on a recording side of a digital VTR to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration on the reproducing side of a digital VTR to which the present invention is applied.

FIG. 3 is a diagram showing a track format of a magnetic tape used in a digital VTR according to the present invention.

FIG. 4 is a block diagram of a subcode selection circuit.

FIG. 5 is a block diagram of a conventional digital VTR.

FIG. 6 is a diagram showing a track format of a conventional magnetic tape for digital VTR.

FIG. 7 is a diagram showing a track format of a conventional magnetic tape for digital VTR.

[Explanation of symbols]

 43S Sub-code output terminal 53, 56 Switch circuit 54 Timing generator 57 Switch controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inoue Hajime 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Keiji Kanata 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation

Claims (4)

[Claims] 1. A magnetic tape on which video data and audio data are digitally recorded, wherein a plurality of tracks are formed on the magnetic tape, and the tracks are attached to the audio data and the video data. A first subcode recording area recording a subcode, an audio data recording area recording the audio data, a video data recording area recording the video data, and data similar to the first subcode recording area. A magnetic tape on which data is recorded in the order of the recorded second subcode recording area. 2. Video data and audio data are digitally recorded on tracks on a magnetic tape, and
In a digital video tape recorder having a normal reproduction mode and a high speed search mode, first selection means to which data of a first subcode area and data of a second subcode area are supplied, and the first selection means. And a second selection means to which the data of the first sub-code area and the data of the second sub-code area are supplied. The sub-code is a digital video tape recorder controlled by a control signal supplied from the controller to the second selecting means. 3. The digital video according to claim 2, wherein in the normal reproduction mode, either the data of the first sub-code area or the data of the second sub-code area is output. Tape recorder. 4. In the high speed search mode, the second
3. The digital video tape recorder according to claim 2, wherein the data of the sub-code area is output.