JPH0652633A - Recording and reproducing device for digital video signal - Google Patents

Abstract

PURPOSE:To enable restricting a digital copy by performing scramble by changing the order of shuffling of a macro block. CONSTITUTION:An analog video signal is inputted to an input terminal 90. Analog processing circuit 91 converts the analog video signal to a digital signal, and supplies it to a scrambler 92 as digital data. A key signal generating circuit 93 generates a key signal used for scramble and supplies it to the scrambler 92. The scrambler 92 receives this key signal, and changes the order of shuffling of a macro block constituted by collecting blocks of a component signal and performs scramble. A parity generating circuit 96 adds parity to input video data, and outputs it to a recording processing circuit 97. The circuit 97 modulates the input video data, and outputs it to a magnetic head 98. Also, the circuit 97 supplies the key signal too outputted from the circuit 93 to the magnetic head 98.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in, for example, a digital video tape recorder when digitally recording an NTSC video signal or a high-definition television signal represented by high definition on a magnetic tape. The present invention relates to a digital video signal recording / reproducing apparatus.

[0002]

2. Description of the Related Art FIG. 12 shows an example of copying (dubbing) in a digital video tape recorder.

In the example of FIG. 12, the deck A is the reproducing side and the deck B is the recording side. In the deck A, the video data reproduced from the magnetic tape 71 by the magnetic head 72 is supplied to the error correction (ECC) circuit 74 after being subjected to necessary processing such as demodulation in the reproduction processing circuit 73 to correct the error. Be seen. The output of the ECC circuit 74 is A / D converted in the analog processing circuit 75, and is output and displayed as an analog signal on a CRT (not shown) or the like.

The digital data output from the ECC circuit 74 of the deck A is supplied to the deck B via the digital interface. In Deck B,
The parity generation circuit 81 adds a parity to the data input from the deck A. The data to which the parity is added is modulated by the recording processing circuit 82, supplied to the magnetic head 83, and recorded on the magnetic tape 84.

[0005]

However, since the digital video tape recorder constructed so that the digital data can be output as it is can copy digitally any number of times, it is a copyrighted work. There may be social problems from the perspective of rights protection.

The present invention has been made in view of the above circumstances, and it is possible to limit digital copying.

[0007]

DISCLOSURE OF THE INVENTION According to the present invention, the shuffling order of a macroblock formed by collecting blocks of component signals is changed and scrambled, and key information indicating the shuffling order of the macroblock is recorded on a tape. Is a recording device for a digital video signal, which is adapted to be recorded in a predetermined area.

The present invention is a reproducing apparatus for a digital video signal in which the order of macroblock deshuffling is changed in accordance with key information in a predetermined area on a tape to descramble.

The shuffling order of macroblocks is changed within the same sub-area.

[0010]

The scrambling can be performed by changing the shuffling order of macroblocks. Also, by changing the order of the shuffling within the same sub-area, it is possible to deal with clogs and scratch noises.

[0011]

1 and 2 are block diagrams showing a configuration example of a recording system and a reproducing system of a digital video tape recorder to which a recording medium recording apparatus and a reproducing apparatus of the present invention are applied.

In FIG. 1, an analog video signal is input to the input terminal 90. The analog processing circuit 91 A / D converts this analog video signal and supplies it to the scrambler 92 as digital data. The key signal generation circuit 93 generates a key signal used for scrambling and supplies it to the scrambler 92.
The switch 94 selects one of the digital video data input from the input terminal 95 and the scrambled digital video data input from the scrambler 92, and supplies it to the parity generation circuit 96. The parity generation circuit 96 adds parity to the input digital video data and outputs it to the recording processing circuit 97. The recording processing circuit 97 modulates the digital video data input from the parity generation circuit 96 and outputs it to the magnetic head 98. The recording processing circuit 97 also supplies the key signal output from the key signal generating circuit 93 to the magnetic head 98. The rotating magnetic head 98 attached to a rotating drum (not shown) records the input digital video data and key signal on the magnetic tape 99 at a predetermined timing.

In FIG. 2, the magnetic head 98 outputs a signal reproduced from the magnetic tape 99 to the reproduction processing circuit 100. The reproduction processing circuit 100 outputs
The key signal is output to the key signal detection circuit 104, the digital video data is digitally demodulated, and the digital data is output to the error correction (ECC) circuit 101. The key signal detection circuit 104 detects a key signal from the input signal. The error correction circuit 101 corrects an error in the input digital data and outputs it to the descrambler 102. The descrambler 102 is also supplied with the key signal detected by the key signal detection circuit 104.
The data descrambled by the descrambler 102 is input to the analog processing circuit 105, D / A converted, and output from the output terminal 106.
Further, the digital data output from the ECC circuit 101 is output to the outside from the output terminal 103 arranged in the preceding stage of the output terminal scrambler 102.

Next, the operation will be described. The analog video signal input from the input terminal 90 is A / D converted in the analog processing circuit 91 to be digital video data. The scrambler 92 scrambles the digital video data input from the analog processing circuit 91 in response to the key signal input from the key signal generation circuit 93. The scramble is performed by changing the shuffling, which will be described in detail later. This scrambled digital video data is sent to the switch 9
It is input to the parity generation circuit 96 via 4 and the parity is added. The digital video data with parity is digitally modulated in the recording processing circuit 97,
The data is recorded on the magnetic tape 99 via the magnetic head 98.
Further, at this time, the magnetic head 98 is switched at a predetermined timing, and together with the digital video data,
The key signal is also recorded on the magnetic tape 99.

FIG. 3 shows a simplified positional relationship between the digital video data thus recorded and the key signal on the magnetic tape 99 (for a more detailed format of the track, refer to FIG. 5). See below). As shown in FIG. 3, a plurality of slanted tracks are formed on the magnetic tape 99. A video data recording area 99A is formed on this track, and a key signal recording area 99B is formed at a position different from this video data recording area 99A. The digital video data is recorded in the video data recording area 99A, and the key signal used for scrambling is recorded in the key signal recording area 99B.

The signal reproduced from the magnetic tape 99 by the magnetic head 98 is input to the reproduction processing circuit 100.
The reproduction processing circuit 100 outputs the key signal among the input signals to the key signal detection circuit 104, digitally demodulates the digital video data, and the ECC circuit 101.
Output to. The key signal detection circuit 104 detects a key signal from the input signal. The ECC circuit 101 corrects an error in the input digital data and outputs it to the descrambler 102. The descrambler 102 descrambles the digital video data input from the ECC circuit 101 in response to the key signal detected by the key signal detection circuit 104. Descrambler 102
Is a deshuffling circuit. Descrambler 102
The digital video data descrambled by is input to the analog processing circuit 105, D / A converted,
It is output from the output terminal 106.

Next, the operation for copying will be described. When copying a magnetic tape, two digital video tape recorders having the recording / reproducing system shown in FIGS. 1 and 2 are prepared. Then, the digital video data reproduced by one of the digital video tape recorders (having at least a reproducing system) and output from the output terminal 103 thereof is input to the other digital video tape recorder (having at least a recording system) of its input terminal 95. Will be supplied from. Now, for convenience of explanation, digital video data reproduced by the reproduction system shown in FIG.
Description will be made assuming that recording is performed in the recording system shown in FIG.

When the magnetic tape 98 is reproduced by the magnetic head 98 in the reproducing system, the video data recording area 99 is formed.
The digital video data is reproduced from A and the key signal is reproduced from the key signal recording area 99B. The digital video data is output from the output terminal 103 after being error-corrected in the ECC circuit 101. This output terminal 10
The reference numeral 3 is arranged in front of the descrambler 102. Therefore, the digital video data output from the output terminal 103 becomes scrambled data.

The digital data output from the output terminal 103 is input to the parity generation circuit 96 via the input terminal 95 of the recording system and the switch 94. Here, the digital video data to which the parity is added is recorded by the recording processing circuit 9
The data is digitally modulated at 7, and recorded by the magnetic head 98 in the video data recording area 99A of the magnetic tape 99 (copy destination magnetic tape).

However, in the reproducing system, the key signal reproduced from the magnetic tape 99 is supplied to the key signal detecting circuit 104 incorporated in the reproducing system, but is not output from the output terminal 103. Therefore, this key signal cannot be recorded in the recording system. That is, as shown in FIG. 4, digital video data is recorded (copied) in the video data recording area of the copy destination magnetic tape 99, but no key signal is recorded in the key signal recording area 99B.

In this way, when the magnetic tape 99 on which the key signal is not recorded is reproduced by the reproducing system, the scrambler 1
Although digital video data is input to 02, it cannot be descrambled after all because the key signal is not detected. Therefore, even if the video signal output from the analog processing circuit 105 is output to a CRT or the like, substantially no image is displayed. That is, in this sense, copying of digital video data is substantially prohibited.

FIG. 5 shows a track format on a magnetic tape as a recording medium of a digital video tape recorder to which the recording medium recording / reproducing apparatus of the present invention is applied. As shown in the figure, in this embodiment, signals are arranged as follows in order from the side (the left side in the figure) where the magnetic head starts contacting the magnetic tape. First 45
The period of 5 bytes and 455 bytes at the end (the side where the magnetic head separates from the magnetic tape (the right side in FIG. 5)) is
Each is a margin area. Then, substantial data is recorded in the period of 16089 bytes between these two margin areas.

Next to the first margin area, 60 bytes of T amble are recorded. Since this amble is immediately after the contact with the magnetic head, the PL that generates the clock is generated.
Considering the pull-in of L, it is formed slightly longer than other ambles. In the next 237-byte period, AT
A region F1 is formed. In this area, the pilot signals f1, f2, f _N for tracking are recorded and the timing sync signal f _T is recorded.
In the A channel track, the signal f _T is recorded in the first 6 × 6 byte section, and the pilot signals f1 and f _N for tracking are recorded in the remaining section. On the other hand, in the B channel track, the signal f _T is recorded in the first 6 × 10 byte section, and the pilot signals f _N and f2 for tracking are recorded in the remaining section. However, the pilot signal f2 is recorded Ichikai the four tracks are adapted to the pilot signal f _N are recorded in the remaining three tracks.

In the signal f _T , 6 bytes are recorded as 1 unit (1 block), the first 2 bytes are sync data,
The next 2 bytes are ID data, and the next 1 byte is ID parity (IDP). According to the standard, the remaining 1 byte is reserved for future use. In this embodiment, the above-mentioned key signal is recorded here. That is,
A signal indicating the scrambling order is recorded here.

As described above, in this embodiment, the key signal is recorded in the remaining 1 byte of the signal f _T. This key signal does not have to be recorded on all tracks. If this key signal is recorded on a specific track, the scramble strength is enhanced, that is, the track number of the track on which the key signal is written is made known only to a specific user. In this way, only the user who knows the track number on which the key signal is written can access the track on which the key signal is written and descramble it.

Following ATF1, a period of 176 bytes,
An amble area is formed. A predetermined period on the front side of the amble area is a 131-byte IBG area (inter block gap area). In the subsequent preamble area, a clock necessary for detecting audio data in the audio data recording area that follows is recorded for a period of 45 bytes.

Next to the amble area, an audio data recording area of 1274 bytes (recording area dedicated to audio data) is arranged. In this audio data recording area, uncompressed audio data is recorded as it is. That is, for example, the data which is converted into digital data with the sampling frequency of 48 kHz for the analog audio signal of 2 channels and the quantization bit number of 16 bits is directly recorded here (32 kHz, 1
It can also be 2-bit, 4-channel data).

Next to the audio data recording area, 18
An amble area of a 2-byte period is formed. This amble area includes a 6-byte postamble period following the audio data recording area and a 45-byte preamble period preceding the subsequent video data recording area. And between the two amble areas, 13
A 1-byte IBG area is formed.

The video data recording area has a length of 13377 bytes. In the video data recording area, as will be described later, for example, video data compressed by DCT (discrete / cosine transform) processing is recorded, and audio data compressed by DPCM or the like is also recorded. ing.

Next to the video data recording area, an amble area having a period of 182 bytes is formed. This amble area also has a postamble area (6 bytes) and a preamble area (45 bytes) formed in the same manner as in the amble area formed on the start point side of the video data recording area, and an IBG area between them. (131 bytes) are formed. The postamble area follows the video data recording area, and the preamble area precedes the next subcode recording area.

The subcode recording area is set for a period of 144 bytes. In this area, subcodes associated with video data and audio data recorded in the video data recording area or audio data recording area, such as data and time code required for high-speed access, are recorded.

Next to the subcode recording area, an amble area having a period of 220 bytes is formed. This amble area is also divided into a postamble area (44 bytes) following the subcode recording area and a preamble area (45 bytes) preceding the next ATF2 area, and an IBG area (131 bytes) is formed between them. Has been done.

The area of ATF2 has a period of 237 bytes, and the same data as in the case of ATF1 described above is recorded in this area.

Next, with reference to FIGS. 6 and 7, an embodiment of a digital video tape recorder for recording and reproducing data in the above-mentioned format will be described.

FIG. 6 shows the structure of the recording side.
Digital luminance signals Y and digital color difference signals U and V formed from, for example, three primary color signals R, G and B output from a color video camera (not shown) are supplied to input terminals respectively indicated by 1Y, 1U and 1V. To be done. In this case, the clock rate of each signal is 13.5MHz or 6.75M.
Hz, and the number of bits per sample is 8 bits.

Of this signal, the data amount in the blanking period is removed and the data amount is compressed by the effective information extraction circuit 2 which extracts only the information in the effective area. Of the output of the effective information extraction circuit 2, the luminance signal Y is supplied to the frequency conversion circuit 3 and the sampling frequency is converted from 13.5 MHz to 3/4 thereof. As the frequency conversion circuit 3, for example, a thinning filter is used so that aliasing distortion does not occur. The output signal of the frequency conversion circuit 3 is supplied to the blocking circuit 5, and the order of luminance data is converted into the order of blocks. The blocking circuit 5 is
It is provided for the block encoding circuit 8 provided in the subsequent stage.

For block coding, DCT, ADRC
(Encoding adapted to the dynamic range) or the like can be adopted. One block has 8 × 8 pixels.

Of the outputs of the valid information extraction circuit 2,
The two color difference signals U and V are supplied to the sub-sampling and sub-line circuit 4, the sampling frequency is converted from 6.75 MHz to half thereof, and then two digital color difference signals are alternately selected for each line, and one channel is selected. Is combined with the data of.

Subsampling and subline circuit 4
The line sequential output signal is supplied to the blocking circuit 6. Similar to the blocking circuit 5, the blocking circuit 6 converts color difference data in the scanning order of the television signal into data in the block order. Similar to the blocking circuit 5, the blocking circuit 6 converts the color difference data into a block structure of 8 × 8 pixels. The output signals of the blocking circuits 5 and 6 are supplied to the combining circuit 7.

In the synthesizing circuit 7, four blocks of the luminance signal,
A macroblock is synthesized from two blocks of each of the two color difference signals. This macro block is supplied to the shuffling circuit 28. The order of shuffling is changed according to the key information from the key generation circuit 27 when scramble recording is performed.

The output signal of the synthesizing circuit 7 is supplied to the block coding circuit 8. The block coding circuit 8 includes coding circuits (ADRC), D adapted to the dynamic range of each block, as in the blocking circuits 5 and 6.
A CT circuit or the like can be applied. The output signal of the block encoding circuit 8 is supplied to the framing circuit 9 and converted into frame structure data.

Further, the digital audio data input from the input terminal 1A1 is supplied to the audio processing circuit 18 and subjected to processing necessary for recording. The output data of the audio processing circuit 18 is supplied to the parity generation circuit 19, and the parity of the product code which is an error correction code is generated. In this way, the audio data and the parity to be recorded in the audio data recording area described above are supplied to the mixing circuit 12.

The output signal of the framing circuit 9 is supplied to the parity generation circuit 11 via the contact a of the switch 10, and the parity of the product code is generated. The output signal of the parity generation circuit 11 is supplied to the mixing circuit 12. The output signals of the parity generation circuits 19 and 27 are supplied to the mixing circuit 12, respectively. The parity generation circuit 19 generates the parity of the error correction code for the output data of the audio encoding circuit 18. The parity generation circuit 27
An error correction coding process is performed on the subcode input from the input terminal 1S to generate a parity. For the sub-code, only the inner code is used among the product codes having the inner code and the outer code as the error correction code.

The sub-code supplied to the input terminal 1S is
It is generated from the subcode generation circuit 24. Further, the ID or sync generated by the ID generation circuit 25 or the sync generation circuit 26 is supplied to the input terminal 1S. The timing signal generating circuit 23 includes a sub code generating circuit 24, I
The D generating circuit 25 and the sync generating circuit 26 are respectively supplied with necessary predetermined timing signals.

In the mixing circuit 12, the video data, the audio data, and the data in which the subcode is inserted are formed at predetermined positions on one track which will be described later. The output signal of the mixing circuit 12 is supplied to the channel encoder 13, and channel coding is performed so as to reduce the low frequency part of the recording data. Channel encoder 13
Is supplied to the mixing circuit 14. Mixing circuit 14
From the input terminal 15 to the pilot signal f for ATF.
1, f2, f _N are supplied. This pilot signal is
It is a low-frequency signal that can be frequency separated from recorded data. The output signal of the mixing circuit 14 is the recording amplifiers 16A, 16
Magnetic head 17 through B and a rotary transformer (not shown)
It is supplied to A and 17B and recorded on the magnetic tape.

On the other hand, the audio data input from the input terminal 1A2 (this audio data is
1 may be the same as the input data or may be different) and is input to the audio compression circuit 21 and, for example, about 300 by DPCM.
It is compressed to kbps. This data is supplied to and stored in the memory 22. The framing circuit 9 controls the memory 22 to read the audio data stored therein. At this time, the framing circuit 9 switches the switch 10 to the contact b side. As a result, the memory 22
The read audio data is supplied to the parity generation circuit 11 via the contact b of the switch 10, and the parity data is added. This data is supplied to the mixing circuit 12, and in the same manner as described above, the magnetic head 17
It is supplied to A and 17B and recorded.

The key signal generating circuit 29 is used for the magnetic head 17
A track pulse corresponding to the number of revolutions of A and 17B is received, and a key signal is generated in synchronization with the input. This key signal sets the shuffling order of the shuffling circuit 28.

The key signal output from the key signal generating circuit 29 is also supplied to the sub code generating circuit 24. The subcode generation circuit 24 subcodes the input key signal and outputs it as a subcode. As a result, the key signal is recorded in the ATFs 1 and 2 shown in FIG.

Here, the shuffling will be described.
FIG. 8 shows an outline of the shuffling process. As shown in FIG. 8, one frame has five areas A, for example.
It is divided into 0, A1, A2, A3 and A4. Area A
One macro block MB, M from 1, A2, A3, ...
B, MB, ... Are selected. At this time, the macroblocks MB, MB, MB, ... Of each area are selected so that the horizontal positions do not match as much as possible.

As described above, the data is shuffled and collected by selecting the macro blocks MB, MB, MB ... From the areas A0, A1 ,. This is a buffering unit.

The shuffling process will be described in more detail. In order to realize such shuffling, FIG.
As shown in A, each area of one frame is divided into sub areas. The sub-areas in each area are shown in FIG.
As shown in A, they are numbered.

First, the data (0-0) of the macro block number 0 belonging to the sub-area number 0 (shown by hatching) in each area is collected, and the buffering is performed from (0-0) of each area. Units are made up. Next, the data (0-1) of the macroblock of the macroblock number 1 belonging to the sub-area number 0 is collected, and the buffering unit is composed of the (0-1) macroblocks of each area. Hereinafter, (0-2), (0-
3), the data of the sub-blocks of ... Are gathered to form the next buffering unit. As a result, FIG.
As shown in (1), in the first track, (0-0) macroblocks are buffered in units of (0-26).
The data up to the buffering unit, which is a collection of macroblocks of, will be recorded.

Next, the data (1-0) of the macroblock of the super macroblock number 0 belonging to the sub-area number 1 in each area is collected and buffered from the macroblock of (1-0) in each area. Units are made up. Next, the data (1-1) of the super macroblock of the macroblock number 1 belonging to the subarea number 1 is collected, and the buffering unit is composed of the (1-1) macroblocks of each area. Less than,
Data of sub-blocks (1-2), (1-3), ... Are collected to form the next buffering unit. As a result, as shown in FIG. 10, in the next one track, data from the buffering unit in which the macro blocks of (1-0) are collected to the buffering unit in which the macro blocks of (1-26) are collected. Will be recorded.

Thereafter, in the first frame, as shown in FIG. 10, buffering unit data in which data of each super macroblock is collected is recorded. In the next frame, this time, first, the data (1-13) of the super macro block of the super macro block number 8 belonging to the sub area number 1 in each area is collected, and the data (1-13) of each area is recorded. A buffering unit is composed of macroblocks. Next, the data (1-14) of the macroblock of the macroblock number 7 belonging to the sub-area number 1 is collected, and (1-
A buffering unit is composed of the macroblock of 14). Hereinafter, (1-15), (1-16) ... (1-2
6), (1-0) ... Sub-block data is collected to form the next buffering unit. As a result, as shown in FIG. 10, in the first track,
Data from the buffering unit in which the macro blocks of (1-13) are collected to the buffering unit in which the super macro blocks of (1-12) are collected are recorded.

As described above, in the embodiment of the present invention, the order of shuffling is different between the odd frame and the even frame. This is to deal with head clogs and scratch noise.

That is, in order to deal with the error of the reproduced signal of one channel due to the head clog, the macroblocks of even subarea numbers are first collected in the odd frame to form the buffering unit ( In this example, it starts from 0 subarea number),
In an even-numbered frame, macroblocks of odd-numbered sub-area numbers are first collected to form a buffering unit (starting from one sub-area number in this example).
In this way, in the odd-numbered frame, even sub-area number (0-x, 2-x, ...) Super macroblocks are collected in the A channel to record the buffering unit, and the B channel is an odd sub-area. Number (1
-X, 3-x, ...) Macro blocks are collected and recorded in buffering units. In even-numbered frames, odd sub-area numbers (1-x, 3-x,
...) macroblocks are collected and buffering units are recorded, and even sub-area number (2-x, 4-x, ...) macroblocks are collected in the B channel and buffering units are recorded. It Therefore, for example, when the head of channel A cannot be reproduced, even sub-area numbers (0-x, 2-x,
...) macroblocks cannot be reproduced, but even-numbered sub-area numbers (0-x, 2-x,
...) macroblocks can be reproduced, so that interpolation is possible. On the other hand, when the head of channel A cannot be reproduced, the odd sub-area number (1-x,
3- ×, ...) macroblock cannot be played,
In an odd frame, an odd sub area number (1-x, 3
-X, ...) Super macroblocks can be reproduced, so that interpolation is possible.

Further, in order to cope with an error in the longitudinal direction of the tape due to the scratch, the macro block number is advanced in the order of (x-0, x-1, ...) In the odd frame, while the even number is advanced. In the frame, macroblock numbers are advanced in the order of (x-13, x-14, ...).

That is, for example, it is assumed that the first buffering unit BU0 of each track cannot be completely reproduced. In this case, in odd frames, (0-0), (1-0),
The data in the buffering unit of (2-0), ..., That is, the data in the buffering unit in which the macro block number 0 is collected becomes an error. On the other hand, in the even frames, (1-13), (0-13), (3-1)
3), ..., The data in the buffering unit, that is, the data in the buffering unit in which the macroblock number 13 is collected becomes an error, and the macroblock number 0
The buffering unit that collects the ones is being replayed.
Therefore, the data of the buffering unit in which the super macro block number 0 of the odd frame is collected can be interpolated. On the other hand, in the even-numbered frame, the data in the buffering unit in which the macroblock number 13 is collected becomes an error, but in the odd-numbered frame, the data in the buffering unit in which the macroblock number 13 is collected is reproduced. You can

Normally, in odd-numbered frames, the 0th macroblock in each sub-area is selected in order. Scramble is realized by changing the order of macroblocks in each subarea. For example, in FIG.
As shown in FIG. 11A to FIG. 11E, the sub areas SA0, SA
When macro blocks 0, 17, 18, 13, and 26 are selected in order from 1, SA2, SA3, and SA4, they are described as (0, 17, 18, 13, 26). This is used as a key and recorded on the tape. And i
= 0,1, ... 16, (i, 17 + i, 18 +
A set of 5 macroblocks i, 13 + i, 26 + i) (Mod 27) is selected and used as the buffering timing.

As described above, if the initial value of the order of macroblocks is changed in each sub-area, deshuffling cannot be correctly performed if the key is not known.

Next, the structure on the reproducing side will be described with reference to FIG.

In FIG. 7, magnetic heads 17A and 17B are provided.
Reproduction data from the channel decoder 3 via a rotary transformer (not shown) and reproduction amplifiers 31A and 31B.
2 and the ATF circuit 52, respectively. It is supplied to the channel decoder 32 and the ATF circuit 52, respectively. The channel decoder 32 demodulates (decodes) the channel code, and the output signal of the channel decoder 32 is supplied to the TBC circuit (time axis correction circuit) 33. In this TBC circuit 33,
The time-axis fluctuation component of the reproduction signal is removed. ATF circuit 5
2, the reproduced pilot signal f is generated as described above.
A tracking error signal is generated from the level of the crosstalk component of 2, and this tracking error signal is supplied to, for example, a phase servo circuit (not shown) of the capstan servo.

The reproduced data from the TBC circuit 33 is ECC
It is supplied to the circuits 34, 44 and 46, and the error correction using the product code and the error that cannot be corrected are performed. The ECC circuit 34 performs error correction and error correction on video data (including audio data recorded in the video data recording area), and the ECC circuit 44 corrects error in audio data recorded in the audio data recording area. The ECC circuit 46
Performs subcode error correction.

The reproduced subcode is taken out from the output terminal 43S of the ECC circuit 46. This subcode is supplied to a system controller (not shown) for controlling the operation of the entire VTR.

The output signal of the ECC circuit 44 is supplied to the audio processing circuit 45, processed necessary for reproducing the audio signal, and output from the output terminal 43A1 to a circuit (not shown).

The output signal of the ECC circuit 34 is supplied to the frame decomposition circuit 35. The frame decomposing circuit 35 separates the respective components of the block coded data of the video data, and at the same time, changes the clock of the recording system to the clock of the image system. Frame disassembly circuit 35
The respective data separated by is supplied to the block decoding circuit 36, and the restored data corresponding to the original data is decoded for each block.

The output of the block decoding circuit 36 is supplied to the deshuffling circuit 53. The deshuffling circuit 53 returns the shuffled data to the original position. The output of the deshuffling circuit 53 is the distribution circuit 3
7 is supplied.

The distribution circuit 37 separates the decoded data into a luminance signal and a color difference signal. The luminance signal and the color difference signal are supplied to the block decomposition circuits 38 and 39, respectively. The block decomposing circuits 38 and 39, contrary to the block circuits 5 and 6 on the reproducing side, convert the decoded data in block order into raster scan order.

The decoded luminance signal from the block decomposition circuit 38 is supplied to the interpolation filter 40. In the interpolation filter 40, the sampling rate of the luminance signal is from 3fs (fs is a color subcarrier frequency) to 4fs (4fs = 13.
5 MHz). The digital luminance signal Y from the interpolation filter 40 is taken out to the output terminal 43Y.

On the other hand, the digital color difference signal from the block decomposition circuit 39 is supplied to the distribution circuit 41, and the line-sequential digital color difference signals U and V are separated. Digital color difference signals U and V separated by the distribution circuit 41
Are supplied to the interpolation circuit 42 and are interpolated. The interpolating circuit 42 interpolates the data of the thinned pixels by using the restored video data. The interpolating circuit 42 obtains the digital color difference signals U and V having a sampling rate of 4fs and outputs the output terminals. It is taken out to 43U and 43V, respectively.

The audio data recorded in the video data recording area output from the ECC circuit 34 is supplied to the memory 49 and stored therein after being subjected to error correction. The ECC circuit 34 also stores an error flag indicating the position of the error that could not be corrected in the memory 49.
Supply to. In the memory 49, the data that is input corresponding to this error flag and that could not be error-corrected is also written. The data written in the memory 49 is supplied to the compression audio decoding circuit 50, and compression decoding is performed. The decoded data is further interpolated by the interpolation circuit 5
1 is supplied. In the interpolation circuit 51, the data corresponding to the error flag is interpolated. Interpolation circuit 5
The output of 1 is output to a circuit (not shown) via the output terminal 43A2.

Further, the signal output from the TBC circuit 33 is input to the f _T signal processing circuit 47. The f _T signal processing circuit 47 detects the sync and ID in the ATF area from the input signal. Then, the position is determined from the data (sync number) indicating the sync position in this ID, and the counter 48 is operated at a predetermined timing. The counter 48 controls after-recording with a timing signal corresponding to the reproduction position of the magnetic heads 17A and 17B as a reference of the timing signal output from the output terminal 43T.

The f _T signal processing circuit 47 also includes ATF1,
The above-mentioned key signal written in 2 is detected. This key signal is supplied to the block decomposition circuits 38 and 39 and the distribution circuit 41. These circuits perform block decomposing processing and distribution processing corresponding to the key signal, set the order of the deshuffling circuit 53, and perform descrambling.

[0074]

According to the present invention, scrambling is performed by changing the shuffling order of macroblocks. Also, by changing the order of the shuffling within the same sub-area, it is possible to deal with clogs and scratch noises.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital video tape recorder to which a recording medium recording device of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of an embodiment of a digital video tape recorder to which the recording medium reproducing apparatus of the present invention is applied.

FIG. 3 is a diagram illustrating a positional relationship between digital video data and a key signal on a magnetic tape.

FIG. 4 is a diagram illustrating a state in which a magnetic tape is copied.

FIG. 5 is a diagram for explaining a track format of the magnetic tape of the present invention.

FIG. 6 is a block diagram showing the configuration of another embodiment of the recording system of the digital video tape recorder to which the present invention is applied.

FIG. 7 is a block diagram showing the configuration of another embodiment of the reproducing system of the digital video tape recorder to which the present invention is applied.

FIG. 8 is a diagram used for explaining shuffling in a digital video tape recorder to which the present invention is applied.

FIG. 9 is a diagram used for explaining shuffling in a digital video tape recorder to which the present invention is applied.

FIG. 10 is a diagram showing a data arrangement of tracks during shuffling in a digital video tape recorder to which the present invention is applied.

FIG. 11 is a diagram used for explaining shuffling in a digital video tape recorder to which the present invention is applied.

FIG. 12 is a block diagram showing a configuration example when a magnetic tape is copied in a conventional digital video tape recorder.

[Explanation of symbols]

 2 Effective Information Extraction Circuit 4 Subsampling and Subline Circuit 5, 6 Blocking Circuit 8 Block Encoding Circuit 9 Framed Circuit 10, 11 Parity Generation Circuit 12, 14 Mixing Circuit 17A, 17B Magnetic Head 92 Scrambler 93 Key Signal Generation Circuit 98 magnetic head 102 descrambler 103 output terminal 104 key signal detection circuit

Claims (4)

[Claims] 1. A scramble is performed by changing the shuffling order of a macroblock formed by collecting blocks of component signals, and key information indicating the shuffling order of the macroblock is recorded in a predetermined area on a tape. Digital video signal recording device. 2. The shuffling order of the macroblocks is changed within the same sub-area.
An apparatus for recording a digital video signal as described above. 3. A digital video signal reproducing apparatus for descrambling by changing the order of macroblock deshuffling in accordance with key information in a predetermined area on a tape. 4. A digital video signal reproducing apparatus according to claim 3, wherein the order of deshuffling the macroblocks is performed within the same sub-area.