JPH01114275A - Video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To control the redundancy of a recording signal and to remove a skew stain by inserting blanking signals in which video signals are not included in respective segments, switching a head in the period of the signals and synchronizing signals recorded on a tape with the rotary phase of the rotary head so as to generate the signals at the time of recording. CONSTITUTION:The blanking signals with redundancy in which the video signals for head switching are not included (blanking signal) are inserted in respective segments obtained by dividing the video signals of one field into n-number ((n) is an integer of >=2). At the time of recording the video signals and the blanking signals on the tape, the video signals and the blanking signals are recorded with synchronizing with the pulse synchronized with the rotary phase of the head drum. Thus, the skew stain accompanied by head switching is not included in the reproduced video signals and the video signals which closely connect respective segments can be reproduced, and what is called an H array can accurately and easily be obtained.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a video signal recording and reproducing device, which divides a video signal within one vertical scanning period into a plurality of segments, and divides the signal of each segment into a plurality of segments. The present invention relates to a recording signal generation method and apparatus suitable for dividing the recording signal into channels and recording over a plurality of tracks.

4. [Prior Art] As a conventional example of a magnetic recording/playback device using the so-called segment recording method, in which one vertical scanning period (one field) of a video signal is divided into a plurality of pieces and recorded on a magnetic tape, there is a magnetic recording/playback device for commercial use such as broadcasting stations. There is a 4-head VTR.

For details, see 1, for example, the literature (Japan Broadcasting Publishing Association,
(edited and supervised by the Television Network Society, Minoru Inazu, Takashi Iwasawa, VTR Technology). Above segment recording method VTR
Since one field of a video signal is divided into multiple tracks and recorded, during playback, there is a so-called skew (time axis A time axis correction circuit is essential to correct sudden changes.

As a method of correcting this ski,
As detailed in Chapter 1), the delay time of the video signal is made variable according to the above skew amount via a variable delay line, etc., and the horizontal blanking period of the video signal, more specifically, the horizontal synchronization. A time axis correction method is known in which the phases of a video signal and a horizontal synchronization signal are made continuous by temporally expanding or contracting the front porch period immediately before the signal.

According to the above conventional method, the amount of skew that can be corrected is determined by the time width of the front porch of the video signal, and in the current television system, the limit is about 1 to 2μ, 9U.

On the other hand, current home VTRs do not use segment recording as described above, and one field of the video signal is
The so-called helical scan type that records on one track is generally used, but this is done in order to make the VTR even smaller and lighter by reducing the diameter of the rotating drum, or by increasing the number of rotations of the rotating drum. In order to improve image quality,
Furthermore, new VTRs are capable of recording video signals with a bandwidth several times wider than conventional TVs, similar to so-called high-definition TVs, which provide much higher definition and picture quality than current TV systems.
In order to realize this, attempts have been made to perform segment recording as described above in home VTRs as well. However, in helical scan home VTRs, due to manufacturing constraints, the finishing precision of mechanical systems such as the rotating head system and tape transport system is not necessarily sufficient (and considering the storage conditions of tapes in general households). , the amount of skew generated above is several μ
sec, and in consideration of compatible playback, it is necessary to allow for an additional margin in the above value.

In addition, according to some of the methods proposed for the above-mentioned high-definition television, 1 document (Television Society Technical Report VOL, 7
．． 44, March 1984; “High Definition Television Satellite 1”
As described in "Channel Transmission System MUSE"), the horizontal blanking period allocated to the video signal is small (1 μsec or less).

Furthermore, before high-definition television broadcasting begins in earnest recently, it is being considered to use high-definition television for commercial purposes as a closed system in mini-theaters and the like. The VT4 provided for this system is also the above-mentioned home VTR.
It is a helical scan type according to the
It is equipped with a mechanism using a small cassette. However, the purpose of its use is only to capture playback images on a large screen in mini theaters, etc., and it is a broadband product.
- It is necessary to obtain good image quality by recording TV signals as they are in the baseband band without using band compression technology.

For this reason, recording methods have been attempted in which the input video signal is divided into a plurality of channels to narrow the signal band per channel, and one field of data is divided into a plurality of segments. At this time, in addition to countermeasures against skidding associated with segmented recording, another major challenge is to realize H alignment between tracks, which occurs when multiple channel signals are recorded on adjacent tracks.

As mentioned above, in both the current television system and the high-definition television system, it is extremely difficult to completely eliminate the ski distortion that occurs in the reproduced screen using conventional systems. Furthermore, in systems that involve channel division in addition to segment division, the head mounting between channels is difficult.

Due to factors such as cylinder rotation phase control errors during recording,
Achieving the so-called H arrangement on the tape pattern is also a serious problem, making it difficult to realize a VTR that achieves the above objective.

・　8　・ Another conventional example using the above segment recording is as follows.

One example is a so-called digital VTR that converts a video signal into a digital signal and records it in the form of a PCM signal; As a result, the transmission rate of PCM signals recorded on magnetic tape is extremely high (the recording density of the tape is significantly reduced, making it difficult to obtain sufficient recording time, and the signals handled have become extremely broadband). This poses a major obstacle to its widespread use for household use, as it is technically difficult.

In order to secure sufficient recording time and obtain sufficient image quality, it is an important challenge for those skilled in the art to realize the segment recording using an analog method instead of using the digital method.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, since one field is divided into a plurality of tracks and recorded, it is necessary to completely eliminate skew distortion caused by head switching within one field when reproducing the same. However, 1. For example, in a VTR that records high-definition television signals, redundancy in the recorded signal must be kept as low as possible in order to reduce the recording density. There is a problem in that the overlap area of redundant signals and heads must also be largely limited.

In view of these problems, an object of the present invention is to provide video signal recording with a configuration that limits the redundancy of recorded signals and can stably and reliably remove skew distortion, thereby making it possible to easily realize the segment recording described above. The purpose is to provide a playback device.

[Means for solving problems]

The above purpose is to divide one field of video signal into two segments (n is an integer of 2 or more), and between each segment, a redundant blanking signal (hereinafter referred to as When recording the video signal and blanking signal on the tape, the video signal and blanking signal are recorded in synchronization with a pulse synchronized with the rotational phase of the head drum. This can be achieved by

[Effect]

According to the above-described method, a blanking signal that does not include a video signal between each segment of the reproduced signal is obtained,
Since the heads can be switched within the period of this blanking signal, the reproduced video signal does not include ski distortion caused by the head switching (it is possible to reproduce a video signal with good connections between segments). becomes possible.

Also, the signals recorded on the tape during recording.

Results produced synchronously with the rotational phase of the rotating head.

The horizontal synchronization positions on the tape between adjacent tracks coincide in the direction perpendicular to the track longitudinal direction, so-called H
The alignment can be realized accurately and easily.

〔Example〕

The present invention will be explained in detail below using examples.

Fig. 1 is a block diagram showing an embodiment of an 11° device based on a two-channel split recording method (recording when the present invention is applied to a video signal recording/reproducing device, and Fig. 3 shows waveforms for explaining its operation. 4 are diagrams showing track patterns on a magnetic recording medium (tape) obtained by the above-mentioned apparatus.

In FIG. 1, a magnetic tape 1 is connected to a capstan motor 2.
The capstan motor 2 is controlled to a constant rotational speed by the capstan servo circuit 3. The magnetic heads 4α, 5α and 4h, 5h have different azimuth angles, are mounted on the disk 6 at a facing angle of 180°, and are rotated together with the disk 6 by a disk motor 7. Also.

In the above magnetic head, 4α and 4b, and 5α and 5b
Tracks having different azimuth angles and adjacent to each other are formed on the tape 1. At this time, the tape 1 is wound around the disk 6 in 1800 stripes, so that the parts where the heads 4α and 5α or 4h and 5h are in simultaneous contact with each other on the tape 1, that is, on the track, are the shaded parts in FIG. Magnets 8α and Bb corresponding to the front and rear overlap areas are mounted at an opposite angle of 180°, and this is detected by the tack head 9 and a tack pulse (second pulse) synchronized with the rotation of the magnetic head is generated. C) in the figure is obtained from the tack head 9. This tank pulse from the tack head 9 is sent to heads 4α, 4b by a phase adjustment circuit 10.
, 5α and 5h and the tape 1 are phase-adjusted so that they have a predetermined relative positional relationship, that is, after being delayed by a time τ0 as shown in FIG. 2C, the output is sent to the pulse generation circuit 1. Supplied.

This pulse generation circuit 11 generates a pulse with a duty ratio of 50% (d in Fig. 3) synchronized with the rotation of the heads 4α to 5b.
, hereinafter referred to as a head switching signal) is output.

On the other hand, 140 in FIG. 1 is a synchronization information output circuit, which outputs vertical synchronization information VS (b in FIG. 3) based on the horizontal synchronization signal HD and vertical synchronization signal VD input from the terminals 201 and 202. The vertical synchronization information S is supplied to the disk servo circuit 12 as a servo reference signal during recording.In this disk servo circuit 12, the circuit 140
More specifically, as shown in FIG. 3, the vertical synchronization information S (h in FIG. 3) and the head switching signal are synchronized so that both the vertical synchronization information S and the head switching signal are phase-synchronized with each other. (d in Figure 3) so that the phase difference time is τ1,
The rotation of the disc motor 7 is controlled. Also.

Although the information vS in units of vertical synchronization is used as the servo reference signal in the above description, similar control is possible even if the servo reference signal is a frame period signal.

Generally, one field of a video signal is divided into n segments, and each segment is further divided into, for example, two channels, thereby converting one field of video signal into 2rL tracks. The case where the data is recorded separately will be explained below as an example.

First, when the field frequency of the video signal is fo, the rotation speed M of the disk motor is determined by the disk servo circuit 12 so as to satisfy a quadratic equation.

M=Mx le (rp-t)...
・・・・・・・・・(1) Specifically, assuming a high-quality TV signal with 1125 scanning lines as the input video signal,
f6 "" 60 Hz r rL" 3° Therefore, from the above equation (2), a case of 3-segment recording where M=901p, ? will be explained.

Now, the number of horizontal scanning lines (number of lines) X of the video signal per track that can be recorded in a period of 180° in the longitudinal direction of the track (period indicated by T in Figures 3 and 4) is the number of horizontal scanning lines (number of lines) per field. If the number of lines is N, then x--L (lines)
・・・・・・・・・・・・・・・(2)
It is given by n. Substituting the number of lines per field of a high-definition TV signal N = 562°5 into (2) to find X, we get: X = 93.75 (lines)...
......(3). In the present invention, as will be described later, in a period T of 180° in the longitudinal direction of each track,
] (The largest integer that does not exceed X, and in equation (3), (X] =
93) It is configured to record video signals below the line.

In the embodiment shown in FIG. 1, the number of lines to be recorded in the period T is set per track (X)〉Nt = 85: segment 1, 3.5〉N
2=86: Segment 2, 4.6. Here, the video signal of the first field (odd field) is segment 1°2.3, and the video signal of the second field (even field) is 15. - Image signals are recorded in segments) 4, 5.6. Further, the subscript numbers 1 to 512 shown in FIGS. 3 and 4 above indicate line numbers of video signals within one field recorded on the tape.

The signal processing system during recording will be explained using FIG. 1 again.

In Figure 1, 200α, 200b, and 200 (? are the input terminals for the R signal, G signal, and B signal, respectively.

300α and 300b are A-ch and B-, respectively.
This is a video signal output terminal for recording Ch. 101 is a terminal 200a.

Color difference signal CI from input video signals from 200b and 200C.

C2 is a matrix circuit that generates the luminance signal Y.

102, 103, and 104 are input color difference signals C, respectively.
1, C2 and an A/D converter that converts the input luminance signal Y into digital signals; 105 is a reference clock generation circuit that generates a reference clock that is phase-locked (GEN LOCK) with the input horizontal synchronization signal; 106 is a write clock generation circuit , 107 are vertical filters, 108 and 109 are line selection circuits that select signal switching for each line, 110 and 111 are C-system and Y-system memories, respectively, 112 is a write address generation circuit, and 113 and 114 are switching (SW) )times·
16. road, 115 is a synchronous burst generation ROM, 116 is a read address generation circuit, 117 is a read start signal generation circuit, 118 is a read clock generation circuit, 119,
120 is a D/A converter.

The write clock generation circuit 106 generates a sampling clock by frequency-dividing the reference clock generated by the reference clock generation circuit 105, and supplies the clock of frequency fc to the C-based A/D converters 102 and 103. Y
A clock with a frequency of fr is sent to the system A/D converter 104, and the clock is also supplied to the write address generation circuit 112. The write address generation circuit 112 is composed of a counter, etc., and receives the vertical synchronization signal VD and horizontal synchronization signal HD as input and generates synchronization information (horizontal H8, vertical VS). A write address synchronized with is generated and supplied as a write address signal to the memories 110 and 111.

This address signal is sequentially updated in each horizontal scanning period by the horizontal synchronization information H8.
The video signals input from 00α, 200h, and 200C are clocked by the write clock output from the circuit 106, and the C1 and C2 signals are set to f. At the same frequency.

The Y signal is sampled at a frequency fr, and sequentially converted into digital signals by the C-system A/D converters 102 and 103 and the Y-system A/D converter 104, and these digital data are processed according to the address from the circuit 112. rows () are sequentially written to memories 110 and 111 in horizontal scanning period units.

Here, the memories 110 and 111 each have an A-ch (
It has memories for two channels, A-Ch and 13-ch (B channel), and the input digital data is distributed line by line to the memories of A-Ch and 13-ch (2 channels). Split)
. The line selection circuits 108 and 109 realize this kind of function.1 For example, data on odd lines (1, 3, 5,...) is stored in the A-ch memory, and data on even lines is stored in the B-ch memory. Data of (2, 4, 6, . . .) is written. In the case of a C-based memory, there are two types of color difference signals, C1 and C2. For example, C1 is written for odd lines and C2 is written for even lines, and recorded and reproduced as line sequential signals. Therefore, it is necessary to limit the vertical band of the C signal, and the vertical band is limited by the vertical filter 107 after A/D conversion.

Note that the approximate memory capacity of the memories 110 and 111 is that it can store information for about several tens of lines of input video signals (there is no need to provide a large capacity memory such as field memory or frame memory. Memory configuration An example is shown in Fig. 7. Fig. 7 shows a configuration example of the Y system memory 111 shown in Fig. 1, and the A-ch'f system memosa memory 111.
(z, B-Ch Y system memory 111-b is each composed of four memory banks α1 to α4. h1 to h4, and one memory bank has a data capacity of, for example, eight lines. First, 8-bit digital data sampled by the Y-system A/D converter is input to the data input terminal 130.The selection circuit 109 sends the input data to either the A-Chh'fJ or 13-Ch memory. In this embodiment, data on odd lines is input to the A-ch memory, and data on even lines is input to the B-ch memory.A-Ch memory 111
On the input side of the -α, B-C memories 111-h, there is a switch 111- that switches the memory bank at the time of writing.
C1, 111-hl, on the output side there is a switch 111-C2r 111-b2 that changes the memory bank during reading.
z is equipped.

Since the memory capacity per bank is 8H as mentioned above, the line numbers of each memory bank and the data stored therein are as shown in the table of FIG. That is.

For example, memory α1 has the first 8 odd lines (line numbers 1, 3, 5, 7, 9, 11.13°15).
The 17th line and subsequent lines are stored in the memory α2, and the 65th line and subsequent data are stored in the memory α1 again. With such a memory configuration, by appropriately controlling the switch 111-C1 that selects the write memory bank and the switch 111-IZ2 that selects the read memory bank, writing and reading can overlap on one memory. It is possible to avoid this.

Regarding the control of the above switches, switch 11 during writing
For 1-IZI and 111-hl, the input video signal
20 ・It operates according to the line number. Designation of these switches and the write address on the memory is performed by the write address generation circuit 112.

FIG. 9 shows a more detailed block diagram of the write address generation circuit 112, and FIG. 10 shows a timing diagram showing its operation. As shown in FIG. 9, the write address generation circuit is
Line counter 112 that receives synchronization information VS and H8 as input
-1, a decoder 112-2 that decodes the output result of the line counter 112-1; a line counter 112-3 that uses the output result of the decoder as a reset input and uses H8 as a clock source; a decoder that decodes the output result of the counter; 112·n, OR gate 112-6. It is composed of a counter 112-5 whose reset inputs are the write clock WCK and the output result of the OR gate. First, the line counter 112-1 is reset by vertical synchronization information VS, which is sent only once in each field (H8), and is reset by vertical synchronization information VS, which is sent once in each horizontal synchronization (H8).
Count the number of pieces. The decoder 112-2 receives a signal R1 which changes from L level to H level when the counter 112-1 reaches a predetermined count value, for example 50.
Output. Next, the line counter 112-3 starts counting using H8 as a clock from the time when the signal R1 becomes H level. The least significant bit Qo of the line counter 112-3 is used to determine whether the line number is odd or even. When the line number is odd, that is, when Qo or the signal S is at L level, the selection circuit 109 in FIG. 7 is set to the A channel side.

Data is transferred to the memory on the A channel side.

Conversely, when the line number is even, that is, Qo or signal S is H.
At level, the selection circuit 109 selects the B channel side,
The data is transferred to the memory on the B channel side. Next, the 2nd, 3rd and 4th bits of the line counter 112-3, that is, the 3 bits Ql, Q2, Q3, are address signals A8, A9, which give the address of the upper 3 bits of each memory bank having a capacity equivalent to 8 lines. It operates as an AIO and is updated every two lines. Which line number data is stored in each memory bank is as shown in FIG. 8, and its control is performed by SW 11 in FIG.
1-α1. and 111-hl switch. These switches are controlled by the outputs M1 to M4 of the decoder 112.n in FIG. Memory α2 at L level
and h2. When M3 is at L level, memories α3 and ba, M
When 4 is at L level, memories α4 and h4 are respectively selected.

On the other hand, counter 112-5 provides addresses AO-A7 for data within one horizontal interval.

Using the write clock WCK as a clock, the count value is reset for each horizontal synchronization information H8, and when the count value of the line counter reaches 1, for example, 512, the counting operation is controlled via the OR gate 112-6 to stop.

In this embodiment, the address within one horizontal interval is 8 bits,
That is, the configuration is such that addresses from 0 to 255 are given. The write address is controlled as described above, and the input video signal is sequentially written into the memory as digital data.

The above operation has been explained for the Y-system memory 111, but the basic operation for the C-system memory 110 is also the same. The only difference is the number of data within the horizontal period.

Next, referring to FIG. 1 again, the reading operation from the memory will be explained. First, the read clock generation circuit 118
A read clock RCK is generated from the reference clock generated by the reference clock generation circuit 105. A read address generation circuit 116 counts the read clock RCK and generates a read address in synchronization with a read start pulse generated by a read start pulse generation circuit 117 which receives the cylinder tack signal or head switching signal as input. The above reading start pulse is the third
The signal shown in f in the figure is a head switching signal (third
It shows pulses given constant delay amounts τ2 and τ3 (FIG. 3C) from the rising or falling edge of FIG. 3d). Data is read from the memory in synchronization with the read start pulse, and FIG. 11 shows an embodiment of a read address generation circuit for first realizing this operation.

・24・ In FIG. 11, 116-9 is the input terminal for the read start pulse R8 sent from the read start pulse generation circuit 117, and 116-10 is the read clock R.
This is the input terminal of CK. The read start pulse R8 input from the terminal 116-10 is synchronized by the latch circuit 116-1 with the read clock RCK from the terminal 116-9. The output from the latch circuit 116-1 is input to the reset terminal R of the counter 116.n via the OR gate 116-3, thereby resetting the counter 116.n. Further, the read clock RCK from the terminal 116-9 is supplied to the clock terminal CK of the counter 116.n via the AND gate 116-2. 116-
8 is an RS flip-flop which is set by the output from the circuit 116-1, and as a result, the output Q becomes a high level H. As a result, the clock RCK from the AND gate 116-2° terminal 116-9 is output to the counter 116.
・Supplied to n, clock counting is started.

116 to 5 are decoders that decode the count value of the counter 116.n, and the count value of the counter 116.n0 is set to be equal to the number of clocks of the write clock WCK within one horizontal scanning period in the case of this embodiment. A pulse is output when the value of N is set. The output pulse (g in FIG. 3) from this decoder 116-5 is supplied to the reset power R of the counter 116.n via the OR gate 116-3, and thereby the counter 116.
- n is reset again and calculation is restarted. The above operation is repeated based on the output pulse from decoder 116-5. Calculation output AO~ from counter 116・n
A7 is supplied as the lower 8 bits of the read address signal of the memory 111.

In the above series of operations, the output pulse from the decoder 116-5, that is, the pulse generated at timing 1 in FIG. It also shows the starting position,
Signal processing 1 for one horizontal opening interval, which will be described later, such as adding a horizontal synchronizing signal or a burst signal, is performed using this signal as a reference.

Next, the output from the decoder 116-5 is sent to the counter 11.
It is input to the clock input CK of 6-6. Also, the counter 116-6 is reset manually R.

The output from the latch circuit 116-1 is supplied, whereby the counter 116-6 is reset and the decoder 11
．． At step 6-7, the count value of the counter 116-6 is decoded, and when the count value of the counter 116-6 reaches Nl (set to NZ""85 in this embodiment), the pulse N1 is generated.
Output. On the other hand, the decoder 116-7 receives a signal L which controls the switch 111-α2*111-b2 in FIG.
1 to L4 are also generated. The above signals L1 to L4 are switch 1
This signal has the same function as M1 to M4 that control 11-α1.111-bl, and is a signal that selects from which of the four memory banks data is to be read.

The count values of the counter 116-6 are Qo, Qt,
Q3 is supplied as the upper 3 bits of the read address signal for each horizontal scanning unit of the memory.

Next, the decode pulse N1 outputted from the decoder 116-7 is applied to the flip-flop circuit 116-8/27.
- It is input to the glue set terminal, and its output Q (indicated by i in Figure 3) becomes a low level L. As a result, AND gate 116-2 is closed and counters 116.n and 1
Counting of 16-6 is temporarily stopped.

The above operation is repeated at the period T of the read start pulse R8 from the terminal 116-10. Here, data is sequentially read from the memories 110 and 111 according to the read address signal generated by the above operation, and the data from the C-system and Y-system memories of the A channel is transferred to the switching circuit 113. Data from the Y-system memory is input to the switching circuit 114, respectively. on the other hand,
Reference numeral 115 denotes a synchronization and burst generation ROM, which serves to generate digital data necessary to generate a horizontal synchronization signal and a thrust signal to be added to each horizontal synchronization interval of a signal to be recorded. This ROM is also controlled according to the read address generated by the read address generation circuit 116, and sends ROM output data to the switching circuits 113 and 114 at predetermined timing. The switching and 28° circuits 113 and 114 transfer continuous data to the next stage by appropriately switching the output data from the synchronization/burst generation ROM, the output data from the Y-system memory, and the output data from the C-system memory. send to Here, the data of the A channel is sent directly from the switching circuit 113 to the D/A converter 119;

B channel data is once input to the delay circuit 120-1 and sent to the D/A converter 120 after a predetermined delay time.

With reference to FIG. 2, it will be explained that the delay circuit 120-1 as described above is necessary only for B channel data.

FIG. 2(α) is a diagram showing a part of the track formed by the magnetic tape 1 and the magnetic heads 4α, 4b and 5α, 5b. As mentioned earlier, magnetic heads 4α and 5α are A
These are heads for channels, and include magnetic heads 4b and 5.
h is a head for B channel.

FIG. 2(b) shows the mounting positions of the heads on the cylinder, and shows the positions of the magnetic heads 4α and 4h.
Alternatively, 5α and 5b are each arranged at a distance of l in the longitudinal direction of the track as shown in the figure.

Therefore, these heads are on the tape at the second (α
) The heads for the A channel, ie, 4α, 5α, are positioned ahead of the heads for the B channel, ie, 4h, 5b, by a distance l on the tape. So, the track of A channel and the track of B
Between the tracks of the channel.

In order to realize the H arrangement, it is necessary to delay the recording signal supplied to the B channel head by a time corresponding to a distance l on the tape. here.

If the relative speed between the tape heads is Ui, the above delay time is 11/vt, and the delay circuit 120-1 delays the input data by a time of 13/vt, and then performs D/A conversion. It is only necessary to output it to the device 120.

The above embodiment is for the output of the A channel.

As a method of delaying the output of the B channel, a delay circuit is provided before D/A conversion, but in another embodiment, only the data of the B channel is sent to the A channel when reading data from the memories 110 and 111. A method of reading the data after delaying it by a predetermined time may also be considered, and the effect will be the same as that of the above embodiment.

Now, as described above (each data of the A channel and B channel input to the D/A converter is transferred to the D/A converter 119
and 120 into an analog video signal, and terminal 3
00LL and 300hVC are output. The line arrangement of the recorded video signals output to the terminals 300α and 300h is as shown in FIG. 3 (A channel) and A2 (B channel).

As a result of the above, the arrangement of video signals on the tracks recorded on the tape is as shown in FIG.

In Fig. 4, b Tl(Z r T2(Z + 'r
aa l T41Z is an A channel track recorded and formed alternately by heads 4α and 5a in FIG. 1, and head 4α records track TIL:L+T3a+...
...is track T2αr T41 with head 5cL
Z p "' is recorded. On the other hand, Txh r T2
hlT3h, T4h are B channel tracks recorded and formed alternately by heads 4b and 5b, and tracks T1h, T3h, . . .
Tracks T2hr, T4h, . . . are recorded at h.

In addition, as a signal to be recorded on each track in FIG.
31 to the output terminals 300α and 300A of the recording signal in the figure.
- At least one of the recorded video signals to be output includes vertical synchronization information of the field period.

Specifically, the tracks T1ar T4 (L + ·
Positions indicated by line numbers 1, 3.5 of... or line numbers 2 of tracks T1h, T4h +...
, 4.6, the vertical synchronization information may be generated and output from the circuit 115 in FIG.

As mentioned above, if vertical synchronization information is recorded near the scanning start point of the track in relation to the vertical scanning period of the video signal, it will be easier to detect the position during playback, and the field identification of the playback video signal will be easier. This makes it possible to identify the track being played.

In addition to the vertical synchronization information described above, some information has already been proposed. A triangular signal waveform, ie, a ramp waveform, used for nonlinearity correction of the reproduced video signal may be recorded. In this case, the above-mentioned vertical synchronization information is recorded on the line immediately following the recorded line or on a line in the vicinity thereof. By recording at such a position, it is possible to first detect the vertical synchronization information during playback, and then detect the ramp waveform using the position of the vertical synchronization information as a reference. There is an advantage that the detection of the ramp waveform for nonlinearity correction becomes more reliable, and the nonlinearity correction operation is performed stably and reliably.

Furthermore, in order to determine whether the fields are odd or even, the length of the vertical synchronization information may be made different between an odd field (first field) and an even field (second field). Although not shown in the figure, it is also possible to record information for determining whether a field is odd or even after the vertical synchronization information.

Now, in FIG. 4, the broken lines A-A and B-B correspond to the rising and falling edges of the waveform shown in FIG. A) shows the end point (B-B). Also,
The shaded area in FIG. 4 is a redundant area required when switching heads during playback, and the head rotation angle is 180°.
In the range of , one horizontal open period (hereinafter referred to as IH period) in the recorded video signal on the input side of the odd-numbered track, and a period slightly longer than half of the IH period on the output side of the track.

In other words, the length is (+Δ)H (where 0<Δ<<). On the other hand, the input side of even-numbered tracks has a length of +H1, and the output side has a length of IH. By determining the length of the redundant portion in this way and recording signals in synchronization with the rotational phase of the head using the method described above during recording, the relative positional deviation between tracks (αH = +H in Figure 4) can be reduced. It is also possible to absorb temporal fluctuations (jitter) of the rotating head during recording, and it is possible to realize a so-called H arrangement between adjacent tracks. In addition, during playback, by reliably switching heads in a specific area (that is, the shaded area in the figure) as shown in Figure 4, it is possible to eliminate discontinuities in the video signal caused by switching heads. Furthermore, the overlapping portion between the heads may be minute, including the shaded portion in FIG. 4, and the efficiency of use of the recordable area on the tape can be improved. That is, according to the recording method shown in FIG. 4, by providing the redundant period (indicated by the shaded area in the figure), head switching is performed during this period during playback, so that no defects occur in the video signal portion. It is possible to completely eliminate skew distortion on the playback screen due to head switching without creating a continuous portion.

Next, FIG. 12 shows an example of the number of sample clocks in the IH required to record and form a track pattern as shown in FIG. 4.

In FIG. 12, (α) is the area for head switching (
If the area indicated by diagonal lines (hereinafter referred to as the head switching area) is (++Δ)H on the input side in the head scanning direction and on the IH1 output side, (h) is the IH on the input side and +H1 output side in the head scanning direction.
The case is shown below. Here, assuming that the frequency of the sampling clock in the recording signal is, for example, 25.2 MHz, the IH
is formed from 1616 samples, in (α), the effective area other than the head switching area (in which video signals, etc. are recorded, hereinafter referred to as the active area) is 85H, (
In b), the active area is changed to 86H, and the track pattern shown in FIG. 4 can be formed.

, 35°Here, if Δ is formed to have a length corresponding to 216 samples, the length of one track is (α).

Ih)) In either case, (86,5+Δ)H, so the number of samples is 1616 samples x 86.5
H+ 216 samples, totaling 140,000 samples. In addition, the clock frequency is 25.2MHz
Multiplying the reciprocal of , that is, the time required per sample, gives 14
0,000 x 1/25.2 x 106, and a scanning time of 5.55 mztc per track is obtained. However, strictly speaking, the above-mentioned scanning time per track varies slightly due to control errors in the cylinder rotation servo system, but as mentioned earlier, in the present invention, the scanning time is synchronized with the cylinder rotation phase. Since a recording signal as shown in FIG. 12 is generated, the scanning time of one track and the time determined by the number of samples forming one track are the same under normal pressure.

Specifically, if the rotation of the cylinder is slightly slower than the normal rotation speed (and therefore the scanning time per track is longer), the number of samples corresponding to Δ increases, and the number of samples per track of the recording signal increases. The length of one track of the recording signal also increases depending on the scanning time.If the rotation of the ring becomes faster, the number of samples corresponding to Δ will increase, and the length of one track of the recording signal will also increase. As mentioned above, fluctuations in the scanning time per track caused by fluctuations in the rotational speed of the cylinder can be absorbed by increasing or decreasing the number of samples corresponding to Δ.

Next, FIG. 13 shows an example of the structure inside the above-mentioned IH.

In the example of FIG. 13, the IH is formed with 1616 samples.

It consists of horizontal blanking of 84 samples and a video signal of 1532 samples. Also, inside the horizontal blanking is a 30-sample horizontal synchronization signal.

It consists of a burst signal of 24 samples, and the burst signal forms one wave with 4 samples. Therefore, the frequency of the burst signal is 25,2
Since it is Z, it becomes 1/4 of that, 6.3■2.

This burst signal becomes a signal that provides a reference on the time axis when generating a sampling clock (or write clock) during reproduction, as will be described later. In this case, as in this embodiment, when one wave of the burst signal is 4 clocks, by setting the number of samples forming the IH to a multiple of 4 (1616 in this case), the burst in a certain horizontal period can be reduced. The phase of the signal and the burst signal between adjacent horizontal synchronous periods are continuous, and the phase of the write clock obtained during reproduction is also continuous, which is convenient in terms of clock generation circuit operation.

Although the above description has been made regarding the recording pattern shown in FIG. 4, the present invention is not limited to the recording pattern shown in FIG. 4, but has similar effects on other recording patterns. FIGS. 5 and 6 show recording patterns on a magnetic tape in other embodiments of the present invention, and the symbols in the figures indicate the third pattern.
This is the same as the case shown in the figure.

First, in the recording pattern shown in FIG. 5, the track 'r1 (Z r T
lb.

There is a redundant part of +H on the input side of the T3ct-T3h r... head, and (++ε)H on the output side (however, 0 ε〈+
) has redundant parts. On the other hand, truck T2a+
There is no redundant part on the input side of the head (T2brT4(L, T4b +...), and εH on the output side.Here, -generally in a helical scan type rotary head type video signal recording and reproducing device. In this case, the winding angle of the tape to the rotating cylinder is larger than 180° (there is an overlap of at least ±IH between opposing heads. Therefore, in FIG. 5 above, for example, the head entry side of track T2a Then, all the redundant parts above (
(, video signal from the beginning, more specifically line number 1
71 signals are recorded, but in reality, the same redundant portion as that recorded on the output side of track T1 (L) is recorded prior to the video signal. The above situation is the same between other tracks, and when the head scan changes from one track to the next, there is always signal overlap.Therefore, in the example shown in FIG. There is always a redundant period of (++ε)H between tracks, and head switching during reproduction can be performed appropriately during this period.

FIG. 6 shows a recording pattern when ξ is O in FIG. 5, and there is always a redundant period of +H between each track. In Figure 3-2, since the track deviation between 'r1cL, Tlh, T2a, and T2b (indicated here as αH) is +H, by setting the redundancy period to +H, the track T1h , T2a can be realized. Also, at this time, the redundancy period between each track is +
H, and under the condition of αH·nH, it is possible to minimize the above-mentioned redundant period.

FIG. 14 is a block diagram of an embodiment of a reproducing device for reproducing the video signal recorded on the magnetic tape as shown in FIG. 4 as described above, and FIG. 15 is a block diagram for explaining its operation. The waveform diagrams of each part are shown respectively.

In FIG. 14, the same parts are given the same numbers because they can be used in common with parts of the recording apparatus shown in FIG. 1. Since the operations of these common parts are the same as described above, their explanation will be omitted.

The video signals alternately reproduced from the tape 1 by the heads 4α, 4b and 5α, 5b are amplified to a predetermined level by the reproduction preamplifier 400, and then transmitted to the head 4α.

Output from 5α, that is, output signal on the A channel side・40
- 400-1 is input to the A-Ch time base correction circuit 410.

On the other hand, the output from the heads 4A and 5A, ie, the output signal 400-2 on the B channel side, is input to the B-ch time axis correction circuit 420. In the A-ch time axis correction circuit 410, the reproduced signal is first demodulated by the FM demodulator 411, and a video signal as shown in FIG. 15 a1 is obtained. - way, f
Similarly, for 3-ch, a video signal of the form a2 is obtained. The following operation will be explained only for the A channel, but the same operation is performed for the B channel as well. Now, the demodulated video signal is input to the primary synchronization separation circuit 412, where it is input to the primary synchronization separation circuit 412 as shown in FIG. 12C.
Vertical synchronization information and horizontal synchronization information (FIG. 15d), which are recorded only once in the field, are detected, separated, and output. Here, the first IH of one field is assigned as the vertical synchronization information. Next, this synchronization information is input to the head switching signal generation circuit 418.

The head switching signal generation circuit 418 first detects the last horizontal synchronization information of each segment as shown in FIG. 15C based on the vertical synchronization information and horizontal synchronization information. Next, as shown in FIG. 15f, a square wave having a constant delay time width τ is generated from the signal e. By dividing the frequency by two in synchronization with the falling edge of the above signal f, a signal as shown in da is obtained, and this signal is at a high level (H
), the signal from the head 4a is selected, and when the level is low (L), the signal from the head 5a is selected, so that the reproduction preamplifier controls the input from the head.

FIG. 16 shows an example of a preamplifier that allows input signals from each head to be selected using the method described above. As mentioned above, the reproduced signals from heads 4α and 5α are A-ch
After being selected by the switching means 469 controlled by the head switching signal, it is output as a continuous signal to the A-c output terminal 465. Further, the above operation is the same for B-ch, and the reproduced signals from heads 4h and 5h are 33-
After being selected by the switching means 470 according to the ah head switching signal, it is outputted to the B-Ch output terminal 467 as a continuous signal. According to the above method, since the signals from the two opposing heads are switched in the head switching area provided in the signal during recording, no loss occurs in the video signal due to head switching.

The reproduction signal processing operation will be explained using FIG. 14 again. F
The signal demodulated by the M demodulator 411 is then sent to the A/D converter 4
14 and is converted into digital data. At this time, the sampling clock used for A/D conversion is the clock generated by the write clock generation circuit 413, and the synchronization information in the reproduced signal after demodulation or the 13th
This is a clock synchronized with the burst signal shown in the figure.

therefore.

The above clock is the temporal fluctuation that occurs during the playback process.

That is, it is a clock synchronized with jitter, and by processing the digital data sampled by this clock using the clock from the reference clock generation circuit 438 with a crystal oscillator, the above jitter can be removed from the reproduced video signal. is possible. Next, the digital data output from the A/D converter 414 is sequentially written into the A-ch memory 416 according to the write address generated by the write address generation circuit 415, and then generated by the memoria 43 address generation circuit 436. The data is output from the memory according to the read address. Here, the read address is generated based on the crystal-locked clock from the reference clock generation circuit 438.

Jitter has been removed from the digital data at the time it is read out from the A-ChhC library 416. The digital data output from the A-ch memory 416 is transferred to the A-ch memory 417 at a predetermined timing.
The data of the chC system memory 430Y system is A-ch'f
The data are transferred to the system memory 431, respectively.

The above-mentioned series of operations is similarly applied to the 13-ah signal, and the output data from the f3-ch time axis correction circuit 420 is sent to the 13-ch C system memory 432 l3-CA.
The data is distributed to the Y-system memory 433 and stored therein. Next, A-1? The output data of the Ac system memory 430 and the B-chC system memory 432 is input to the selection circuit 434,
Here, data is selected and output in a predetermined order, and the C-system VA
Inputs to converters 439 and 440. On the other hand, A-ch
Y-type memememory 43133-chY-type memememory 433
The output data of is input to the selection circuit 435, and data 44 is similarly selected and output and input to the Y-system D/A converter 441. As a result, C1°C2 and Y signals are outputted from each D/A converter, and these signals are outputted as R, G, and H signals through the matrix circuit 442.

In addition, the synchronization signal generation circuit 437 generates a horizontal synchronization signal HD (first
5i) and the vertical synchronization signal VD (FIG. 15)) are generated. Furthermore, from the synchronization signal generation circuit 437, 3
A reference signal (REF30) of 0 Hz is generated, and this signal is used as a reference signal for the servo system during reproduction to control the rotational phase of the cylinder. Specifically, the reference signal REF30
is the signal shown at h in FIG. 15, and the rotational phase of the disk motor is controlled so that the head switching signal DA is always temporally separated by τ from REF 30.

Note that the rotation of the capstan motor 2 is controlled by a capstan servo circuit 3, and this capstan servo circuit 3 is connected to the magnetic tape 1 and the head 4a.

It consists of a tracking control system and the like to control the relative positions of 4h, 5α, and 5h, accurately scan the recorded track with these heads, and reproduce the signal. It is used.

By the above servo control, the timings of the writing operation to the memory in the two time axis correction circuits 410 and 420 of the video signal reproduced from the head, and the timing of the reading operation from the memory are always kept in a constant relationship, and the timing of the reading operation from the memory is always maintained in a constant relationship. A series of signal processing is performed. As a result, terminal 450
The R, G, and B reproduced video signals output to α, h, and c are as shown in FIG. This results in a stable video signal restored to .

As is clear from the above, the possible amount of skinny correction by applying the present invention is (1+Δ)H.

However, H is one horizontal period of the recording signal (in this example, two
1616 clock periods with 5.2M11z sampling)
and Δ is 216 clock periods. This value can be said to be a sufficient skinny correction amount for a skew amount of 0.1H or less that occurs during actual reproduction.

Furthermore, since the above redundant period (1+Δ)H is generated in synchronization with the rotation of the head during recording, the above redundant period (1+Δ)H is located at a fixed position on the tape as shown in FIG. The recording position will not change. As a result, compatible playback becomes easy and reliable, and the performance and reliability of the device can be significantly improved.

Furthermore, in the embodiment shown in FIG. 1, the generation timing of the read start pulse R8 generated in the read start pulse generation circuit 117 (determined by τ2 and τ3 indicated by - in FIG. 3) is determined by the scan period of the head. By changing it appropriately for each T.

As shown in the track pattern diagram of FIG. 4, the relative recording pattern of adjacent tracks and horizontal scanning line units between adjacent tracks can be easily changed. Without being restricted by the amount of misalignment of horizontal scanning lines at the track end (αH shown in FIG. 4), which is determined according to the relative speed of Secondary effects such as being able to reduce interference caused by crosstalk from the track and providing a device that provides good image quality can be obtained.

Furthermore, as is clear from the above, according to the recording method of the present invention, all video signals to be recorded and reproduced are completely processed within the scanning period T of the head (within a period of 180° on the track), Further, according to the present invention, it is possible to easily detect the recording position on the tape of the head switching area that exists at both ends of each track, and moreover, the recording position can be detected from the reproduced video signal.

Since self-detection can be performed reliably, it becomes possible to reduce the overlapping area of several H, which was essential in conventional analog recording type VTRs, to about IH. In other words, the effective area on the tape can be expanded accordingly, and as a result, the recording time can be increased, which is a secondary effect. Furthermore, signals other than the video signal 1, such as conventionally known time-base compressed digitized audio signals, or tracking/48° control signals such as pilot signals, can be recorded to the extent that the overlap is reduced. It can also be used as an area, and the effect of enabling high-density recording of a variety of signals can also be obtained.

In addition, in this embodiment, only an example is shown in which a high-definition television signal is divided into two channels and the cylinder is rotated three times to record the divided three segments. It is of course possible to apply the present invention, and the same effects as described in the embodiments can be obtained. Furthermore, the signals to be recorded include not only baseband high-definition television signals, but also signals that have been subjected to some band compression, signals of current television systems such as NTSC, 'PAL, SECAM, etc. The present invention can also be applied to systems that have improved image quality such as resolution while being compatible with the system.

〔Effect of the invention〕

As described above, according to the present invention, in a video signal recording and reproducing apparatus that divides an input video signal into a plurality of channels and records each channel by dividing it into a plurality of segments, It is possible to completely eliminate time axis fluctuations and record and reproduce good and stable video signals. Furthermore, H alignment between adjacent tracks can be realized reliably and easily, and the redundant period in the recording signal required for head switching during reproduction can also be minimized, making it possible to increase the recording density of the tape.

As a result, it has become possible to easily achieve higher recording densities and longer recording times compared to conventional digital recording methods.This, combined with improved compatibility, reduces device costs.
It is possible to obtain effects such as significantly improving performance and reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a video signal recording device according to the present invention, and FIG. 2 is an enlarged view of the periphery of the head.
3 is a waveform diagram of each part in FIG. 1, FIGS. 4 to 6 are tape pattern diagrams, FIG. 7 is an example of a configuration of a memory for video signal processing, and FIG. 8 is a diagram of each part stored in the memory. 9 is a block diagram showing an embodiment of the write address generation circuit according to the present invention, FIG. 10 is a waveform of each part thereof, and FIG. 11 is an example of the read address generation circuit according to the present invention. 12 is a block diagram showing the pattern of one track of the recording signal according to the present invention, FIG. 13 is a waveform diagram showing the format of the video signal during one horizontal opening period according to the present invention, and FIG. A block diagram showing an example of a playback device according to the present invention, FIG. 15 is a waveform diagram of each part in FIG. 14,
FIG. 16 is a diagram showing an example of the configuration of a playback head amplifier. 102, 103...A/D converter for C signal. 104...Y signal A/D converter. 110...Memory for C signal, 111...Memory for Y signal. 115...ROM for synchronization/burst signal generation. 119...D/A converter for A channel. 120...D/A converter for B channel, 112...
-Write address generation circuit. 116...Read address generation circuit.

Claims (1)

[Claims] 1. A video signal of one vertical scanning period consisting of N horizontal scanning lines is divided into m channels (m is an integer of 2 or more) with each video signal of one horizontal scanning period as a unit. , the signals of each of the m channels are further divided into n (n is an integer of 2 or more) segments, each channel is equipped with at least two rotary heads, and m segments are transmitted in one head scan. By recording tracks adjacent to each other,
The video signal of one vertical scanning period mentioned above is scanned n times in total m
- In a helical scan type rotary head type video signal recording and reproducing device configured to divide recording into n tracks, an overlapping area where at least two rotary heads corresponding to each of the channels are in simultaneous contact with the magnetic tape. The video signal for one vertical scanning period is transmitted per block [
N/m・n] (the largest integer not exceeding N/m・n) so as to include video signals equivalent to the number of horizontal scanning lines within
means for dividing the m/n blocks into n blocks; and when sequentially recording the m/n blocks onto the m/n tracks, recording video signals in the m/n blocks in units of each block; time axis converting means for sequentially converting the time axis for each block in synchronization with the rotational angle of the rotary head arranged so as to perform horizontal scanning line by block, thereby generating a redundant period of a predetermined length between each block; A video signal recording and reproducing device, characterized in that the redundant period is recorded within the overlap area. 2. When one horizontal scanning period of the above-mentioned video signal after time-base conversion is 1H, the time axis converting means is configured to record m adjacent tracks in one head scan;
The amount of track deviation that exists between m adjacent tracks recorded in the next adjacent head scan is αH
(However, when 0<α≦1), the redundancy period recorded in the overlap area is set to a minimum αH and a maximum (1−
2. The video signal recording and reproducing apparatus according to claim 1, wherein the video signal recording and reproducing apparatus is set within the range of Δ+α)H (0<Δ<α). 3. The time axis conversion means converts, between m adjacent tracks recorded in one head scan, horizontal scanning line units of the video signal after time axis conversion in each of the m tracks. 3. The video signal recording and reproducing apparatus according to claim 1, further comprising means for controlling the time axis so that the recording positions are aligned with each other in a direction orthogonal to the longitudinal direction of the track. 4. The time axis converting means determines the recording position of the video signal after the time axis conversion in units of horizontal scanning lines in the m adjacent tracks recorded in the one head scan, and the recording position of the next adjacent track. The time axis is controlled so that the recording positions of the video signals after the time axis conversion in units of horizontal scanning lines in the m adjacent tracks recorded by head scanning are aligned in a direction orthogonal to the longitudinal direction of the tracks. 3. A video signal recording and reproducing apparatus according to claim 1 or 2, characterized in that the video signal recording and reproducing apparatus has means for: 5. The video signal recording and reproducing apparatus according to claim 1 or 2, further comprising means for recording horizontal synchronization information at a predetermined location within each redundant period. . 6. The time axis conversion means includes means for sampling an effective portion within a horizontal scanning line of the video signal, and converting the effective portion into a signal obtained by time axis conversion in units of horizontal scanning lines with a predetermined number of samples for a predetermined period. It has means for adding horizontal synchronization information consisting of a horizontal synchronization signal including a redundant part and a burst signal of a predetermined period with a predetermined number of samples, and the total number of samples in one horizontal scanning line of the video signal after time axis conversion is calculated. 2. The video signal recording and reproducing apparatus according to claim 1, wherein the number of samples is set to be an integral multiple of the number of samples in one cycle of the burst signal. 7. At a position near the head scanning start end after the redundancy period of at least one of the m adjacent tracks on which the signals of the m channels are recorded, vertical scanning is performed every vertical scanning period with a predetermined width. The video signal recording and reproducing apparatus according to claim 1, further comprising means for recording synchronization information. 8. On the track where the vertical synchronization information is recorded,
Claim 7, further comprising means for recording a triangular wave-like signal whose amplitude gradually increases linearly during a predetermined period after the recording position of the vertical synchronization information.
The video signal recording and reproducing device as described in .