JPS613519A - Pulse circuit - Google Patents

Abstract

PURPOSE:To ensure the operation of a switching Tr controlling the short-circuit/ opening of a capacitor by providing a delay characteristic to a delay drive source comprising a diode and a resistor. CONSTITUTION:Diodes 14, 15, 16 and resistors 17, 18, 19 constitute the delay drive source. Since the rising of an anode potential of the diode 24 is slow in comparison with that of the diode 15, when the potential of a power supply 20 starts rising, a transistor (Tr)12 is turned on by the anode potential of the diode 15, a mirror circuit 10 is actuated to turn on a Tr5 thereby discharging the electric charge of the capacitor 4. Thus, the anode potential of the diode 14 rises, a Tr13 is turned on, a mirror circuit 11 is actuated and then a Tr6 is turned on. As a result, the Tr5 is turned off, the capacitor 4 starts charging and an output of the inverter 2 goes to ''L'' when the potential reaches a prescribed potential.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pulse circuit that initially resets a pulse circuit such as a flip-flop when power is turned on.

[Prior art]

A conventional pulse circuit is shown in FIG. In Figure 1,
1 is a flip-flop, 2 is an inverter that inverts the logic level, 3 is a constant current source, 4 is a capacitor that is charged by the constant current source 3 when the initial reset is released, and 5 is for short-circuiting the capacitor 4 during the initial reset. 6 is a switching transistor that turns off switching transistor 5 when the initial reset is canceled; 7 and 8 are resistors for supplying base current to switching transistors 5 and 6; 9 is a level shift diode; 20 is a DC power supply for this circuit, and A and B are nodes.

Next, (a) a case where the DC power supply 20 starts up slowly and (b) a case where the DC power supply 20 starts up steeply will be explained.

First, case (a) will be explained using FIGS. 1 and 2. In FIG. 2, FIG. 2(a) shows the DC power supply 20
Figure 2 (b) shows that the potential of increases with time.
) shows the change in potential at node A, and Fig. 2(c) shows the change in potential at node B.
2(d) shows a change in the output terminal potential of the inverter 2, 21 is a straight line showing the rise of the potential of the DC power supply 20, 22 is a curve showing the potential of the node A, 23 is a curve showing the potential of node B, 24 is a curve showing the output terminal potential of inverter 2, 25 is a potential difference related to the initial reset time, 26 is the ground potential, 27 is a propagation delay time that determines the initial reset time, tl is the time when the switching transistor 5 starts to turn on, and t2 is the time when the switching transistor 6 starts to turn on.

When the power is turned on, the DC power supply 20 gradually rises as shown in FIG. From the relationship of the threshold levels of the switching transistor 6 including
It is turned on by IE and the potential of node A is set to logic level rLJ. In other words, the charge from the capacitor 4 is extracted. Then, the output terminal potential 24 of inverter 2 and the flip
Flop 1 positive terminal potential is logic level rHJ
Therefore, flip-flop 1 is reset. After that, when the potential of the DC power supply 20 rises by a potential difference of 25 and its level becomes 2VIE, the switching transistor 6
is turned on, and the switching transistor 5 is turned off because the base supply current disappears. From that point on, charging of the capacitor 4 by the current from the constant current source 3 starts.

When the potential 22 at the node A rises due to charging of the capacitor 4 and reaches the logic level "H", the output terminal potential 24 of the inverter 2 and the positive terminal potential of the flip-flop 1 become the logic level "L", and the flip-flop 1 The initial reset of is canceled.

In other words, the initial power reset has worked.

Next, case (b) will be explained using FIGS. 1 and 3. In this case, the switching transistor 5 at time t
, but before it is turned on sufficiently, time t2
There is a problem in that the switching transistor 6 is turned on and the reset terminal potential of the flip-flop 1 does not reach the logic level rHJ, that is, the initial reset is not performed.

[Summary of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a first switching transistor that determines the start time of initial reset, and a second switching transistor that determines the end time of initial reset. An object of the present invention is to provide a pulse circuit that prevents initial reset errors of pulse circuits such as flip-flops by turning on a transistor later than conventional ones to surely turn on a first switching transistor. In order to achieve such an object, the present invention provides a delay drive source composed of a diode and a resistor for imparting delay characteristics to the second switching transistor.

[Embodiments of the invention]

The present invention will be explained in detail based on examples.

FIG. 4 shows an embodiment of a pulse circuit according to the present invention.

In FIG. 4, 1o and 11 are PNP mirror circuits that provide base currents to switching transistors 5 and 6, 12 and 13 are NPN mirror circuits that provide base currents to the PNP mirror circuits, and 14, 15, 16, and 1
7.18.19 are diodes and resistors forming a delay drive source for supplying base current to the NPN mirror circuit 12.13; 21 is a signal connecting the collector of the PNP mirror circuit 10 and the base of the switching transistor 5; A line 22 is a signal line connecting the collector of the PNP mirror circuit 11 and the base of the switching transistor 6. In FIG. 4, the same or equivalent parts as in FIG. 1 are given the same reference numerals.

Next, the operation of this device will be explained using FIGS. 4 and 5. In FIG. 5, L3 is the time when the switching transistor 6 starts turning on.

In FIG. 5, the same or equivalent parts as in FIG. 3 are given the same reference numerals.

Diodes 14, 15, 16 and resistors 17, 18, 19 in FIG. 4 constitute a delay drive source, and diode 1
4 is connected in parallel to the diode 15 via the resistor 17, the rise of its anode potential is slower than that of the diode 15. Also, the diode 14 is NPN
The mirror circuit 13 is given a base potential, and the diode 15 is given a base potential to the NPN mirror circuit 12. Therefore, the NPN mirror circuit 13 is turned on after the NPN mirror circuit 12 is turned on. The ON signal of the NPN mirror circuit 13 is the ON signal of the PNP mirror circuit 11. It is transmitted through the signal line 22 to the switching transistor 6, and is connected to the NPN mirror circuit 1.
The ON signal of 2 is the PNP mirror circuit 10. Since the signal is transmitted to the switching transistor 5 via the signal line 21, the switching transistor 6 is turned on after the switching transistor 5 is turned on. In FIG. 5, the difference between time 1° when switching transistor 5 is turned on and time t3 when switching transistor 6 is turned on is the propagation delay time 27. In other words, this propagation delay time 2
7 is determined by the diodes 14 and 15, and this propagation delay time 27 ensures that the switching transistor 5 is turned on, thereby ensuring the initial reset.
Time t2 in FIG. 5 is the start time of the on-operation of the switching transistor 6 in the conventional example. Since the switching transistor 6 in this circuit starts its on operation at L3, the start of its on operation is delayed by 13-12 times compared to the conventional example.

Switching transistor 6 turns on at time t3.
1, the switching transistor 5 is turned off because its base potential becomes the ground potential 26.

When the switching transistor 5 is turned off, the capacitor 4 is released from the short-circuited state and starts being charged by the constant current source 3. When the potential due to charging increases and the potential at node A reaches the logic level rHJ, the output terminal potential 24 of the inverter 2 and the positive terminal potential of the flip-flop 1 reach the logic level rLJ, and the initial reset ends.

〔Effect of the invention〕

As described above, the present invention ensures the operation of the switching transistor that controls the short-circuiting and opening of the capacitor that performs the initial reset when the power is turned on, by giving the delay drive source composed of a diode and a resistor a delay characteristic. Since it is made of a single material, it has the effect of eliminating setting errors in pulse circuits such as flip-flops.

[Brief explanation of drawings]

Figure 1 is a conventional pulse circuit diagram, Figures 2 (a) to (d) and 3 (a) to (d) are waveform diagrams for explaining its operation, and Figure 4 is a diagram related to the present invention. A circuit diagram showing one embodiment of the pulse circuit, and FIGS. 5(a) to 5(d) are waveform diagrams for explaining its operation. 1...Flip-flop, 2...Inverter, 3...Constant current source, 4...Capacitor, 5.6
...Switching transistor, 10, 11...
・PNP mirror circuit, 12.13... NPN mirror circuit, 14, 15.16... Diode, 17, 1
8.19...Resistance, 20...DC power supply, 21.
22, 23.24...Potential, 25...Potential difference, 26...Earth potential, 27...Propagation delay time.

Claims (1)

[Claims] a capacitor that charges and discharges to initialize a pulse circuit such as a flip-flop when power is turned on; first and second switching transistors that charge and discharge the capacitor;
a constant current source that supplies a current to the switching transistor and supplies current to the capacitor when the initial reset is released; a first PNP mirror circuit that supplies a base current to the first switching transistor when the initial reset is released; a second PNP mirror circuit that provides a base current to the second switching transistor; a first NPN mirror circuit that provides a base current to the first PNP mirror circuit during initial reset; and a second PNP mirror circuit that provides a base current to the first PNP mirror circuit during initial reset; a second NPN mirror circuit that provides a base current to the circuit; and a delay drive that provides a base current to the first NPN mirror circuit and provides a base current that rises later than this base current to the second NPN mirror circuit. A pulse circuit characterized by comprising a source.