JPS6134186B2 - - Google Patents

Info

Publication number
JPS6134186B2
JPS6134186B2 JP56047774A JP4777481A JPS6134186B2 JP S6134186 B2 JPS6134186 B2 JP S6134186B2 JP 56047774 A JP56047774 A JP 56047774A JP 4777481 A JP4777481 A JP 4777481A JP S6134186 B2 JPS6134186 B2 JP S6134186B2
Authority
JP
Japan
Prior art keywords
register
vector
instruction
waiting
instruction information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56047774A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57161938A (en
Inventor
Shigeaki Okuya
Tetsuo Okagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56047774A priority Critical patent/JPS57161938A/ja
Publication of JPS57161938A publication Critical patent/JPS57161938A/ja
Publication of JPS6134186B2 publication Critical patent/JPS6134186B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
JP56047774A 1981-03-30 1981-03-30 Instruction control system Granted JPS57161938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047774A JPS57161938A (en) 1981-03-30 1981-03-30 Instruction control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047774A JPS57161938A (en) 1981-03-30 1981-03-30 Instruction control system

Publications (2)

Publication Number Publication Date
JPS57161938A JPS57161938A (en) 1982-10-05
JPS6134186B2 true JPS6134186B2 (zh) 1986-08-06

Family

ID=12784722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047774A Granted JPS57161938A (en) 1981-03-30 1981-03-30 Instruction control system

Country Status (1)

Country Link
JP (1) JPS57161938A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158441A (ja) * 1983-03-01 1984-09-07 Nec Corp パイプライン制御方式
JPS6116335A (ja) * 1984-07-02 1986-01-24 Nec Corp 情報処理装置
DE3750055T2 (de) * 1986-06-12 1995-01-05 Ibm Ablauffolgesteuerung und zugehörige Methode in einer Befehlsverarbeitungseinheit, um diese Einheit in einen Freigabe-, Ausführungs-, Halte- oder Auflösezustand zu versetzen.
JPH0673105B2 (ja) * 1988-08-11 1994-09-14 株式会社東芝 命令パイプライン方式のマイクロプロセッサ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51854A (en) * 1974-06-21 1976-01-07 Hitachi Ltd Deijitarukeisankino senkoseigyohoshiki
JPS5199427A (zh) * 1975-02-27 1976-09-02 Hitachi Ltd
JPS5421150A (en) * 1977-07-18 1979-02-17 Nec Corp Information processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51854A (en) * 1974-06-21 1976-01-07 Hitachi Ltd Deijitarukeisankino senkoseigyohoshiki
JPS5199427A (zh) * 1975-02-27 1976-09-02 Hitachi Ltd
JPS5421150A (en) * 1977-07-18 1979-02-17 Nec Corp Information processor

Also Published As

Publication number Publication date
JPS57161938A (en) 1982-10-05

Similar Documents

Publication Publication Date Title
US4507728A (en) Data processing system for parallel processing of different instructions
US5404552A (en) Pipeline risc processing unit with improved efficiency when handling data dependency
US4675806A (en) Data processing unit utilizing data flow ordered execution
JP2503164B2 (ja) デ―タ処理システム
US5261113A (en) Apparatus and method for single operand register array for vector and scalar data processing operations
US6219775B1 (en) Massively parallel computer including auxiliary vector processor
US5353418A (en) System storing thread descriptor identifying one of plural threads of computation in storage only when all data for operating on thread is ready and independently of resultant imperative processing of thread
JP2645669B2 (ja) データ処理システム
EP0213842A2 (en) Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
JPH0731597B2 (ja) 複数のマイクロプログラム制御式処理装置を備えるプロセッサ
JPH083786B2 (ja) 浮動小数点演算処理装置
US4967350A (en) Pipelined vector processor for executing recursive instructions
JP2008181551A (ja) ベクトルレジスタを備えたコンピュータにおけるベクトルテールゲーティング
JP3797570B2 (ja) セマフォ命令用のセマフォ・バッファを用いた装置と方法
US4853890A (en) Vector processor
EP0295646A3 (en) Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus
US5745725A (en) Parallel instruction execution with operand availability check during execution
US4974198A (en) Vector processing system utilizing firm ware control to prevent delays during processing operations
US5276822A (en) System with enhanced execution of address-conflicting instructions using immediate data latch for holding immediate data of a preceding instruction
JPS6134186B2 (zh)
JPS59106075A (ja) デ−タ処理システム
JPS6161416B2 (zh)
US5802384A (en) Vector data bypass mechanism for vector computer
JP2503984B2 (ja) 情報処理装置
US5327565A (en) Data processing apparatus