JPS6132557A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6132557A
JPS6132557A JP15305784A JP15305784A JPS6132557A JP S6132557 A JPS6132557 A JP S6132557A JP 15305784 A JP15305784 A JP 15305784A JP 15305784 A JP15305784 A JP 15305784A JP S6132557 A JPS6132557 A JP S6132557A
Authority
JP
Japan
Prior art keywords
resin
wire
chip
chip coating
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15305784A
Other languages
Japanese (ja)
Inventor
Kazuo Tominaga
富永　和雄
Masayoshi Sugiyama
杉山　正義
Isao Kojima
小島　勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15305784A priority Critical patent/JPS6132557A/en
Publication of JPS6132557A publication Critical patent/JPS6132557A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor device in molded structure having excellent damp-proofing and reliability by forming a chip coating in double structure of a resin having the small coefficient of linear expansion and a hydrophobic resin. CONSTITUTION:A resin 11 for chip coating having the coefficient of linear expasion in the same extent as an alumina pate 2 is mounted only onto an silicon chip 5 containing an Al wire 6, and a rubbery resin 12 for chip coating is fitted. The resin 11 for chip coating coats the Al wire 6 section, and has the small coefficient of linear expansion, thus applying slight thermal stress to the Al wire 6. Since the hydrophobic rubbery resin 12 for chip coating is also set up, infiltration more than before in moisture permeating from clearances, etc. among terminal boards 3a-3c and a cover 10 is prevented. Accordingly, the Al wire is not disconnected, characteristics are difficult to deteriorate due to the permeation of moisture, and damp-proofing and reliability are improved.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は金属ベースの上に絶縁板、端子板及び半導体チ
ップを順次ろう材を介して搭載しレジンでモールドした
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device in which an insulating plate, a terminal plate, and a semiconductor chip are successively mounted on a metal base via a brazing material and molded with resin.

〔発明の背景〕[Background of the invention]

従来この種の半導体装置は第２図に示す構成となってい
る（特開昭５７−７８１５７号公報）。即ち、第２図に
おいて、１は銅ペース、２はアルミナ板、３ａは銅端子
板、４はモリブデン等の熱応力緩飯板、５はシリコンチ
ップであシ、これら部材の間は半田で固着されている。Conventionally, this type of semiconductor device has a structure shown in FIG. 2 (Japanese Patent Application Laid-open No. 78157/1983). That is, in Fig. 2, 1 is a copper paste, 2 is an alumina plate, 3a is a copper terminal board, 4 is a thermal stress relief plate such as molybdenum, 5 is a silicon chip, and the spaces between these members are fixed with solder. has been done.

　　− シリコンチップ上側の電極面からは、Ａｔワイヤー６に
よって他端子板３ｂ、３ｃとの接続がなされる。- From the electrode surface on the upper side of the silicon chip, connections with other terminal boards 3b and 3c are made by At wires 6.

そして、パッケージ構成は、プラスチックのケース７を
銅ベースに接着してシリコンチップ５とＡｔワイヤー６
が完全に覆われるまでチップコーティング用樹脂８を注
入し、その上にモールド樹脂９を注入して蓋１０が装着
されている。The package configuration consists of a plastic case 7 bonded to a copper base, a silicon chip 5 and an At wire 6.
A chip coating resin 8 is injected until it is completely covered, a molding resin 9 is injected thereon, and a lid 10 is attached.

チップコーティング用樹脂８はシリコンチップ５及びＡ
ｔワイヤー６を機械的に保護することを目的として、ゴ
ム状又はゲル状等のソフトレジンが使用される。Chip coating resin 8 is silicon chip 5 and A
For the purpose of mechanically protecting the t-wire 6, a rubber-like or gel-like soft resin is used.

モールド樹脂９は主として端子板３ａ〜３ｃ。The molded resin 9 mainly covers the terminal plates 3a to 3c.

蓋１０等を固定するために使用されており、エポキシ等
のハードレジンが使用される。It is used to fix the lid 10 etc., and hard resin such as epoxy is used.

この種の半導体装置はプラスチックパッケージであるた
め、金属パッケージの半導体装置に比べると特に耐環境
性能が劣ることが問題となる。実際、耐湿性試験、プレ
ッシャー・タック試験等の寿命試験にて不良がおこりや
すい。この原因としては、銅ベース１とケース７の間隙
、端子板３ａ〜３Ｃとモールド樹脂９の間隙、ケース７
とモールド樹脂９の間隙等より半導体装置内に水分が浸
入して来て、チップコーティング用樹脂８の界面に達し
だとき、コーティング樹脂がゲル状の場合は親水性であ
るために、水分が更にコーティング樹脂８中にも浸透し
て、終にはＡｔワイヤー６、シリコンチップ５にまで到
達する。このためＡ４ワイヤー６の腐食、シリコンチッ
プ５表面の汚染が発生して特性劣化がおこる。Since this type of semiconductor device is a plastic package, a problem arises in that its environmental resistance is particularly poor compared to semiconductor devices in a metal package. In fact, defects are likely to occur in life tests such as moisture resistance tests and pressure/tuck tests. The causes of this include the gap between the copper base 1 and the case 7, the gap between the terminal boards 3a to 3C and the molded resin 9, and the gap between the case 7 and the terminal boards 3a to 3C.
When moisture enters the semiconductor device through the gap between the mold resin 9 and the chip coating resin 9 and reaches the interface of the chip coating resin 8, the coating resin is hydrophilic if it is in the form of a gel. It also penetrates into the coating resin 8 and eventually reaches the At wire 6 and silicon chip 5. This causes corrosion of the A4 wire 6 and contamination of the surface of the silicon chip 5, resulting in deterioration of characteristics.

一方チツブコーティング用樹脂８としてゴム状のものを
使用した場合は、疎水性であるためにチップコーティン
グ用樹脂８中への水分の浸透は防止できる。ところがゴ
ムの場合はゲルに比べて線膨張係数がけるかに大きいた
めに、通電によるシリコンチップ５の発熱等により半導
体装置に熱履歴が加わった場合にチップコーテイング用
樹脂８自体が、膨張、収縮を繰り返すために樹脂８中の
Ａｔワイヤー６に歪が加わることになる。このため、Ａ
ｔワイヤー６の切断やシリコンチップ表面でのワイヤは
がれ等が発生しやすく、信頼性上重大な問題となる。On the other hand, when a rubber-like material is used as the chip coating resin 8, water penetration into the chip coating resin 8 can be prevented since it is hydrophobic. However, in the case of rubber, the coefficient of linear expansion is much larger than that of gel, so when a thermal history is applied to the semiconductor device due to heat generation of the silicon chip 5 due to energization, the chip coating resin 8 itself expands or contracts. As this is repeated, strain is applied to the At wire 6 in the resin 8. For this reason, A
Breaking of the t-wire 6 and wire peeling on the silicon chip surface are likely to occur, which poses a serious problem in terms of reliability.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、耐湿性および信頼性に優れたモールド
構造の半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having a molded structure with excellent moisture resistance and reliability.

〔発明の概要〕[Summary of the invention]

上記目的を達成する本発明の特徴とするところは、チッ
プコートを線膨張係数が小さいチップコーティング用樹
脂と疎水性のチップコーティング用樹脂の二重構造にし
たことにある。A feature of the present invention that achieves the above object is that the chip coat has a dual structure of a chip coating resin with a small coefficient of linear expansion and a hydrophobic chip coating resin.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明の一実施例を示しておシ、第２図に示し
たものと同一物、相当物には同一符号を付けている。FIG. 1 shows an embodiment of the present invention, and the same or equivalent parts as shown in FIG. 2 are given the same reference numerals.

第１図の実施例で、第２図に示す従来例と異なっている
ところは、チップコーティング用樹脂の構造セ、線膨張
係数がアルミナ板２と同程度のチップコーティング用樹
脂１１をＡｔワイヤー６を含むシリコンチップ５上のみ
に設けてから、ゴム状のチップコーティング用樹脂１２
を設けている。The embodiment shown in FIG. 1 is different from the conventional example shown in FIG. The rubber-like chip coating resin 12 is applied only on the silicon chip 5 containing
has been established.

チップコーティング用樹脂１１はフェノール系樹脂で住
友ジュレッ社よシ商品名「ジュレンＲＰ−１６３８２Ｊ
として販売されている熱硬化性のものを一例として用い
た。この樹脂の線膨張係数は３　Ｘ　１０−’／ｌ：’
であシ、アルミナ板２のそれは７　Ｘ　１０−６／Ｃで
ある。またゴム状のチップコーティング用樹脂１２は従
来より用いられているもので、その線膨張係数は３１０
ｘｔＯ−’／ｃである。チップコーティング用樹脂１１
がＡｔワイヤー６のある部分を覆っており、その線膨張
係数は小さいため、Ａｔワイヤー６に熱応力は殆ど加わ
らず、疎水性のゴム状チップコーティング用樹脂１２も
設けられているため、端子板３８〜３ｃと蓋１０の隙間
等から浸透した水分はこの樹脂１２によってそれ以上の
浸透を阻止される。The chip coating resin 11 is a phenolic resin manufactured by Sumitomo Juret Co., Ltd. under the trade name "Jurene RP-16382J".
As an example, a thermosetting material sold as . The coefficient of linear expansion of this resin is 3 x 10-'/l:'
Yes, that of alumina plate 2 is 7 x 10-6/C. Furthermore, the rubber-like chip coating resin 12 has been used conventionally, and its coefficient of linear expansion is 310.
xtO-'/c. Chip coating resin 11
covers a certain part of the At wire 6, and its coefficient of linear expansion is small, so almost no thermal stress is applied to the At wire 6. Since the hydrophobic rubber-like chip coating resin 12 is also provided, the terminal board The resin 12 prevents moisture from penetrating further through the gaps between the lid 10 and the lid 10.

尚、緩衝板４がなく、シリコンチップ５が端子板３ａ上
比直接固定されるものや、Ａｔワイヤー以外の他のリー
ドで接続したものにも本発明は適用できる。The present invention can also be applied to a device in which the buffer plate 4 is not provided and the silicon chip 5 is directly fixed onto the terminal plate 3a, or a device in which the silicon chip 5 is connected with leads other than At wires.

更に、アルミナ板２の上に複数のシリコンチップ５が搭
載されたものでもよい。Furthermore, a plurality of silicon chips 5 may be mounted on the alumina plate 2.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、Ａｔワイヤーにほとんど熱応力が加わ
らず、断線を起す心配（はなく、また、水分の浸透によ
る特性劣化が起りづらく、従って、耐湿性、信頼性の優
れた半導体装置を得ることができる。According to the present invention, almost no thermal stress is applied to the At wire, there is no risk of wire breakage, and characteristic deterioration due to moisture penetration is less likely to occur, thus providing a semiconductor device with excellent moisture resistance and reliability. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す図、第２図は従来の半
導体装置を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional semiconductor device.

Claims (1)

【特許請求の範囲】[Claims] １、金属ベース上にろう材を介して順次絶縁板、複数の
端子板及び半導体チップを固着搭載し端子板と半導体チ
ップ間をリードで接続し、その周囲をチップコーティン
グ用樹脂およびモールド樹脂で覆つた半導体装置におい
て、チップコーティング用樹脂を上記絶縁板と線膨張係
数が近似した第一の樹脂と疎水性の第二の樹脂の二重構
造にしたことを特徴とする半導体装置。1. An insulating plate, multiple terminal boards, and semiconductor chips are fixedly mounted one after another on a metal base via a brazing material, the terminal boards and semiconductor chips are connected with leads, and the periphery is covered with chip coating resin and molding resin. 1. A semiconductor device characterized in that a chip coating resin has a double structure of a first resin having a linear expansion coefficient similar to that of the insulating plate and a hydrophobic second resin.
JP15305784A 1984-07-25 1984-07-25 Semiconductor device Pending JPS6132557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15305784A JPS6132557A (en) 1984-07-25 1984-07-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15305784A JPS6132557A (en) 1984-07-25 1984-07-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6132557A true JPS6132557A (en) 1986-02-15

Family

ID=15554035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15305784A Pending JPS6132557A (en) 1984-07-25 1984-07-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6132557A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009759A (en) * 2010-06-28 2012-01-12 Shindengen Electric Mfg Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009759A (en) * 2010-06-28 2012-01-12 Shindengen Electric Mfg Co Ltd Semiconductor device

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