JPS6132159A - Dma controller - Google Patents

Abstract

PURPOSE:To process automatically picture data without intervention of a central processor and with high general-purpose properties by providing a data processing means for storing data and processing it logically to a DMA controller itself. CONSTITUTION:In setting the operation mode to a data moving mode, the presence of duplication of areas is checked and if any duplication exists, the direction of duplication is discriminated and flags FX, FY are set. When, e.g., the flags FX, FY are both 0, the content of a register RSA is set to counters SS, SI and the content of a register RDA is set to counters DS, DI. When there is a request for DNA transfer, the content of a sender memory is read by the address information generated by the content of the counters SS and SI and it is latched by a logical operation unit ALU. Then the logical processing is applied to the content of the logical operation unit ALU, a destination address DS+DI is outputted to a data line and the content of the memory is rewritten by the result of operation.

Description

Detailed Description of the Invention ■Field of the Invention The present invention relates to a DMA system that performs data transfer processing at high speed instead of a central processing unit (CPU) in order to perform high-speed processing.
(direct memory access) control device.

■Conventional technology Central processing units such as microprocessors are highly versatile and can perform a variety of processes. However, this type of device executes processing by reading the contents of memory one byte or several bytes at a time and decoding the program, so its processing speed is slow. Especially when processing a large amount of data, the processing speed cannot be increased even though the processing involves repeating the same process over and over again. Therefore, DMA processing is employed to transfer data at high speed.

In DMA processing, the central processing unit is separated from the system bus, and instead of the central processing unit, the DMA control unit generates address information, read strobes, write strobes, etc. Or data is transferred between memories with different addresses.

However, conventional DMA control devices can only perform simple data transfers, so processing that involves data processing is difficult.
Even if the processing content is simple, DMA processing cannot be adopted.

For example, when performing image processing, it is often necessary to invert or move data in a specific two-dimensional area. Conventionally, this type of processing has had to be performed by the central processing unit itself, and the processing takes a long time.

When a central processing unit performs processing to invert data in a predetermined two-dimensional area, the memory address of each pixel is calculated sequentially using the processing start address and the X and Y coordinates of each pixel, and each time the address is obtained, the memory address is The data is read, inverted, stored at the same address again, and compared to see if it is the end position, repeating these processes until the end position is detected. Also, when moving data, simply transferring the data will destroy the data if it exists at the transfer destination, so read the data at the transfer source and perform a logical OR between it and the data at the transfer destination. Processing such as storing the result at the transfer destination is performed, and this process is repeated for all data. Conventional DMA controllers cannot be used for this type of processing.

■Purpose of the Invention The first object of the present invention is to provide a DMA control device that is highly versatile and can automatically process image data, etc. without the intervention of a central processing unit. The second purpose is to provide a DMA control device that can process with one instruction, and the third purpose is to prevent data destruction when the data area of the transfer source and the data area of the transfer destination overlap. shall be.

(2) Structure of the Invention In order to achieve the above object, in the present invention, the DMA control device itself is provided with data processing means capable of holding data and logically processing the data, thereby enabling data processing during transfer. Logical processing includes inversion, logical sum, logical product, exclusive logical sum, and erasure.

According to this, for example, when it is desired to invert data in a series of areas, it is only necessary to set the inversion mode and other necessary parameters in the DMA control device and output a DMA request.

When processing image data, processing is generally performed on a specific two-dimensional region. Although the addresses of the display memory are continuous, the two-dimensional area appearing on the display screen is a collection of one-dimensional areas with non-continuous addresses. In other words, in general, groups of pixels that are continuous on the X coordinate of the display surface correspond to memories located at addresses adjacent to each other, but
The addresses of groups of pixels that are continuous in terms of coordinates are separated from each other by a predetermined amount (memory address amount corresponding to one line of display). If the addresses are discontinuous in this way, it is necessary to calculate the address every time the Y coordinate is updated, so when using a conventional DMA control device, a central processing unit must be involved for each line of processing. The process is complicated and time-consuming. Therefore, in a preferred embodiment of the present invention, the DMA control device is provided with at least two counters that count the respective coordinate values of the two-dimensional coordinates, and the DMA control device automatically performs the counter operations according to the counted values of these counters. Calculate the address of the two-dimensional area. This eliminates the need for a central processing unit to handle two-dimensional data.

By the way, when data in a specific two-dimensional area is moved to another two-dimensional area, the data may be destroyed if there is overlap between those areas. For example, if the memory address increases toward the right side of the display coordinates, and the right side of the transfer source data area and the left side of the transfer destination data area overlap, data will be transferred in order from the smallest memory address. For example, the data transferred at the beginning is stored in the transfer source area, and later when the processing memory address reaches the overlapping area, the data transferred at the beginning will be transferred again, and the desired No transfer results are obtained.

In such a case, if the order of updating the data transfer addresses is reversed, data destruction during transfer will not occur. Therefore, in a preferred embodiment of the present invention, the DMA control device checks the parameters of the areas set therein to examine the overlap between the transfer areas, and if there is an overlap, performs processing according to the direction of the overlap. Determine the address update direction.

In other words, if there is overlap in the horizontal (X) direction and the transfer destination pixel is located to the right of the transfer source pixel, the address is updated so that processing is performed from the right side of the pixel to the left side,
In the opposite case, the address is updated from the left side of the pixel to the right side, and if there is vertical overlap and the destination pixel is located below the transfer source pixel, the address is updated from the bottom of the pixel. Addresses are updated so as to process toward the top, and vice versa, addresses are updated from the top of the pixel to the bottom.

Failed five Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a DMA control device used in a display information processing device to be described later. Briefly speaking, this DMA control device differs from a normal DMA control device in that it transfers data in a two-dimensional area and can process data during data transfer.

This will be explained with reference to FIG. This DMA control device has
8 data lines, 2
0 address lines, several DMA request signal lines D
REQ (DMA request), several DMA response signals DA CK (DMA acknowledge), hold request signal line HRQ (hold request) to the central processing unit, hold confirmation signal line HLDA (hold acknowledge) from the central processing unit. ), reset signal line RESET.

Clock signal line CLK, processing end signal line EOP
(end of process) and other signal lines are provided.

When this DMA control device is actually incorporated into a system, each of the above signal lines is connected to a path line of the system.

When setting the operation mode, control parameters, etc. to this DMA control device, the DMA control device uses the input/output buffer BF.
2, various information is taken in from the data line.

In that case, the command control circuit CMC determines what the data means based on the information input to the address line at that time.

Command data specifying the operating mode etc. is held in the command register ROM. In this example, the operation modes of the DMA control device include data movement mode/data fixation mode, calculation mode/non-calculation mode, etc. Data movement mode is a mode in which data input from a first address area is moved (transferred) to a second address area, and data fixation mode is a mode in which data input from a first address area is transferred to a second address area. This is a mode in which data is transferred to address area 1 (address remains unchanged). In data movement mode, the data input from the first address and the
It is possible to perform an operation on the data input from the address of and output the result. The calculation mode is a mode in which preset calculation processing is performed on input data and the result is output to the transfer destination.

In the calculation mode, specify what kind of calculation to perform. In this example, the operation modes include bit-by-bit inversion, logical sum of first data and second data, logical product of first data and second data, and logical sum of first data and second data.
Exclusive OR with data, erasure (writing zero), double rotation (bit shift), etc. are provided.

When actually transferring data, various parameters are set in addition to the operation mode. In this example, the parameters include the transfer source start address, the transfer destination start address, the length of the X coordinate (the number of bytes), the length of the Y coordinate (the number of lines) (in the case of rotation, an integral multiple of 8), and the output device (display There are five memory amounts (number of bytes) per line determined by the configuration of the device. These parameters are
Transfer source start address register R3A, transfer destination start address register RDA, byte number setting value register RXB, line number setting value register RYL, respectively.
and is stored in the line byte setting value register RXH.

Address information for data transfer is output from four counters SS, SI, DS and DI. Counters SI and DI are 16-bit counters,
S and DS are 4-bit counters. One address information (20 bits) is generated by one index address counter SI or DI and one segment address counter SS or DS. The index address counters Sl and DI are incremented or decremented each time a transfer is performed, and when they overflow or underflow and a carry is output,
Segment address counter SS or DS is incremented or decremented.

The X counter CNX and the Y counter CNY count the number of times the X and Y coordinates of the two-dimensional area to be transferred are updated, respectively.

The processing timing of the entire DMA control device is controlled by a timing and control circuit TMC.

Next, an outline of the processing operation of the DMA control device shown in FIG. 1 will be explained with reference to FIGS. 2a, 2b, and 2c.

First, set the operating mode, commands, various parameters, etc. Here, when the data movement mode, that is, the mode in which data is transferred between mutually different addresses, is set, the presence or absence of area overlap is then checked.

In other words, the address order for data transfer is generally /J
% You may update from a small address to a large address or vice versa, but if there is an overlap between the transfer source memory area and the transfer destination memory area, Depending on the update direction, a memory area may be set as the transfer source after being set as the transfer destination. In that case, the contents of the data that have been updated will be transferred again, so the memory area to which the data was transferred will be The content becomes abnormal. 'Therefore, if there is an overlap between the transfer memory areas, the direction of the overlap is determined and flags FX and FY are set according to the result. If the destination address is larger than the source address in the first dimension (X-axis direction),
That is, if the transfer destination area exists on the right side of the transfer source area on the display screen, the flag FX is set to II 111, and if not, the flag FX is set to II OII. Also, if the destination address is larger than the source address in the second dimension (Y-axis direction), that is,
If the destination area exists below the source area on the display screen, the flag FY is set to HI II; otherwise, the flag FY is set to II O11. Note that if there is no overlap in the areas, flags FX and FY are both set to 11.011.

If flags FX and FY are both II O7+, the contents of the transfer source start address register R8A are preset to the transfer source segment address counter SS and transfer source index address counter SI, and the contents of the transfer source start address register R8A are preset to the transfer destination segment address counter DS and transfer destination index address counter SI. The contents of the transfer destination start address register RDA (the coordinates of the upper left end of the area on the display screen) are preset in DI. Similarly, flag FX is II 1 # and FY is rr O
In the case of n, the contents of the transfer source start address register R5A are set to the byte number setting value register RXB in SS0SI.
Preset the result of adding the contents of and set it to DS + DI.
The result of adding the contents of the byte number setting value register RXB to the contents of the transfer destination start address register RDA (on the display screen, the upper right coordinates of the area) is preset. Flag FX
is “0” and FY is II I 11, SS+S
Preset the result of multiplying I by the contents of the line byte setting value register RXM and the contents of the line number setting value register RYL and adding the contents of the transfer source start address register R8A (lower left coordinate of the area on the display screen). death,
The result of multiplying the contents of the line byte setting value register RXM by the contents of the line number setting value register RYL and adding the contents of the transfer destination start address register RDA is preset to pS+DI. Otherwise, if flags FX and FY are both II I H, SS+SI
The result of multiplying the contents of line byte setting value register RXM by the contents of line number setting value register RYL, adding the contents of byte number setting value register RXB, and the contents of transfer source start address register R3A is preset. , DS0DI is multiplied by the contents of the line byte setting value register RXM and the contents of the line number setting value register RYL, and the contents of the byte number setting value register RXB and the contents of the transfer destination start address register RDA are added. Preset results.

A request for DMA transfer (e.g. from the central processing unit CPU)
If so, proceed to the next process. However, if the channel is masked in advance, only that request is stored.

If the mask is released, the DMA acknowledge signal D
It outputs ACK to the device that requested the transfer, and then outputs a hold request signal HRQ to the central processing unit. When the central processing unit receives the hold request HRQ, the central processing unit releases the system bus after finishing the process currently being executed.
A hold acknowledge signal HLDA is output to the DMA control device. After this, the DMA control device controls the system bus to perform predetermined data transfer.

First, counter CNX is set to byte number setting value register RXB.
The contents of the line number setting value register RYL are preset to the counter CNY.

Address information generated from the contents of the transfer source segment address counter SS and transfer source index address counter SI is output to the address line of the system bus via the multiplexer & output buffer BFI, and at the same time a memory read strobe signal (not shown) is output to the address line of the system bus. ) and output
Read the contents of the transfer source memory. Here, the data appearing on the data line is taken into the DMA control unit via the input/output buffer BF2, and is sent to the logic operation unit ALU.
Latch with.

When there is one address, that is, the transfer source address and the transfer destination address are the same, and the operation mode is set, the data latched in the logical operation unit ALU is transferred to the ALU according to the type of operation mode. The calculation is performed internally, and the result is also held in the ALU.

Then, the contents of the transfer source counter SS+SI are outputted to the address line, the data held in the logical operation unit ALU is outputted to the data line, and a memory write strobe signal (not shown) is outputted to rewrite the contents of the memory.

Operation modes when the data transfer source address and data transfer destination address are different are divided into two groups.

One is a mode in which the contents of the logical operation unit ALU are inverted, erased, and logically operated with a predetermined value y.The other is a mode in which the contents of the logical operation unit ALU and the transfer destination address (DS+I ) I) is a mode in which logical operations are performed on the data stored in I). In either mode, the results are stored in the logic unit ALU. Then, it outputs the transfer destination address (DS+DI) to the address line, outputs the contents of the logic operation unit ALU to the data line, outputs a data write strobe signal to the system bus, and rewrites the contents of the memory with the operation result.

When one transfer process is completed, the contents of the counter CNX are first decremented. As a result, if the contents of the counter CNX are 0 or more, the contents of the counters SS, SI, DS, and DI are updated according to the state of the flag FX. If the flag FX is II O+7, the index address counters SI and DI are incremented, and the FX is II 1.
If it is 71, decrement them. If index address counters SI and DI overflow (or underflow) at that time, the values of segment address counters SS and DS are updated (incremented or decremented), respectively.

If the result of decrementing counter CNX is negative,
The contents of the byte number setting value register RXB are reset to the counter CNX, the counter CNY is decremented, and the address counter SS and
Reset the contents of SI, DS and DI. Flag FX
and FY are both 0'', the contents of line byte setting value register RXM are added to counter SS+SI, the contents of byte number setting value register RXB are subtracted, and counter D
The contents of RXM are also added to S1DI, and the contents of RXB are subtracted. Similarly, flag FX is '1'' and FY is 710
In case of II, register RXB is added to counter SS+SI.
The contents of the register RXM are added to the contents of the register RXM, and the counter DS
The contents of RXB and RXM are also added to +DI. When flag FX is ``exhausted 0'' and FY is 1'', the contents of register RXB and register RXM are subtracted from the contents of counter SS-SI, and the contents of register RXB and register RXM are subtracted from the contents of counter DS+DI. Subtract the contents of. Other than that, both flags FX and FY are “1”
Then, add the contents of register RXB to counter SS + S I, subtract the contents of register RXM, and set counter D.
Add the contents of register RXB to S+DI and register RX
Subtract the contents of M.

In other words, in a normal display device where the memory address increases from left to right and from top to bottom on the two-dimensional display surface, the direction in which the address is updated is the flag FX.
and FY are both jl OII, the direction is from left to right and from top to bottom on the display screen, and the flag FX
If ## I II and FY is II OII, the direction is from right to left and top to bottom on the display screen, and when flag FX is "0" and FY is 1, the direction is on the display surface. The direction is from left to right and from bottom to top, and the flag FX
and FY are both sr 1 u, the direction is from right to left and from bottom to top on the display screen.

If the result of decrementing the counter CNX becomes negative and the result of decrementing the counter CNY becomes negative, it means that data transfer for all areas has been completed.
The hold request signal HRQ is released, the system bus is released for the central processing unit, and the initial state is returned.

FIG. 3 shows a - format display information processing device.

This will be explained with reference to FIG. This display information processing device is equipped with the DMA control device shown in FIG. 1 as a direct memory access unit DMAP. The system bus of this device includes, in addition to the microprocessor MPU and direct memory access unit DMAP, an address decoder ADD, a main memory RAM1, a read-only memory ROM1. I10 port OP, bitmap memory RAM 2, character memory RAM
3. External memory interface IFI, scanner interface IF2. If the keyboard unit, display signal synthesis unit DSPU, etc. are connected, the display signal synthesis unit DSPU is connected to the cathode ray tube display unit CRTU.
A signal for displaying a predetermined image is generated. This signal is generated by the logical sum of the data corresponding to each pixel written in the bitmap memory RAM2 and the pixel data corresponding to the character code written in the character memory RAM3. In this example, pixel data of a large number of character patterns are written in advance in the character generator ROM2, and when the character memory RAM3 outputs predetermined character code data, the corresponding character pattern data is output to the display signal synthesis unit DSPU. . In addition,
The CRT display unit CRTU is a color display.

A floppy disk unit FDU and a laser disk unit RDU are connected to the external memory interface IFI, and an image scanner IMS is connected to the scanner interface IF2.

FIG. 4 shows the configuration of the bitmap memory RAM2 of FIG. 3. Please refer to FIG. This memory RAM2 has four banks of read/write memory of 512 bytes each. The system bus connected to the microprocessor MPU is configured so that one of four banks can be connected. However, the display signal synthesis unit DSPU has 4
You can access two banks at the same time.

Memory address of bitmap memory RAM2 and CRT
The correspondence relationship with the information displayed on the display unit CRTU will be explained with reference to FIGS. 9 and 10. In this example, each data bit in the bitmap memory is divided into 2048
2048 two-dimensional coordinates are assigned to each pixel, of which an area of 1024 x 768 can be displayed at one time on the display surface of the CRT display unit CRTU. Each bit of 1 byte of data corresponds to 8 consecutive pixels in the horizontal direction, and a group of pixels in one horizontal line is:
It corresponds to 256 bytes of memory with consecutive addresses.

Note that an area of several pixels in the horizontal direction (ΔX) and several pixels in the vertical direction (Δy) among the two-dimensional coordinates of 2048 x 2048 is allocated as a non-display area for scrolling, which will be described later.

Pixel data at each coordinate is composed of 4-bit data obtained from each memory bank.

The color of the pixel displayed on the CRT display unit CRTU is determined according to the configuration of this 4-bit data. In this embodiment, the complementary relationship of 4-bit data and the complementary color relationship of display colors match. In other words, when predetermined 4-bit data is being displayed and the data is rewritten into a complemented version, the complementary color of the previously displayed color will be displayed.

FIG. 5 schematically shows the operation of the microprocessor MPU in FIG. 3 during data editing. When processing starts, initial settings are made and a key human power check is performed. When there is an input from the keyboard unit KEY, the type is determined and processing proceeds accordingly. In this example, there are specifically 11 types of commands. The function of each command is as follows.

KO: To call up image data that has been stored in advance on the disk 1: To save data on the memory (RAM2, RAM3) to the disk 2: Setting the amount of movement of the cursor, etc. when operating the cursor keys, flag F2 Set.

K3: Instructions to move the cursor, select a 4-niblock cursor (window) to move up, down, left or right, select one of the three and set flag F4 accordingly to display a 5-niblock cursor /Erase 6: Display data and/or block cursor status setting instruction, select processing according to the status of flags F7 and F8 7: Specify window size setting mode, set flag F7 8: Window movement mode Specify, set flag F8 to 9:
Display data editing instructions Two-character input process other than the above Next, we will discuss the features of the device shown in FIG. 3, which are shown as subroutines in FIG. "Edit" will be explained in detail. An outline of these processes is given in Section 6a.
It is shown in FIGS.

When 5 is specified in the command, flag F5 is checked. Flag F5 is set to HIH when the block cursor or window is displayed, and is set to PI O#l otherwise.

In this specification, symbols enclosed in parentheses (such as flags, registers, etc.), such as F5 (F4) shown in Fig. 6c, are used to indicate that there are multiple symbols and are selected by the parameters in parentheses. In other words, in command 5, processing is performed on the window previously selected in command 4.

If the flag F5 is IIO'1, the "window display set" subroutine is executed, and if it is '1'', the "window display clear" subroutine is executed, and in either case, the state of the flag F5 is reversed after processing.

In the "window display set" subroutine, flag F5 is checked, and if it is 0, memory bank l.

2. Execute the "display reversal processing" subroutine and the "window identification mark display" subroutine for each of steps 3 and 4. In "display inversion processing", data fixing mode and logical inversion operation mode are set for direct memory access unit DMAP, and registers R8A and R'
XB, RYL and RX M 4: each register BC
Set the values of A, BCX, BCY and fixed value XM and press D.
Generates an MA request and waits for the DMA transfer to complete.

Registers BCA, BCX, and BCY contain the start address of the window (top left coordinates), the horizontal length of the window,
and the vertical length of the window (the number of lines) are stored. Therefore, when the "display inversion process" is executed, data obtained by inverting the original data bit by bit is written into each memory in the two-dimensional memory area corresponding to the window area. In other words, in the case of the simplest black/white display, the two-dimensional area set in the window is rewritten with display content that is the black and white inversion of the previous display content.

FIG. 7 shows an example of a state in which the window is displayed. In Figure 7, BCI, BO2 and BO3 are windows, and PI, P2
and P3 are arbitrary display pattern data. Referring to Figure 7, although there are no lines drawn in the window area, it is clear that the window area and other areas can be distinguished. The area and other areas can be reliably identified without a single pixel error.

"Window identification mark display" is a process of displaying the distinction between each window within the window when a plurality of windows are displayed. Specifically, one horizontal line is displayed in the first window, two horizontal lines are displayed in the second window, and three horizontal lines are displayed in the third window.

Note that these horizontal lines are displayed by inverting the data before displaying them, as in the case of windows. See Figure 6e.

If flag F4 is 2 or more (selects the third window), B C
Write data obtained by inverting the contents bit by bit into a 5-byte memory whose starting address is A 10N x + (N3yX X M). If flag F4 is 1 or more (selecting the second window or third window), further BC
5 with A+Nx+ (N2yXXM) as the starting address
Write those inverted data to the byte memory, and if flag F4 is 0 or more (select the first window, second window, or third window), further write BCA+Nx+ (NlyX
The inverted data is written to a 5-byte memory whose starting address is XM).

That is, for example, when the third window BC3 is selected, as shown in FIG. 8, three lines (marks) Ml, N2
and N3 are displayed in the upper left corner of the window.

If it is the second window, lines M2 and Ml are displayed, and if it is the first window, only line M1 is displayed.

In the “window display clear” subroutine, flag F5 is set to ’1.
'', set it to 7+0 II, select each memory bank 1, 2, 3, and 4, and execute ``window identification mark display'' and ``display inversion processing'', respectively.

In other words, the process is the opposite of the above-mentioned "window display set" subroutine. Therefore, when the "window display set" subroutine is executed, the selected window is displayed with its mark,
Executing the "window display clear" subroutine clears the selected window.

When 6 is specified in the command, "display processing" is executed. Flag F by 7 on the command before this is indicated.
If 7 is set to a value other than 0, the display window is enlarged or reduced. In addition, when displaying the window for the first time,
A window is displayed with a predetermined initial size. Flag F
If 7 is 111 N1, move (update) the coordinates of the bottom edge of the window lower than the current one, and if flag F7 is 2'', move the coordinates of the bottom edge of the window higher than the current one. , flag F
When flag F7 is #3 It, the coordinates of the right end of the window are moved to the right from the current position, and when flag F7 is Pl 4 II, the coordinates of the left end of the window are moved to the left from the current position. The movement amount N is 1 if the flag F2 is "0". F2 is II 1 P
If it is l, set it to 10. When performing this process,
First, the "window display clear" subroutine is executed to erase the displayed window, the value of the window parameter BCY or BCX is updated, and then the "window display set" subroutine is executed again.

If the flag F8 is set to a value other than 0 by the command 8 before the command 6 is specified, the following operation occurs depending on the contents of the flag F8. If the flag F8 is 1, a "window movement" subroutine is executed, and only the currently displayed window (the entire window) is moved on the screen. If the flag F8 is 2, a "window/data movement" subroutine is executed, and the window being displayed and the display data located in the window area are moved to the designated position. Also, if flag F8 is 3, "data movement"
Execute the subroutine and move (scroll) only the displayed data.

In the "window movement" subroutine, first the flag F5 is checked, and if it is IIIII, the next movement process is performed. In the movement process, execute the "window display clear" subroutine to erase the displayed window, update the parameter BCA (start address) of that window, and then execute the "window display set" subroutine to display the window again. do.

In other words, the data displayed on the screen of the CRT display unit CRTU remains unchanged, and only the position of the window moves in accordance with the designated direction. Depending on whether the direction of movement is up, down, left or right, the window parameter BCA is updated as follows.

If the moving direction is upward, the result of multiplying the number of bytes of one line XM by a predetermined number N is subtracted from the contents of register BCA. Similarly, if the moving direction is down, the result of multiplying XM by a predetermined value N is added to the contents of the register BCA, and if the moving direction is left, the value of the predetermined value N is subtracted from the contents of the register BCA,
If the moving direction is right, a predetermined value N is added to the contents of register BCA.

The predetermined value N is an arbitrary value or a value of 1 or 10 depending on the flag F2.

In the "window/data movement" subroutine, flag F5 is first checked and if it is Pl I N, the process proceeds to the next step. If the moving direction is upward, a value obtained by multiplying the number of bytes of one line XM by a predetermined value N is subtracted from the contents of register BCA, and the value is stored in register BCD. Register B
The CD is for storing the start address of the data transfer destination of each window. Similarly, if the direction of movement is down, then
The value obtained by multiplying M by N is added to the contents of register BCA and stored in register BCD. If the movement direction is left, the value obtained by subtracting N from the contents of register BCA is stored in register BCD, and the value obtained by subtracting N from the contents of register BCA is stored in register BCD. If it is right, add N to the contents of register BCA.
The added value is stored in register BCD. And rD
Execute the "MA data movement" subroutine.

In the ``rDMA data movement'' subroutine, the DMA
After setting the control device as follows, issue a DMA request and wait for the DMA transfer to finish. The operation mode is set to data movement mode and OR operation mode. and registers R5A and RDA.

Register BC in RXB, RYL and RXM, respectively.
Set the values of A, BCD, BCX, BCY and predetermined value XM.

When the DMA issues a request with these settings, the DMA
The control device first reads the transfer source data and latches it, then reads the transfer destination data, performs a logical OR operation between it and the latched data, and then uses the result as the transfer destination address. The process of storing in memory is performed for the entire two-dimensional area of the window. That is, in the two-dimensional area to which the window is moved, the data before the movement and the data that was at the window position before the movement are displayed.

When "rDMA data movement" is completed, set the contents of register BCD to register BCA, and then "set window display".
Execute a subroutine. As a result, the window will be displayed again at the same location (transfer destination) as the moved data.

In the "data movement" subroutine, flag F5
The contents of (+, 2.3) are saved in a predetermined memory before proceeding to the next process. Execute the "window display clear" subroutine for each window that is currently displayed to erase the window. Next, the direction of data movement (scrolling) is checked, and the contents of registers R8A and RDA are set as follows according to the result.

Upward scroll RS A: Am1n RD'A: A+oin+[(YM-N)XXM]
Downward scroll R8A: Am1n+((YM-N)XXM)RD
A: Am1n+(YMXXM) Scroll leftward RS A: Am1n RDA: Am1n+ (XM+N) Scroll rightward R8A: All1in+(XM-N) RD A:
A+min+ X MHowever, All1in S R
Minimum address YM of A M 2: Maximum value of Y coordinate of display memory N: Transfer distance (ΔX or Δy in FIG. 9) Furthermore, each register RXB, RYL and RXM has a predetermined value XM,
YM and XM are set, the operation mode of the DMA controller is set to data movement mode and non-operation mode, and a DMA request is issued.

When DMA transfer is performed as a result, the data in the bitmap memory RAM2 moves up, down, left, or right by N on the two-dimensional coordinates shown in FIG. The data displayed on the screen is updated (scrolled).

Next, load the saved data into flag F5 (1, 2, 3), and if each is set to window display, execute the "window display set" subroutine and restart the window. indicate.

Next, "display data editing" will be explained.

In this process, an editing mode is first specified, and processing is performed according to the result. In this example, [Edit Reverse Processing], [
``edit deletion process'', ``edit extraction process'', ``edit move process'', and ``edit exchange process'' can be executed.

In the "edit reversal process", the display data of that portion of the two-dimensional area where the window is displayed is inverted bit by bit. In this example, the "window display clear" subroutine is executed, the "display inversion process" subroutine is executed for each of memory banks 1, 2, 3, and 4, and the "window display set" subroutine is executed to perform this processing. ing.

In the "edit/delete process", the display data of that part of the two-dimensional area where the window is displayed is deleted. First, execute the "window display clear" subroutine to erase the window, then execute "r display erase processing" for each of memory banks 1, 2, 3, and 4 to clear the memory contents, and then select "window display set". Execute the subroutine and redisplay the window.

In "display erasure processing", data fixing mode and erasure operation processing mode are set as the operation modes of the DMA control device, and registers BC, A, BOX, BCY and a predetermined value XM are set in registers R8A, RXB, RYL and RXM, respectively. Set the value and issue a DMA request. If a DMA transfer is performed in this state, registers BCA, BCX and B
All 0s are written into the memory of the two-dimensional area specified by CY, that is, the area where the window was displayed.

In the "edit extraction process", display data corresponding to the area where the window is displayed is stored in the laser disk unit RDU. First, wait for the file name to be entered, then
Once it is entered, execute the "window display clear" subroutine to clear the window and laser the display data at the address corresponding to the window area in memory banks 1, 2.3 and 4 along with the entered file name. Disk unit RD
Store in U. When data storage is completed, the window is displayed again by executing the ``r window display set'' subroutine.

In the "edit movement process", a process is performed to move the data located in the currently selected window position to the position of another window. First, wait for the destination window to be specified.

The destination window is stored in flag F4b. To use the subroutine, exchange the contents of flag F4 and F4b, execute the "window display clear" subroutine,
Delete the destination window. Next, in order to match the sizes of the source window and destination window, register B OX (F
Store the contents of 4b) in the register box (F4),
Save the contents of register B CY (F4b) to register B C
Y (F4) and executes the "window display set" subroutine. When you do this, the size of the window you specified as the data destination will match the size of the source window.

At this point, you can change the position of the selected window, that is, the window to which you want to move. When a movement start instruction is given, a ``window display clear'' subroutine is executed, the contents of the flag F4 and the flag F4b are exchanged and returned to their original values, and the ``window display clear'' subroutine is executed again. This erases both windows. Next, DMA
Set the control device as follows. As the operation mode, a data movement mode and an OR operation mode are set. And each register R8A, RDA, RXB, RY
Register BCA (F4) for L and RXM, respectively.
BCA (F4b), BCX (F4), BCY (F4),
and set the value of the predetermined value XM.

In this state, each of memory banks 1, 2, 3, and 4 is selected and a DMA request is issued for each. When this is done, the display data at the source window position overlaps the data at the destination window position (logical OR). When the data movement is completed, the "window display set" subroutine is executed for each of the transfer source window and the transfer destination window to display the windows again.

In the "edit exchange process", the display data at the currently displayed (selected) window position and the display data at the other window position are exchanged. First, wait for the second window to be specified. As in the previous case, the contents of flag F4 and F4
b, execute the "window display clear" subroutine to erase the second window, adjust the size parameters (BOX, BCY) of the second window to the values of the first window, and execute " The window display set subroutine is executed to display the second window again.

Waits for an instruction to start the data exchange process, and when that instruction is received,
Erase the two windows. Then, the display data of the first window area is saved to a predetermined area of the main memory RAM1, and "display erasure processing" is executed for each of memory banks 1, 2, 3, and 4 of the bitmap memory RAM2, and the display data of the first window area is saved. Clear the display data in the window area. Then DM as follows
Set the A control device and execute "rI) MA transfer".

The operation mode is data movement mode and non-operation mode, and each register R8A, RDA, RXB, RYL and R
Registers B CA (F4b) and BC in XM, respectively.
Set the values of A (F4), BOX (F4), BCY (F4) and predetermined value XM. When DMA transfer is performed in this state, the same data as the display data in the second window area is stored (displayed) in the first window area as the movement destination.

Next, flags F4 and F4b are exchanged again, and "display erasure processing" is performed for each of memory banks 1, 2, 3, and 4.
is executed to erase the display data in the second window area. Furthermore, the DMA control device is set as follows to perform rDMA transfer. The operation mode is data movement mode and non-operation mode, and registers R8A, RDA, RXB, RYL
and RXM, display data save address (first
RAMI address where window data was saved), registers BCA (F4), BCX (F4), BCY (F4),
and set the value of the predetermined value XM. When a DMA request is issued in this state, the display data of the first window area saved in the main memory RAM1 is transferred to the second window area. Then, the "window display set" subroutine is executed for the first window and the second window, and the two windows are redisplayed.

■Effects As described above, according to the present invention, processing can be added to data transferred during DMA transfer, so DM
A can be used to process data at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a DMA control device. Figures 2a, 2b and 2c represent the D shown in Figure 1.
3 is a flowchart showing a schematic operation of the MA control device. FIG. 3 is a block diagram showing a -type display information processing device using the DMA control device shown in FIG. FIG. 4 is a block diagram schematically showing the bitmap memory RAM2 of FIG. 3. FIG. 5 is a flowchart showing the general operation of the microprocessor MPU shown in FIG. Figure 6a, Figure 6b, Figure 6C, Figure 6d, Figure 6e,
Figure 6f, Figure 6g, Figure 6h, Figure 61, Figure 6j,
6th figure, figure 612, figure 6m. 6n and 60 are flowcharts showing details of the process shown in FIG. 5. FIG. 7 is a front view showing an example of the display surface of the CRT display unit CRTU shown in FIG. 3, and FIG. 8 is a front view showing a part of FIG. 7 in an enlarged manner. 9 and 10 are plan views showing the correspondence between two-dimensional coordinates of display pixel data and memory addresses. 55, SI, DS, DI: Counter (address information generation means) BF2: Input/output buffer (data input/output means) ALU: Logical operation unit (data processing means) TM
C: Timing and control circuit (electronic control means) BC:1. BC2, BC3 block cursor (window) M
, P2. P3: Display pattern C8R: Cursor No. 6c A No. 6d Roto 6e (branch) Kushin identification mark table E〉 Skull 6 and Zuji 7 Aku 8 Zotaku 9 fig.
Spontaneous) September 72゜1, 1981, Indication of the incident 1982 Patent Application No. 1523262
, Title of the invention DMA control device 3, Relationship to the case of the person making the amendment Patent applicant address 1-3-6 Nakamagome, Ota-ku, Tokyo Name
(674) Ricoh Co., Ltd. Representative Hama 1)
Hiro 4, Agent 103 Te1.03864-605
2 Address: 2-27-6 Higashi Nihonbashi, Chuo-ku, Tokyo
No. 6, Contents of amendment (a) The following pages and lines of Kiryu's detailed explanation of the invention in the specification, (b) Figures 2a, 2b, 2C, and 3 of the drawings are attached as separate sheets. Correct as follows. 7. List of attached documents

Claims (8)

[Claims] (1) At least one address information generation means; data input/output means for outputting data to a predetermined signal line and inputting data from the signal line; data storage for holding data inputted via the data input/output means; and a logical calculation means for performing predetermined processing on the data stored in the data storage means; and data input/output means for instructing the address information generation means to output predetermined address information. inputting data obtained from the data processing means to the data processing means, instructing the address information generation means to output predetermined address information, and transmitting the data stored in the data processing means to a predetermined signal via the data input/output means. A DMA control device comprising: electronic control means for outputting data to a line and repeating these operations while updating an address until a predetermined condition is satisfied. (2) The electronic control means includes a first counter and a second counter, and counts up or down the first counter every time one process is performed, and when the first counter performs a predetermined count, the 2 counters are counted up or down, and the value of the address to be output by the address information generation means is determined according to the count value of the first counter and the count value of the second counter. DMA control device according to paragraph (1). (3) The address information generation means includes a first address information generation means and a second address information generation means, and in the first operation mode, the electronic control means generates an address generated by the first address information generation means. The result of calculating the data obtained by the address generated by the second address information generating means and the data obtained by the generated address of the second address information generating means is output together with predetermined address information, and in the second operation mode, the first address information generating means The data obtained by the address generated by the second address information generation means is output together with the address generated by the second address information generation means, and in the third operation mode, the data obtained by the address generated by the first address information generation means is processed. The DMA control device according to claim 1, wherein the DMA control device outputs the generated address together with the address generated by the first address information generation means. (4) If the address of the transfer source data area and the address of the transfer destination data area overlap, the electronic control means:
The DMA control device according to claim 1, which determines the direction of the overlap and selects the update direction of the address generated by the address information generating means in accordance with the result. (5) The electronic control means is configured to control the data transfer source address, the data transfer destination address, the size of the first dimension of the data transfer area, the size of the second dimension of the data transfer area, and the output device. The DMA control device according to claim 1, wherein the address information generating means is instructed to generate an address using a one-dimensional maximum value as a parameter. (6) The DMA control device according to claim (1), wherein the logical operation means has an operation mode for generating at least a complement of the data to be processed. (7) The logical operation means is provided with a plurality of operation modes, and calculates the data to be processed in the operation mode selected according to the operation mode preset in the electronic control means. DMA control device. (8) The address information generation means includes a first counter and a second counter, and the electronic control means counts up or down the first counter every time data is transferred, and the first counter overflows or underflows. Claims (1), (2), (3), (4), and (5), in which the second counter is counted up or down each time DMA control device according to item (6) or item (7).