JPH07182157A - Digital signal processor - Google Patents

Abstract

PURPOSE:To fast transfer data to a module by performing the input/output control of data for each block and at a direct memory transfer control part between an external data memory connecting part and an internal, data memory via a direct memory transfer bus. CONSTITUTION:The input data signals are inputted through plural data input buses 104 and stored in the internal data memories 107 and 108. Then the stored data signals are processed at an arithmetic part 106 and an address generating part 103. Meanwhile an external data memory 105 is connected to a read/write port of an external data memory connecting part 111. Furthermore the memory 105 is connected to a direct memory transfer bus 110 via a direct memory transfer control part 109 which performs the input/output control of data for each block between the part 111 and both memories 107 and 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor which mainly executes arithmetic processing on signal sequences.

[0002]

2. Description of the Related Art FIG.
1) A conventional digital signal processor DSSP1 (Digital Speech Si)
FIG. 1 is a block diagram showing a configuration of a general processor 1), in which 1 is a program counter PC having a stack for controlling an instruction address, 2 is an instruction mask ROM storing microinstructions, and 3 is the instruction mask ROM 2 or an external unit. The instruction registers IR0 and 4 for inputting one word of the micro instruction input from the instruction register IR0, 4 input only the bit field in the micro instruction input to the instruction register IR0 3 which needs decoding. Reference numeral 5 is an instruction decoder for decoding the microinstruction input to the instruction register IR14, 6 is a program bus P-Bus for distributing the microinstruction to each functional unit, and 7 is this program bus P-. Output from us6 enter the immediate in the microinstruction (18 bits wide), the data bus D
-Register BI for outputting to Bus8, 8 is a data bus D-Bus having an 18-bit width used for internal transfer of data associated with operation, and 9 is a register A for inputting an address mode instruction of the data memory from program bus P-Bus6.
M and 10 are registers AD having a width of 4 × 16 bits for holding address pointer information used for indirect address generation,
Reference numeral 11 is a 3-bit width page register PR for designating a page of the external data memory, 12 is a 9-bit width address calculator AAU capable of simultaneously generating a maximum of three addresses,
13 is an address register AR0, 14 is an address register AR1, 15 is an address register AR2, 16 is an address selector RAS, 17 is a loop counter LC, 1
8 is a status register SR for displaying the operation mode and state of the processor, 19 is a serial I / O port S
A DMA control unit that directly transfers data between I0 / 1, SO0 / 1 32 and an external data memory, 20 is an address register AR that holds a 12-bit wide address to be output to the external data memory, and 21 is 512w × 18. Dual port internal data memory 2P-RA with bit capacity and capable of reading and writing two data at the same time
M and 22 are registers DP for holding the input data to be operated
0 and 23 are registers DP1 for holding operation input data,
24 is a multiplier FMPL for performing floating point multiplication in 12E6 bit format, 25 is a register P for holding the result of the multiplier FMPL24, 26 is a selector, 27 is a selector, and 28 is mainly 12E6 bit format floating point operation Floating point arithmetic logic unit FAL
U and 29 are the floating point arithmetic logic unit FALU28
The 4w × 18-bit accumulators ACC0 to ACC3, 30 for holding the output of the memory and used for accumulation and the like are data registers DR connected to the data bus D-Bus8 for the purpose of temporarily holding the read / write data for the external data memory. , 31 is a read / write control circuit R / W Cont of an external data memory, 32 is a serial I / O port SI0 / 1, SO0 / 1 for executing serial / double-channel serial data transfer with an external device,
33 is an interrupt control circuit Int. Cont. , 34 are external data memory bus control circuits BusCont. , 35 are clock control circuits CLKCon for controlling internal timing
t. , 36 are selectors.

FIG. 8 is a time chart for explaining a microinstruction execution sequence of the digital signal processor DSSP1 shown in FIG. 7. In the figure, 40 is a cycle timing composed of four-phase clocks, 41 is an address of the program counter PC1. Fetch stage timing indicating the stage of output and microinstruction input to the instruction register IR03, 42 is decode stage timing for decoding the microinstruction input to the instruction register IR14 by the instruction decoder 5, 43 is address calculation in the decode stage Of updating the unit AAU12, 44 is a timing of operation of the floating point multiplier FMPL24, and 45 is a floating point arithmetic logic unit FAL.
U28 is the timing of the calculation, 46 is the data bus D-
Reference numeral 47 is a timing for transferring data between registers via Bus 8, and 47 is a timing for reading / writing data from / to external data memory via the data register DR30.

FIG. 9 is a diagram showing the structure of a microinstruction having a 32-bit width per word, which is classified into 4 groups of the digital signal processor DSSP1 shown in FIG. 7, and 50 controls the instruction operating procedure. A sequence instruction to perform, 51 is a mode instruction indicating the mode setting / initial value setting of the status register SR17, the address calculator AAU12, and the DMA control unit 19, and 52 is mainly execution to the floating-point arithmetic logic operation unit FALU28 and accompanying parallel data transfer. Is a load instruction for executing an immediate load to an arbitrary register or data memory.

Next, the operation will be described. Hereinafter, for simplification, the names of the respective parts shall be the abbreviations used in the above description. First, the overall schematic operation will be described with reference to FIG. This signal processor is P-Bus 6 and D-Bus
8 has a separated structure, and inputs microinstructions to IR03, transfers microinstructions via P-Bus6, decodes microinstructions by instruction decoder 5, and executes instructions by D-Bus8, FMPL24, FALU28, etc. Parallel processing is performed by pipeline processing. Here, all the execution units including the D-Bus 8 and 2P-RAM 21 are register-based, that is, the input and output are all connected to the register. The access timing to this register is output at the leading edge of the machine cycle, and the register is set at the trailing edge of the machine cycle. That is, the data actually processed is not the content set in the register by the same microinstruction, but the content set in the register by one or more previous microinstructions. This is called a delay operation (delayed operation), and it is possible to operate each unit in parallel by dividing each unit in the arithmetic unit with a register. For example, the FMPL 24 always executes the floating point multiplication once every machine cycle in this processor. When inputting the operation data here, first, the data is set in DP0 22 and DP1 23 by the previous microinstruction, and 1
The multiplication result is obtained by taking out the contents set in P25 by one or more subsequent microinstructions. Since the data is held by DP0 22, DP1 23, and P25 until the contents are taken out, data input, multiplication, data output, and one multiplication that originally requires 3 microinstructions can be processed continuously. When performing, processing can be equivalently performed once for one microinstruction.

In the DSPP1, the FMPL24 and the FALU2
8 is connected via P25, FALU28 is ACC0
~ ACC329 is configured so that the contents of P25 can be accumulated. This is Louis Schirm's Ele
paper published in the December 20, 1979 issue of ctronics, "Packing a signal proc".
essor onto a single digit
Similar to the multiplier-accumulator pair shown in “al board”, filtering, FFT (Fast Fourier) is performed.
This is for executing one term of the multiply-accumulate operation, which is frequently used in the r. The sum of products follows, for example, the following formula.

[0007]

[Equation 1]

In this processor, the sum of products of one term is DP
0 22, data input to DP 1 23, FMPL 24
3 multiplications of the multiplication result set in P25 by the FALU 28 and the accumulation of ACC0 to ACC329 are required. Of course, when performing processing continuously,
Equivalently, the sum of products of one term can be realized once for one microinstruction. Naturally, once every 1 microinstruction,
In order to execute the sum of products of one term, DP is applied to the two input data corresponding to a _i and b _i in the above equation for each microinstruction.
It is necessary to input to 0 22 and DP1 23.
Therefore, the 2P-RAM 21 can supply these two input data, and the data read from the 2P-RAM 21 is D in order to avoid the bus competition to the D-Bus 8.
-A path for directly transferring to DP0 22 and DP1 23 without going through Bus8 is provided. Mainly this 2P-RAM2
For addressing 1-input 2-input data, the AAU 12 is provided with means for selecting and outputting 2 out of 9-bit width address data output via AR 0 13, AR 1 14 and AR 2 15. This AAU12 is 2P-RA
2 input data address from M21 and DR30, AR2
Only one output data address to the external data memory via 0 can be designated up to three addresses at the same time. Each addressing is AAU12
Only the so-called indirect addressing method using the address pointer set inside the
Increment, modulo, bit reverse, repeat, increment base address, increment value update, etc. are possible with respect to other AR1 14,
AR2 15 is only capable of simple increments. The AAU12 can perform address arithmetic only in the 9-bit natural binary format, and the external data memory address 12
When specifying the bits, the 9 bits are combined with the 3-bit memory page specified by PR11 to make 12 bits. On the other hand, FMPL24 and FALU28 are 12E
2P for performing operations in the normalized floating point format of 6
-RAM 21, DP0 22, DP1 23, P25,
ACC0 to ACC3 29, DR30, D-Bus8,
BI7 is all 18 bits wide and requires a special operation mode in order to calculate a special address initial value in FALU28. Therefore, AR0 13, AR1 1
4, AR2 15, AR20 and ACC0 to ACC3 2
There is no data compatibility between the operation result data set to 9.

The DMA controller 19 has a total of two channels of full-duplex serial I / O ports SI0 / 1 and SO0 / 1 3.
The data transfer between the two input / output data and the external data memory is executed independently of the micro instruction. DMA controller 19
For data transfer by D-Bus8, AR20, DR3
Since 0 is used, there is a risk of contention between the micro instruction operation controlled by the instruction decoder 5 and this internal resource. In order to avoid this, when the data is transferred by the DMA controller 19, the instruction decoder 5 is suspended for 6 machine cycles per word, and the operation by the micro instruction is stopped. To summarize the above, the DSSP 1 can execute the following operations in parallel within one microinstruction when executing a microinstruction. (1) Up to three types of 9-bit address calculation by AAU12. (2) 12E6 floating point multiplication by FMPL24. (3) 12E6 floating point arithmetic by FALU28. (4) Data transfer between the 2P-RAM 21 and the external data memory via the D-Bus 8 and DR 30. (5) 2-channel full-duplex serial I / O port SI
DMA data transfer between 0/1, SO0 / 1 32 and external data memory via D-Bus 8 and DR30.

Next, the microinstruction execution timing of the DSSP1 will be described with reference to FIG. The machine cycle 40 of the DSSP1 operates with the timing of four phases P0 to P3 obtained by dividing one machine cycle into four, and the cycle time of one machine cycle is nominally 50 nsec, which is a high speed. Therefore, the instruction mask R within one machine cycle
Micro instruction reading from OM2, micro instruction decoding by instruction decoder 5, FMPL
In reality, it is difficult to perform the three operations of executing instructions by internal resources such as 24 and FALU28. Therefore, in the DSPP1, these three are divided into stages for each one machine cycle, and a three-stage pipeline is configured to express a high speed operation. The following is executed in each stage of this three-stage pipeline. (1) Fetch stage 41 Micro instruction address output by PC1 and instruction mask R
Read micro instruction from OM2. And IR0
Micro instruction set to 3. (2) Decode stages 42 and 43 Micro instruction transfer from IR0 3 to IR1 4 and micro instruction decoding by the instruction decoder 5. And a set of program control modes. IR0
3 to P-Bus6 micro instruction transfer and AM9, A
Address operation of AAU12 via D10. (3) Execution stage 44, 45, 46, 47 Data calculation by the FMPL 24, FALU 28. D-B
Data transfer by us8. External data memory access etc. via AR20, DR30. This allows the DSSP
1 requires 3 machine cycles to execute 1 microinstruction. However, the pipeline method makes it possible to execute one micro instruction equivalently every one machine cycle. Therefore, there is a delay of 2 machine cycles from the time when the micro instruction is read from the instruction mask ROM 2 to the time when the instruction is actually executed. The internal bus is set to P-Bus 6, for the purpose of completely preventing timing conflict in internal resources.
Separated into D-Bus 8 and instruction mask ROM
This is why the 2 and 2P-RAMs 21 are separated. However, in the branching instruction, etc., the branch actually occurs at the decode stage of (2), so at that point IR0
The microinstruction being set to 3 will be executed. That is, the instruction written after the branch instruction is unconditionally executed. DSSP1 to avoid this
Then, while the branch instruction is being executed, the next instruction is automatically changed to NOP (no operation). This function aims at simplification of microinstruction description, but branching operation causes a loss of one machine cycle, and further D-
Indirect branching using Bus8 causes a loss of 2 machine cycles. Generally, considering the order of instruction description, unconditional branching of about 80% does not cause a problem even when the next instruction is executed, and the loss can be avoided, but this is impossible in the DSSP1.

Next, the microinstruction set of the DSSP1 will be described with reference to FIG. There are only four types of microinstruction sets: sequence, mode, operation, and load instruction. The sequence instruction controls a branch, a loop, and a subroutine call, and is mainly in charge of an instruction to the PC 1. Mode command is AAU12 selector 16, LC1
7, SR 18, and DMA control unit 19 are instructions for setting initial values and modes. The load instruction is an instruction to load an immediate value (18-bit width) into a register connected to D-Bus 8 via BI7. In the above microinstruction, the resource to be operated becomes constant depending on the instruction operation. On the other hand, as for the operation instruction, it is necessary to directly instruct all of the internal resources capable of operating in parallel. Therefore, the bit length of the arithmetic instruction becomes the maximum, and the DSPP1
Uses a 32-bit wide horizontal microinstruction. Here, the FMPL 24 is set to free run, and as described above, it is not directly instructed by an instruction. The operation designation to the FALU 28 is directly given by an instruction, and there are the following, for example. (1) Absolute value 1X1 (2) Sign correlation Sign (Y) · X (3) Addition X + Y (4) Subtraction XY (5) Maximum value MAX (X, Y) (6) Minimum value MIN (X, Y ) (7) Fixed to floating conversion FLT (X) (8) Floating to fixed conversion FIX (X) (9) Shift R1, L1 to L8 (10) Logical AND, OR, EOR, NOT (11) Mantissa addition X _M + Y _M (12) Mantissa subtraction X _E + Y _E The problem here is that the DSPP1 is based on floating-point arithmetic, and fixed-point arithmetic is used when performing logical / address arithmetic. As described above, the two are not compatible with each other. For example, when addressing the memory by the operation result, it is necessary to execute the instruction (8) in the FALU 28. Further, in general signal processing, data is not input / output in floating point very often, so it is necessary to execute the instructions (7) to (8) for each data input / output to perform data conversion.

The second problem is that bits are always truncated when normalizing floating point data.
Since the signal processing processor has a finite calculation accuracy, it naturally has a calculation error. However, if this is dealt with only by truncating bits, considering that the operation result always takes an absolute value, it becomes smaller than the true value, and the error is not randomized. This can be made an amount that can be easily ignored by increasing the operation word length, but there is a limit to this because a normal signal processor requires high-speed operation. Such a problem cannot be ignored particularly in the IIR type digital filter (recursive type) and image signal processing for performing inter-frame processing, and it is necessary to round (round) the processing result in the DSPP1 by a logical operation instruction or the like. Further, in a general signal processing algorithm, the calculation accuracy is often specified for each unit processing, and the accuracy does not always match the calculation word length of the signal processing processor. In this case, the format conversion of the calculation data is repeated using the FALU 28 for each unit processing.

The next problem is that the DSP 1 is limited to only the above-described product-sum operation as the operations that can be processed at high speed. This is sufficient for the FFT and FIR filters, which are typical conventional signal processing algorithms. However, in recent signal processing algorithms, vectors A → and B
High-speed processing is required for the degree of approximation of →, that is, distance calculation, for example, the one expressed by the following equation.

[0014]

[Equation 2]

Such an operation cannot be supported by the DSSP1, and all four arithmetic operations need to be decomposed and processed. Therefore, three operations must be performed separately to calculate one term. At this time, if the result of the above equation is calculated for each term, 3 × 3 = 9 instructions are required for each term due to delay, and the processing multiplicity is extremely reduced. Of course, by using the 2P-RAM 21 to save the intermediate result, the multiplicity can be increased by the classification of difference + square accumulation, but it becomes difficult to effectively use the limited data memory space,
Cannot handle multiple data.

Consider, for example, the case of performing a binary tree search as shown in FIG. Here, the input vector A → is set on the 2P-RAM 21, and the reference vector B → structured in a tree shape is assigned to each numbered node in the external data memory as shown in FIG. It is supposed to be arranged. The evaluation function representing the degree of approximation between the input vector A → and the reference vector B → is

[0017]

[Equation 3]

Then, the one that minimizes this result is selected in a binary tree shape at each stage, and finally the reference vector with the highest degree of approximation is obtained. At this time, the reference vector B of each stage
→ indicates 2n + 1 and 2n + when the current node number is n
The degree of approximation is calculated between the two reference vectors B → of the second node, and the node number of the reference vector to be compared in the next stage is calculated from the result. When this processing is realized by DSSP1, the following instruction step number is required.・ Input data conversion N + 2 steps ・ 1 vector evaluation value calculation 9N + 2 steps ・ Evaluation value rounding about 3 steps ・ Evaluation value comparison 4 steps ・ Next node reference vector address calculation about 9 steps 18N + 14 steps 1 stage + N + 2 steps Is an ideal value of 2N steps required for the evaluation value calculation, which is about 9 times the number of steps when the conversion between the address and the input data is unnecessary. Furthermore, in the case of such processing, the same processing is not continuous, so it is necessary to always be aware of the context of the instructions. For this reason, not only the processing efficiency is significantly deteriorated, but also the program creation becomes very complicated, which obviously causes a problem in terms of man-hours for software development.

[0019]

Since the conventional digital signal processor is constructed as described above, it has the following problems, for example. All the 2-input / 1-output operations cannot be read / written simultaneously from the data memory, and the efficiency is extremely deteriorated, for example, in the processing of vector data. -The mode of the indirect address cannot be specified immediately in the instruction, and the process must be interrupted every time the address mode is changed. -Since data transfer to an external module such as an external memory cannot be performed at high speed, it takes too much time for data transfer of other modules.

The present invention has been made to solve the above problems, and provides a digital signal processor capable of high-speed data transfer to other modules with a flexible and simple device configuration. The purpose is to

[0021]

A digital signal processor according to a first aspect of the present invention reads external data from a data input bus and external data memory provided externally, and external data to write data to the external data memory. A memory connection unit, a direct memory transfer bus connecting the read / write port of the external data memory connection unit and the external data memory, and the external data memory connection unit and the internal data memory via the direct memory transfer bus. And a direct memory transfer control unit for controlling input / output of data in block units.

In the digital signal processor according to the second aspect of the present invention, the address instruction to the external data memory connection section is given by k rows in a two-dimensional data address space of m rows × n columns (m and n are positive integers) × By designating the rectangular part of the L column (k and L are positive integers), designating an arbitrary start address for the external data memory, and performing two-dimensional data transfer between the external data memory and the internal data memory. It is something to do.

A digital signal processor according to a third aspect of the invention performs data input / output with an external data memory and internal arithmetic processing in parallel in units of rectangular blocks of k rows × L columns.

In the digital signal processor according to the fourth aspect of the present invention, the external data memory is divided into two, and when one of them is addressed, it is a high speed memory which completes read / write in one machine cycle, and when the other is addressed. Is a low-speed memory that waits until a read / write completion signal from the outside is detected.

[0025]

The digital signal processor of the first aspect of the present invention configured as described above controls the input / output of data in block units between the external data memory connection section and the internal data memory via the direct memory transfer bus. By doing so, high speed transfer of data becomes possible.

The digital signal processor according to the second aspect of the present invention having the above-described configuration provides the address designation to the external data memory connection unit in a two-dimensional data address space of m rows × n columns (m and n are positive integers). K rows × L columns (k,
L is a positive integer) indicating the rectangular part. Then, specify an arbitrary start address for the external data memory,
2 between the external data memory and the internal data memory
It is possible to perform dimensional data transfer.

The digital signal processor of the third invention configured as described above can perform data input / output and internal arithmetic processing in parallel.

In the digital signal processor according to the fourth aspect of the present invention configured as described above, the external data memory is divided into two, one of which is a high speed memory and the other of which is a low speed memory, thereby improving the efficiency of data transfer. .

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an outline of a digital signal processor according to the present invention.
0 is an external program bus for connecting to an external extended microinstruction memory, 101 is a writable instruction memory WCS mounted inside, and 102 is a microinstruction read from the external program bus 100 or the writable instruction memory WCS 101. And a sequence control unit for performing predetermined operation control in the instruction execution pipeline, 1
Reference numeral 03 designates an address generator for generating two input / one output addresses in parallel to the data memory, and 104 designates the two input
Three internal data buses, each having a width of 24 bits, provided for transferring one output data in parallel, 105
Selects one of the three internal data buses 104,
External data memory I / connected to external data bus 111
F and 106 are connected to three internal data buses 104,
An arithmetic unit 107 for performing a predetermined arithmetic operation includes an internal data memory M0, 10 provided with one read port and one read / write port and connected to the internal data bus 104.
Similarly, 8 is an internal data memory M1, 109 is a DMA control unit independently provided with an external data memory address generator and an internal data memory address generator, and 110 is an external data bus 111 and an internal data memory M0 107 to internal data memory M1. DM for performing DMA transfer with 108
A bus, 111 is an external data bus connected to an external extended data memory, 112 is a reset terminal for inputting an external reset signal to the sequence control unit 102, and 113 is an interrupt terminal for similarly inputting an external interrupt control signal. Is.

FIG. 2 is a block diagram showing a configuration example of the arithmetic unit 106 in FIG. 1. In the figure, 120 is an X- for transferring the data to be operated in the three internal data buses 104.
A bus, 121 is a Y-bus for transferring calculation data in the same manner,
122 is a Z-bus for transferring output data similarly, 123
Is a 24-bit word length barrel shifter B that shifts / rotates the input data by a predetermined number of bits in one machine cycle.
-SFT, 124 is a 24-bit word length arithmetic logic unit ALU for calculating a predetermined arithmetic logic operation or difference absolute value in 1 machine cycle, 125 is 24 in 1 machine cycle
Multipliers MPY and 126 that perform bit multiplication and output a 47-bit result temporarily hold the difference output of the arithmetic logic operation unit ALU124 and output it to the square input port of the multiplier MPY125 to calculate the difference square. Data pipeline registers DPR0 and 127 are barrel shifters B
-A multiplexer that selects one of the 24-bit output of the SFT123 or the 24-bit output of the arithmetic and logic unit ALU124 and outputs it to the data pipeline registers DPR1 and 129, and 128 is a data that temporarily holds the 47-bit output of the multiplier MPY125. Pipeline register D
PR2 and 129 are data pipeline registers DPR for temporarily holding the 24-bit output of the multiplexer 127.
1, 130 are data pipeline registers DPR1
Normalization in which one of 24-bit data from 129 or 47-bit data of the data pipeline register DPR2 128 is selected and input, a predetermined number of digits is adjusted in 1/2 machine cycle, and then output as 24-bit data For barrel shifter N-SFT, 131 is the 24-bit output of this normalizing barrel shifter N-SFT 130, 132
Is a 24-bit accumulation output from the working register W _r 135, 133 is an accumulation / rounding adder AU, 134 is a 24-bit result output of this accumulation / rounding adder AU133, and 135 is 24 bits × 8 words The working register W _{r of the} configuration, 136 is a flag output of the arithmetic and logic unit ALU, 137 is a flag check circuit for conditionally testing the flag output 136, and 138 is a 1-bit true / false determination result output from the flag check circuit. Sequentially store 24
× 1 bit conditional test shift register tcsr, 13
9 is L in the normalizing barrel shifter N-SFT130
It is a 1-bit carry that outputs the most significant bit shifted out in the SB direction, that is, when the right shift is instructed.

FIG. 3 is a diagram for explaining the relationship between the internal data memory and the internal data bus of the digital signal processor shown in FIG. 1, and 140 is the internal data memory M01.
A demultiplexer 141 outputs 24-bit data from the read port of 07 to one of the X-bus 120 to Y-bus 121. Reference numeral 141 represents the 24-bit data from the read port of the internal data memory M1 108 to the X-bus 12.
Demultiplexer for outputting to one of 0 to Y-bus 121, and 142 for Z-bus 122 to DMA bus 110
Select one of the write data of the internal data memory M
0-107 read / write port multiplexer, 143 is also a Z-bus 122 to DM.
A multiplexer 144 for selecting one of the write data of the A bus 110 and outputting it to the read / write port of the internal data memory M1 108 is a write address D
The address 147 and the internal data memory address I address 148 from the DMA control unit 109 are transferred to the internal data memory M.
0 107 to the internal data memory M1 108 and the read / write port of the address 2-2 selector 145 for selecting and outputting the internal data memory M1 108.
0 107 is the read port address S0 address, 146 is the read port address of the internal data memory M1 108 S1 address, 147 is the internal data memory M0107 to internal data memory M1 10
Write address for 8 and 148 for DMA bus 11
It is an I address which is an internal data memory address corresponding to data transferred from 0.

FIG. 4 is a diagram for explaining the configuration of the address generator 103 in FIG. 1, and 150 is the sequence controller 10.
2 is the display data indicated by the immediate value in the microinstruction input to 2; 151 is a 24 bit × 4 word address register AR; 152 is a 12 bit × 4 word index modification register IXR; 153 is an address register AR151 and X-bus. 120 data input / output paths,
154 is an index modification register IXR152 and X-
A data input / output path of the bus 120, 155 is an address adder having a 24-bit word length, 156 is an address generator AGU independently provided in three systems, and 157 is a write address pipe for delaying a write address of a 24-bit access by one machine cycle. The line registers DAPR3 and 158 are similarly write address pipeline registers DAPR4.
Is.

FIG. 5 is a diagram for explaining an instruction execution pipeline composed of 5 stages of the digital signal processor shown in FIG. 1. 160 is a machine cycle composed of 4 phases, 161 is a fetch stage, and 162 is a machine cycle. Is a decode stage, 163 is an address update timing in the latter half of the decode stage, 164 is a read stage, 165
Is an execution stage, 166 is a normalization timing in the first half of the write / accumulation stage, and 167 is a write / accumulation stage.

FIG. 6 is a diagram showing a part of an example of a microinstruction set of the digital signal processor shown in FIG.
In the figure, 170 is a load instruction, 171 is a branch instruction,
172 is a 1-source operation instruction, 173 is a 2-source operation instruction, 174 is a source instruction code, 175 is a destination instruction code, 176 is a source 0 instruction code, 17
Reference numeral 7 is a source 1 instruction code.

Next, the operation will be described. Hereinafter, similarly, the names of the respective parts use the abbreviations used in the above description. First, the overall schematic operation will be described with reference to FIG. The digital signal processor according to the present invention has a configuration in which the program bus 100 and the data bus 104 are separated as in the conventional example.
Micro instruction input to sequence control unit 102, data input / output of operation unit 106 via data bus 104, parallel generation of 2-input / 1-output data address by address generation unit 103, internal data memories M0 107, M1 1
08 or the external data memory I / F 105 accesses the external data memory in parallel by microinstructions. Further, the DMA control unit 109 causes the DMA bus 1
Independent of this internal operation via the internal data memory M0
107, M1108 and external data memory I / F 105
DMA transfer of data is executed between and. Here, each execution unit is register-based as in the conventional example. Since most of the instructions in this processor do not use the delayed operation format, the instruction input pipeline includes the data input / output stage. Therefore, for example, considering the case where the arithmetic unit 106 performs addition, the addition instruction may be executed by one-step micro instruction including the input and output. Therefore, even a program combining various operations can equivalently execute one micro instruction in one machine cycle. However, the instruction execution result can be used after three instruction steps corresponding to the difference in the number of stages from the read stage of the next instruction. In this processor, most of the results that need to be used immediately, including the meaning of avoiding the loss due to this, are compound operations and are handled by one instruction.
For this reason, most programs do not experience this loss. The data word lengths and formats of the arithmetic unit 106 and the address generation unit 103 are the same, and they are completely compatible. Therefore, in the processing such as table lookup and dictionary reference, the calculation result can be directly converted into the data memory address.

Next, the function of the arithmetic unit 106 will be described with reference to FIG. B-SFT123, ALU124, MPY1
All of 25 can operate in one machine cycle, and operate in the execution stage of the instruction execution pipeline stage. In the write / accumulation stage, which is the next stage, the number of digits is adjusted in the N-SFT 130, and the result 131
The Z- or output to the bus 122 writing to the data memory can again result 134 performs accumulation or rounding the contents 132 of W _r 135 is set to W _r 135 by AU133. Where DPR1 129, DP
R2 128 is a register that transfers the result to the next stage. With this configuration, for example, a composite operation is executed as follows. Sum of products: MPY125 → DPR2 128 → N-SFT1
30 → AU133 → W _r 135 Sum of absolute differences: ALU124 → MUX127 → DPR1
_{129 → SFT130 → AU133 → W r} 135 sum of squared differences: ALU124 → DPR0 126 → MPY
125 → DPR2 128 → N-SFT130 → AU1
33 → W _r 135 For the sum of squared differences, the delay operation is performed using DPR0 126. However, in most cases this instruction is only used consecutively, and the problem due to this can be ignored.

When rounding is performed, the following procedure is performed in this processor. MSB LSB (1) 0000 0000 1111 1111 1010 0111: DPR1 129 output 24 bits (2) 0000 0000 0000 0000 0000 1111 1111: N-SFT130 output (right 8 bit shift) 1: carry 139 (3) 0000 0000 0000 0001 0000 0000: AU133 output 134 Carry addition is performed. That is, the rounding process can be performed by setting the most significant bit of the data shifted out in the N-SFT 130 as the carry and performing the carry addition in the AU 133. Therefore, the output destination of the rounded result is limited to only W _r 135. Next, the flag check circuit 137 outputs a 1-bit flag indicating whether or not the condition is satisfied according to the condition code designated by the microinstruction, as the flag 136 as a result of the comparison operation by the ALU 124, and sequentially outputs to tcsr 138. I will set it. For example, when obtaining the maximum and minimum values of two-input data, the history of which is selected can be stored. A horizontal view of the contents set in the tcsr 138 from the MSB to the LSB corresponds to the index code in the binary tree search.

The structure of the internal data memory will be described with reference to FIG. Each of M0 107 and M1 108 is a 2-port RAM of 24 bits × 512 words, and the arithmetic unit 106
To output 2 input data in parallel to M0 107,
The output of the read port of M1 108 is selected by the selector 14
0, 141 to output to the X-bus 120 Y-bus 121. As for the address at this time, S0 address 145 is M0
107, S1 address 146 is output to M1 108. Further, in the case of vector addition, that is, in the case of targeting the source and destination data memories as in A → + B →→ C →, the M0 107 to M1 108 from the Z-bus 122 through the MUX 142 to MUX 143.
Data is written from the read / write port of. That is, bus contention does not occur in the internal operation.

The configuration of the address generator 103 will be described with reference to FIG. The address generator 103 is composed of three systems of AGU 156, which are in charge of the R0 address generator, the S1 generator, and the D address generator, respectively. Each AGU is provided with an AR151 of 24 bits × 4 words and an IXR152 of 12 bits × 4 words.
Two-dimensional address generation is possible by performing the combination of the addition of the three terms 52 and the displacement 150 by the address adder 155.

Although the operation of the AGU 156 is the decode stage, there is a stage difference of two stages from the write / accumulation stage, so the D address 147 is set to DAPR3.
157, DAPR4 158 delays the output by 2 machine cycles and then outputs from AGU 156. AR15
1, 1 and IXR 152 are each connected to the X-bus 120, and the data format is compatible with the arithmetic unit 106. Thus, for example, when performing a table lookup, the AR 151 is directly connected to the W _r 135 via the X-bus 120.
The data may be transferred to the S0 address 145 to the S1 address 146, and the address may be output.

The instruction execution pipeline of this processor will be described with reference to FIG. The instruction execution pipeline is composed of the following five stages per instruction. (1) Fetch stage 161 Program counter output and 1-word (48-bit width) microinstruction read. (2) Decode stage Micro instruction decode 162 and address update 16
3. (3) Read stage 164 Read source data such as data memory or register via X-bus 120 and Y-bus 121. (4) Execution stage 165 Calculation by B-SFT123, ALU124, MPY125. (5) Write / accumulation stage Normalization 166 and AU 133 by N-SFT 130
Round / accumulate by or write to data memory 167 via Z-bus 122. Write (5) here /
AU133 or Z-Bus 122 in accumulation stage
Sharing the timing 167 of writing data via the output of the AU 133 is set to W _r 135 only,
This is because there is an exclusive relationship that the AU 133 is not used when the Z-bus 122 is used. By executing the instructions according to the above sequence, it becomes almost unnecessary to create a program considering a complicated delay, and an efficient microprogram can be created even by using a high-level language compiler.

The microinstruction of this processor is shown in FIG.
As shown in (1), it is a 1-word horizontal type instruction set with a word length of 48 bits. In this instruction set, a function code that defines a combination of resource operations of each stage is used for each instruction instead of instructing internal resources that can operate simultaneously in parallel. This simplifies the description of microinstructions. This instruction set is roughly divided into a load 170, a branch 171, a 1-source operation 172, and a 2-source operation 173. Source code 174, destination code 175, source 0 code corresponding to the function code and controlling the source / destination. 176 and source 1 code 177 are set. Each of these codes is an addressing instruction code for the corresponding AGU 156 in the address generator 103 when the data memory is targeted. This identification is done by the resource code. With this instruction set, for example, the addressing mode can be switched and the settings such as the normalized shift value can be changed for each operation instruction, and it is possible to describe with a minimum loss even when programming a complicated signal processing algorithm.

For example, when executing the binary tree search shown in FIG. 10 as in the conventional example, the processor may be programmed to calculate the degree of approximation as follows. rep N {subaa sc0, sc1, wr _x } N times repeated sc0: Input vector address control sc1: Reference vector address control wr _x : Working register designation The number of machine cycles required for this is N + 1 cycles, and this can be repeated twice. For example, the degree of approximation of the reference vector in directions 0 and 1 can be obtained. Next, the process of determining the one with the highest degree of approximation and obtaining the node number of the next stage can be described as follows. cmp · ge wr0, wr1 are compared, and the result is set to tcsr138 Initialize the address pointer of mvr ar00, ar01} sc0, sc1 mvr ar10, ar11 adsl 1, tscr, wr2 Calculate the secondary node reference vector address (2n + 1: 1 is (preset to wr2) nop nop mvr wr2 ar12 Total 7 instructions require 2N + 9 machine cycles per stage. It is clear that this is a highly efficient process that almost matches the ideal value, and the program is simple.

In the above embodiment, the word length is 24 bits and the address space is 16 MW (24 bits). However, other word lengths and data formats may be used. Further, although the binary tree search is described in the above embodiment, other signal processing algorithms also have the same effect as the above embodiment. Further, it is apparent that the detailed specifications of the above-mentioned embodiment are not related to the essence of the present invention and do not limit the content of the present invention.

[0045]

As described above, according to the first and third aspects of the present invention, it is possible to judge the input / output of data in block units between the external data memory connection section and the internal data memory via the direct memory transfer bus. By doing so, high-speed data transfer becomes possible, and the data transmission efficiency to the external memory can be improved. According to the second aspect of the invention, the two-dimensional data transfer between the external data memory and the internal data memory can be performed by designating an arbitrary rectangular portion in the two-dimensional data address space for the external data memory. It is possible. (See p.13) According to the fourth invention, the efficiency of data transfer is improved by dividing the external data memory into two parts, one of which is a high speed memory and the other of which is a low speed memory. Therefore, the data transmission efficiency to the external memory can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an arithmetic unit in FIG. 1 of the present invention.

FIG. 3 is a diagram for explaining the internal data memory configuration in FIG. 1 of the present invention.

FIG. 4 is a diagram showing a configuration of an address generation unit in FIG. 1 of the present invention.

5 is a diagram illustrating instruction execution timing of the digital signal processor shown in FIG. 1 of the present invention.

6 is a diagram showing an example of a micro instruction set of the digital signal processor shown in FIG. 1 of the present invention.

FIG. 7 is a block diagram showing a configuration of a DSSP1 which is an example of a conventional digital signal processor.

8 is a diagram illustrating instruction execution timing of the DSSP1 of FIG.

FIG. 9 is a diagram showing a microinstruction set of DSSP1.

FIG. 10 is a diagram illustrating an operation of a binary tree search.

11 is a diagram showing a sequence of arrangement of reference vectors in FIG. 10 in a data memory.

[Explanation of symbols]

100 program bus, 101 WCS, 102 sequence control unit, 103 address generation unit, 104 data bus, 105 external data memory I / F, 106
Arithmetic unit, 107 M0, 108 M1, 109 DMA
Control unit, 110 DMA bus, 111 external data bus,
120 X-bus, 121 Y-bus, 122 Z-bus. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 17/10 15/78 510 F

Claims (4)

[Claims] 1. A plurality of data input buses for transmitting input data signals, an internal data memory for receiving the respective input data signals from the plurality of data input buses, and storing the input data signals, and the internal data. A digital signal processor comprising: an arithmetic unit that receives an input data signal output from a memory and performs arithmetic processing; and an address generation unit that controls the operations of the arithmetic unit and the data memory. An externally provided external data memory that reads data from the plurality of data input buses, an external data memory connection unit that writes data to the external data memory, and a read / write port of the external data memory connection unit A direct memory transfer bus for connecting to the external data memory, and a direct memory for controlling input / output of data in block units between the external data memory connection unit and the internal data memory via the direct memory transfer bus. A digital signal processor comprising a transfer control unit. 2. The direct memory transfer control unit gives address instructions to the external data memory connection unit in k rows × L columns in a two-dimensional data address space of m rows × n columns (m and n are positive integers). Instructing a rectangular part (where k and L are positive integers), instructing an arbitrary start address for the external data memory, and performing two-dimensional data transfer between the external data memory and the internal data memory. A digital signal processor according to claim 1. 3. The direct memory transfer control unit performs data input / output with the external data memory and internal arithmetic processing in parallel in units of rectangular blocks of k rows × L columns. The digital signal processor according to item 1. 4. The external data memory connection section divides the external data memory into two, and when one of them is addressed, a high-speed memory that completes read / write in one machine cycle is completed, and when the other is addressed, 2. The digital signal processor according to claim 1, wherein the digital signal processor is a low-speed memory that waits until an external read / write completion signal is detected.